Philips BSP121 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSP121

N-channel enhancement mode
vertical D-MOS transistor

Product specification
Supersedes data of April 1995
File under Discrete Semiconductors, SC13b

1998 Apr 01

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

DESCRIPTION

N-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope and
designed for use as a line current
interrupter in telephone sets and for
application in relay, high-speed and
line-transformer drivers.

FEATURES

• Direct interface to C-MOS, TTL,
etc.

• High-speed switching

• No secondary breakdown

QUICK REFERENCE DATA

Drain source voltage V
Gate-source voltage (open drain) ±V
Drain current (DC) I
Total power dissipation up to

T

=25°CP

amb

Drain-source on-resistance

= 400 mA; VGS= 10 V R

I

D

Transfer admittance

= 400 mA; VDS= 25 V  Yfs

I

D

PINNING - SOT223

1 = gate
2 = drain
3 = source
4 = drain

DS

GSO

D

tot

DS(on)

BSP121

max. 200 V
max. 20 V
max. 350 mA

max. 1.5 W

typ.
max.

min.
typ.

4.5

6.0ΩΩ

200
350mSmS

PIN CONFIGURATION

Marking code

BSP121

handbook, halfpage

Top view

Fig.1 Simplified outline and symbol.

4

123

MAM054

d

g

s

1998 Apr 01 2

Philips Semiconductors Product specification

N-channel enhancement mode vertical

BSP121

D-MOS transistor

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Drain-source voltage V
Gate-source voltage (open drain) ±V
Drain current (DC) I
Drain current (peak) I

DS

GSO
D
DM

Total power dissipation up to

T

=25°C (note 1) P

amb

Storage temperature range T
Junction temperature T

tot
stg
j

THERMAL RESISTANCE

From junction to ambient (note 1) R

thj-a

Note

1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead

2

min. 6 cm

.

max. 200 V
max. 20 V
max. 350 mA
max. 1.2 A

max. 1.5 W

−65 to + 150 °C

max. 150 °C

= 83.3 K/W

1998 Apr 01 3

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

CHARACTERISTICS

=25°C unless otherwise specified

T

j

Drain-source breakdown voltage

ID=10µA; VGS=0 V

Drain-source leakage current

V

= 160 V; VGS=0 I

DS

= 60 V; VGS=0 I

V

DS

Gate-source leakage current

± V

= 20 V; VDS=0 ±I

GS

Gate threshold voltage

= 1 mA; VDS= V

I

D

Drain-source on-resistance

= 400 mA; VGS= 10 V R

I

D

Transfer admittance

= 400 mA; VDS= 25 V  Yfs

I

D

GS

(BR)DSS

DSS
DSS

GSS

V

GS(th)

DS(on)

BSP121

min. 200 V

max. 1.0 µA
max. 200 nA

max. 100 nA

min.
max.

typ.
max.

min.
typ.

0.8

2.8VV

4.5

6.0ΩΩ

200
350mSmS

Input capacitance at f = 1 MHz

= 25 V; VGS=0 C

V

DS

Output capacitance at f = 1 MHz

= 25 V; VGS=0 C

V

DS

Feedback capacitance at f = 1 MHz

= 25 V; VGS=0 C

V

DS

Switching times (see Figs 2 and 3)

= 250 mA; VDD= 50 V; VGS= 0 to 10 V t

I

D

iss

oss

rss

on

t

off

typ.
max.

typ.
max.

typ.
max.

typ.
max.

typ.
max.

4560pF

pF

1525pF

pF

3.510pF
pF

510pF

pF

1520ns

ns

1998 Apr 01 4