Philips BSP120 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSP120

N-channel enhancement mode vertical D-MOS transistor

Product speciﬁcation File under Discrete Semiconductors, SC13b

April 1995

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode vertical D-MOS transistor

DESCRIPTION

N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use as a line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers.

FEATURES

• Direct interface to C-MOS, TTL, etc.

• High-speed switching

• No secondary breakdown

QUICK REFERENCE DATA

Drain-source voltage V Drain-current (DC) I Drain-source ON-resistance

ID= 250 mA; VGS= 10 V R

Gate threshold voltage V

PINNING - SOT223

1 = gate 2 = drain 3 = source 4 = drain

Marking code

BSP120

DS

D

DS(on)

GS(th)

BSP120

max. 200 V max. 250 mA

typ. max.

max. 2.8 V

712Ω

Ω

PIN CONFIGURATION

handbook, halfpage

Top view

Fig.1 Simplified outline and symbol.

4

123

MAM054

d

g

s

April 1995 2

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode vertical

BSP120

D-MOS transistor

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Drain-source voltage V Gate-source voltage (open drain) ±V Drain current (DC) I Drain current (peak) I Total power dissipation up to T

=25°C (note 1) P

amb

Storage temperature range T Junction temperature T

DS

GSO D DM

tot stg j

THERMAL RESISTANCE

From junction to ambient (note 1) R

th j-a

Note

1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead min. 6 cm

2

.

max. 200 V max. 20 V max. 250 mA max. 800 mA max. 1.5 W

−65 to + 150 °C

max. 150 °C

= 83.3 K/W

CHARACTERISTICS

=25°C unless otherwise speciﬁed

T

j

Drain-source breakdown voltage

I

=10µA; VGS=0 V

D

Drain-source leakage current

VDS=160 V; VGS=0 I

Gate-source leakage current

V

= 20 V; VDS=0 I

GS

Drain-source ON-resistance (see Fig.4)

ID= 250 mA; VGS= 10 V R

Gate threshold voltage

= 1 mA; VGS=V

I

D

DS

Transfer admittance

= 250 mA; VDS= 15 V  Yfs

I

D

Input capacitance at f = 1 MHz;

= 10 V; VGS=0 C

V

DS

(BR)DSS

DSS

GSS

DS(on)

V

GS(th)

iss

min. 200 V

max. 1.0 µA

max. 100 nA

typ. max.

min. max.

min. typ.

typ. max.

712Ω

Ω

0.8

2.8VV

125 250mSmS

4565pF

pF

Output capacitance at f = 1 MHz;

= 10 V; VGS=0 C

V

DS

April 1995 3

oss

typ. max.

2030pF

pF

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode vertical D-MOS transistor

Feedback capacitance at f = 1 MHz;

= 10 V; VGS= 0 C

V

DS

Switching times (see Figs 2 and 3)

I

= 250 mA; VDD= 50 V;

D

VGS= 0 to 10 V t

handbook, halfpage

10 V

0 V

50 Ω

VDD = 50 V

I

D

MBB691

rss

on

t

off

handbook, halfpage

INPUT

OUTPUT

typ. max.

10 %

t

on

90 %

510pF

36ns

1520ns

90 %

BSP120

pF

ns

t

off

10 %

MBB692

3

10

handbook, halfpage

I

D

(mA)

2

10

Fig.2 Switching time test circuit.

VGS = 10 V

5 V

4 V

81012

R

DSon

Fig.4 Tj=25°C; typical values.

MDA738

(Ω)

Fig.3 Input and output waveforms.

8

VGS (V)

MDA739

handbook, halfpage

144 6

1

I

D

(A)

0.8

0.6

0.4

0.2

0

010

246

Fig.5 Tj=25°C; VDS= 10 V; typical values.

April 1995 4