Philips BSP110 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BSP110
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope and
designed for use in telephone ringer
circuits and for application in relay,
high-speed and line transformer
drivers.
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No secondary breakdown
PINNING - SOT223
1 = gate
2 = drain
3 = source
4 = drain
QUICK REFERENCE DATA
Drain-source voltage V
Drain source voltage
(non-repetitive peak; tp≤ 2 ms) V
Gate-source voltage (open drain) ± V
Drain current (DC) I
Total power dissipation up to T
Drain-source ON-resistance
ID= 200 mA; VGS=10V R
Transfer admittance
= 200 mA; VDS=15V Yfs
I
D
=25°CP
amb
DS
DS(SM)
GSO
D
tot
DS(on)
BSP110
max. 80 V
max. 100 V
max. 20 V
max. 325 mA
max. 1.5 W
typ.
max.
min.
typ.
4.57Ω
Ω
75
150mSmS
MARKING CODE
BSP110
PIN CONFIGURATION
handbook, halfpage
Top view
4
123
MAM054
d
g
s
Fig.1 Simplfied outline and symbol.
April 1995 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP110
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage V
DS
Drain-source voltage
(non-repetitive peak; t
Gate-source voltage (open drain) ± V
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T
Storage temperature range T
Junction temperature T
≤ 2 ms) V
p
=25°C (note 1) P
amb
DS(SM)
GSO
D
DM
tot
stg
j
THERMAL RESISTANCE
From junction to ambient (note 1) R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead min.
2
6 cm
.
max. 80 V
max. 100 V
max. 20 V
max. 325 mA
max. 650 mA
max. 1.5 W
−65 to + 150 °C
max. 150 °C
= 83.3 K/W
CHARACTERISTICS
=25°C unless otherwise specified
T
j
Drain-source breakdown voltage
=10µA; VGS=0 V
I
D
Drain-source leakage current
V
= 60 V; VGS=0 I
DS
Gate-source leakage current
V
= 20 V; VDS=0 I
GS
Gate threshold voltage
ID= 1 mA; VDS=V
GS
Drain-source ON-resistance (see Fig.4)
= 150 mA; VGS=5V R
I
D
ID= 200 mA; VGS=10V R
Transfer admittance
ID= 200 mA; VDS=5V | Yfs|
Input capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
(BR) DSS
DSS
GSS
I
GS(th)
DS(on)
DS(on)
iss
min. 80 V
max. 1.0 µA
max. 100 nA
min.
max.
typ.
max.
typ.
max.
min.
typ.
typ.
max.
0.8
2.8VV
710Ω
Ω
4.57Ω
Ω
75
150mSmS
1530pF
pF
April 1995 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
Output capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
Feedback capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
Switching times (see Figs 2 and 3)
I
= 200 mA; VDD=50V;
D
VGS= 0 to 10 V t
BSP110
oss
rss
on
t
off
typ.
max.
typ.
max.
typ.
max.
typ.
max.
1320pF
pF
36pF
pF
25ns
ns
510ns
ns
handbook, halfpage
10 V
0 V
VDD = 50 V
I
D
50 Ω
MBB691
Fig.2 Switching time test circuit.
handbook, halfpage
INPUT
OUTPUT
Fig.3 Input and output waveforms.
10 %
t
on
90 %
90 %
10 %
t
off
MBB692
April 1995 4
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