Philips BSP107 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BSP107
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
FEATURES
• Direct interface to C-MOS, TTL,
etc. due to low threshold voltage
• High-speed switching
• No secondary breakdown.
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope.
Intended for use as a line current
interruptor in telephone sets and for
applications in relay, high-speed and
line transformer driver switching.
PINNING - SOT223
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain
QUICK REFERENCE DATA
SYMBOL PARAMETER MAX. UNIT
V
DS
V
GS(th)
I
D
R
DS(on)
drain-source voltage (DC) 200 V
gate-source threshold voltage 2.4 V
drain current (DC) 200 mA
drain-source on-state resistance 28 Ω
handbook, halfpage
123
Top view
BSP107
4
g
MAM054
d
s
Fig.1 Simplified outline and symbol.
April 1995 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP107
D-MOS transistor
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
±V
GSO
I
D
I
DM
P
tot
T
stg
T
j
THERMAL RESISTANCE
SYMBOL PARAMETER VALUE UNIT
R
th j-a
Note
1. Device mounted on an epoxy printed circuit board, 40 mm × 40 mm × 1.5 mm. Mounting pad for the drain lead
minimum 6 cm
drain-source voltage − 200 V
gate-source voltage open drain − 20 V
drain current DC − 200 mA
drain current peak − 350 mA
total power dissipation up to T
=25°C − 1.5 W
amb
storage temperature range −65 150 °C
operating junction temperature − 150 °C
from junction to ambient (note 1) 83.3 K/W
2
.
April 1995 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP107
D-MOS transistor
CHARACTERISTICS
T
=25°C unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
I
DSS
I
DSX
±I
GSS
V
GS(th)
R
DS(on)
R
DS(on)
| Y
| transfer admittance ID= 250 mA
fs
C
iss
C
oss
C
rss
drain-source breakdown voltage VGS=0
ID=10µA 200 −−V
drain-source leakage current VDS= 130 V
VGS=0 −−30 nA
drain-source leakage current VDS=70V
VGS= 0.2 V −−1µA
gate-source leakage current ± VGS=15V
VDS=0 −−10 nA
gate threshold voltage ID=1 mA
VDS=V
GS
drain-source on-resistance ID=20mA
VGS= 2.6 V − 20 28 Ω
drain-source on-resistance ID= 150 mA
VGS=10V − 14 −Ω
VDS= 15 V 90 180 − mS
input capacitance VDS=10V
VGS=0
f = 1 MHz − 50 65 pF
output capacitance VDS=10V
VGS=0
f = 1 MHz − 16 25 pF
feedback capacitance VDS=10V
VGS=0
f = 1 MHz − 410pF
0.8 − 2.4 V
Switching times (see Figs 2 and 3)
t
on
switching-on time ID= 250 mA
V
VGS=0−10 V − 210ns
t
off
switching-off time ID= 250 mA
VDD=50V
VGS=0−10 V − 520ns
April 1995 4
DD
=50V
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