DISCRETE SEMICONDUCTORS
DATA SH EET
BSP100
N-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of November 1994
File under Discrete Semiconductors, SC13b
1997 Jun 20
Philips Semiconductors Product specification
N-channel enhancement mode
vertical D-MOS transistor
FEATURES
• High-speed switching
• No secondary breakdown
• Very low on-resistance.
APPLICATIONS
• Low-loss motor and actuator drivers
• Power switching.
DESCRIPTION
N-channel enhancement mode vertical D-MOS transistor
in a plastic SOT223 SMD package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT223
PIN SYMBOL DESCRIPTION
1 g gate
2 d drain
3 s source
4 d drain
handbook, halfpage
123
Top view
4
g
MAM054
BSP100
d
s
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
V
V
I
D
R
P
DS
SD
GSO
GSth
DSon
tot
drain-source voltage (DC) − 30 V
source-drain diode forward voltage IS= 1.25 A − 1.2 V
gate-source voltage (DC) open drain −±20 V
gate-source threshold voltage ID= 1 mA; VDS=V
GS
1 2.8 V
drain current (DC) − 3.5 A
drain-source on-state resistance ID= 2.2 A; VGS=10V − 0.1 Ω
total power dissipation Ts= 100 °C − 5W
1997 Jun 20 2
Philips Semiconductors Product specification
N-channel enhancement mode
BSP100
vertical D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
Notes
1. Pulse width and duty cycle limited by maximum junction temperature.
2. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm
drain-source voltage (DC) − 30 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) Ts≤ 100°C − 3.5 A
peak drain current note 1 − 14 A
total power dissipation Ts= 100 °C − 5W
T
=25°C; note 2 − 1.65 W
amb
storage temperature −65 +150 °C
operating junction temperature − 150 °C
source current (DC) Ts≤ 100°C − 2A
peak pulsed source current note 1 − 7A
2
.
2.0
handbook, halfpage
P
tot
(W)
1.6
1.2
0.8
0.4
0
0 200
50 100 150
T
Fig.2 Power derating curve.
amb
MLB885
(°C)
2
10
handbook, halfpage
I
D
(A)
10
1
P
−1
10
−2
10
−1
10
δ =0.01.
Solder point temperature Ts= 100 °C.
(1) R
DSon
limitation.
(1)
δ
t
p
T
1
Fig.3 SOAR.
MLB834
tp =
10 µs
DC
1 ms
2
(V)
10
V
DS
t
p
=
T
t
10
1997 Jun 20 3
Philips Semiconductors Product specification
N-channel enhancement mode
BSP100
vertical D-MOS transistor
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
R
th j-s
Note
1. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm2.
CHARACTERISTICS
=25°C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GSth
I
DSS
I
GSS
I
Don
R
DSon
y
forward transfer admittance VDS= 20 V; ID= 2.2 A 2 4.5 − S
fs
C
iss
C
oss
C
rss
Q
G
Q
GS
Q
GD
Switching times
t
on
t
off
thermal resistance from junction to ambient note 1 75 K/W
thermal resistance from junction to soldering point 10 K/W
drain-source breakdown voltage VGS= 0; ID=10µA30−−V
gate-source threshold voltage VGS=VDS; ID= 1 mA 1 − 2.8 V
drain-source leakage current VGS= 0; VDS=24V −−100 nA
gate leakage current VGS= ±20 V; VDS=0 −−±100 nA
on-state drain current VGS= 10 V; VDS=1V 3.5 −−A
V
= 4.5 V; VDS=5V 2 −−A
GS
drain-source on-state resistance VGS= 4.5 V; ID=1A − 0.11 0.2 Ω
V
= 10 V; ID= 2.2 A − 0.08 0.1 Ω
GS
input capacitance VGS= 0; VDS= 20 V; f = 1 MHz − 250 − pF
output capacitance VGS= 0; VDS= 20 V; f = 1 MHz − 140 − pF
reverse transfer capacitance VGS= 0; VDS= 20 V; f = 1 MHz − 50 − pF
total gate charge VGS= 10 V; VDS=15V; ID= 2.3 A − 10 30 nC
gate-source charge VGS= 10 V; VDS=15V; ID= 2.3 A − 1 − nC
gate-drain charge VGS= 10 V; VDS=15V; ID= 2.3 A − 2.5 − nC
turn-on time VGS= 0 to 10 V; VDD=20V;
− 15 40 ns
ID= 1 A; RL=20Ω
turn-off time VGS=10to0V; VDD=20V;
− 25 75 ns
ID= 1 A; RL=20Ω
Source-drain diode
V
SD
source-drain diode forward
VGD= 0; IS= 1.25 A −−1.2 V
voltage
t
rr
reverse recovery time IS= 1.25 A; di/dt = 100 A/µs − 35 100 ns
1997 Jun 20 4