Philips BSN304A, BSN304 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BSN304; BSN304A
N-channel enhancement mode
vertical D-MOS transistors
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistors
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No secondary breakdown.
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a TO-92
variant envelope, intended for use as
a line current interruptor in telephone
sets and for applications in relay,
high-speed and line transformer
drivers.
PINNING - TO-92 variant
PIN DESCRIPTION
BSN304
1 gate
2 drain
3 source
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX.
V
DS
I
D
P
tot
±V
GSO
R
DS(on)
drain-source voltage − 300 V
DC drain current − 250 mA
total power dissipation up to T
gate-source voltage open drain − 20 V
drain-source
on-resistance
V
GS(off)
gate-source cut-off
voltage
handbook, halfpage
BSN304; BSN304A
= 25 °C − 1W
amb
ID = 250 mA;
VGS = 10 V
ID = 1 mA;
= V
V
GS
DS
1
2
3
g
MAM146
− 8 Ω
0.8 2 V
d
s
BSN304A
1 source
2 gate
3 drain
Fig.1 Simplified outline and symbol.
April 1995 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSN304; BSN304A
D-MOS transistors
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
±V
GSO
I
D
I
DM
P
tot
T
stg
T
j
THERMAL RESISTANCE
SYMBOL PARAMETER THERMAL RESISTANCE
R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead
minimum 10 mm x 10 mm.
drain-source voltage − 300 V
gate-source voltage open drain − 20 V
DC drain current − 250 mA
peak drain current − 1A
total power dissipation up to T
= 25 °C; note 1 − 1W
amb
storage temperature −65 +150 °C
operating junction temperature − 150 °C
from junction to ambient; note 1 125 K/W
STATIC CHARACTERISTICS
= 25 °C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
±I
GSS
V
GS(th)
R
DS(on)
I
DSS
Y
transfer admittance ID = 250 mA; VDS = 25 V 200 380 − mS
fs
C
iss
drain-source breakdown voltage ID = 10 µA; VGS = 0 300 −−V
gate-source leakage current ±VGS = 20 V; VDS = 0 −−100 nA
gate-source threshold voltage ID = 1 mA; VDS = V
GS
0.8 − 2V
drain-source on-resistance ID = 250 mA; VGS = 10 V − 6.7 8 Ω
I
= 20 mA; VGS = 2.4 V − 7.9 14 Ω
D
drain-source leakage current VDS = 240 V; VGS = 0 −−100 nA
input capacitance VDS = 25 V; VGS = 0;
− 57 90 pF
f = 1 MHz
C
oss
output capacitance VDS = 25 V; VGS = 0;
− 15 30 pF
f = 1 MHz
C
rss
feedback capacitance VDS = 25 V; VGS = 0;
− 2.6 15 pF
f = 1 MHz
Switching times (see Figs 2 and 3)
t
on
turn-on time ID = 250 mA; VDD = 50 V;
− 2.5 10 ns
VGS = 0 to 10 V
t
off
turn-off time ID = 250 mA; VDD = 50 V;
− 17 30 ns
VGS = 10 to 0 V
April 1995 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistors
handbook, halfpage
10 V
0 V
50 Ω
VDD = 50 V
I
D
MSA631
handbook, halfpage
INPUT
OUTPUT
BSN304; BSN304A
90 %
10 %
90 %
t
on
10 %
t
off
MBB692
1.2
handbook, halfpage
P
tot
(W)
0.8
0.4
0
0
Fig.2 Switching times test circuit.
MRC238
50 100 200150
T
amb
(°C)
Fig.3 Input and output waveforms.
150
handbook, halfpage
C
(pF)
100
50
0
0
VGS = 0; f = 1 MHz; Tj = 25 °C.
525
C
C
C
10 15 20
MRC234
iss
oss
rss
VDS (V)
Fig.4 Power derating curve.
April 1995 4
Fig.5 Capacitance as a function of drain-source
voltage, typical values.
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