Philips BS208 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BS208
P-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
P-channel enhancement mode vertical
D-MOS transistor
FEATURES
• Direct interface to C-MOS
• High-speed switching
• No secondary breakdown.
DESCRIPTION
P-channel enhancement mode
vertical D-MOS transistor in a TO-92
envelope. Intended for use in relay,
high-speed and line transformer
drivers.
PINNING - TO-92
PIN DESCRIPTION
1 source
2 gate
3 drain
handbook, halfpage
1
2
3
g
MAM149
Fig.1 Simplified outline and symbol.
BS208
d
s
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DS
V
GSO
Y
forward transfer admittance ID= −200 mA; VDS= −25 V 100 200 − mS
fs
I
D
R
DS(on)
P
tot
drain-source voltage (DC) −−−200 V
gate-source voltage (DC) open drain −−±20 V
drain current (DC) −−−0.2 A
drain-source on-state resistance VGS= −10 V; ID= −200 mA − 10 14 Ω
total power dissipation T
=25°C −−0.83 W
amb
April 1995 2
Philips Semiconductors Product specification
P-channel enhancement mode vertical
BS208
D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
−V
DS
±V
GSO
−I
D
−I
DM
P
tot
T
stg
T
j
THERMAL RESISTANCE
R
thj-a
drain-source voltage − 200 V
gate-source voltage open drain − 20 V
drain current DC − 0.2 A
drain current peak value − 0.6 A
total power dissipation T
=25°C − 0.83 W
amb
storage temperature range −65 +150 °C
junction temperature − 150 °C
SYMBOL PARAMETER MAX. UNIT
from junction to ambient 150 K/W
handbook,
P
(W)
1
tot
0.8
0.6
0.4
0.2
0
0 50 100 200
150
T
amb
Fig.2 Power derating curve.
MDA690
(°C)
April 1995 3
Philips Semiconductors Product specification
P-channel enhancement mode vertical
BS208
D-MOS transistor
CHARACTERISTICS
T
=25°C unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
−V
(BR)DSS
drain-source breakdown
voltage
−I
DSS
−I
DSS
−I
GSS
−V
GS(th)
drain-source leakage current −VDS= 130 V
drain-source leakage current −VDS=70V
gate-source leakage current −VGS=20V
gate-source threshold
voltage
R
DS(on)
Y
transfer admittance −VDS=25V
fs
C
iss
C
oss
C
rss
t
on
t
off
drain-source on-resistance −VGS=10V
input capacitances note 1 − 55 90 pF
output capacitance note 1 − 20 30 pF
feedback capacitance note 1 − 515pF
turn-on time note 2 − 510ns
turn-off time note 2 − 20 30 ns
−VGS=0
−ID=10µA
VGS=0
−VGS= 0.2 V
VDS=0
VGS=V
DS
−ID=1mA
−ID= 200 mA
−ID= 200 mA
200 − -V
−−1µA
−−25 µA
−−100 nA
0.8 − 2.8 V
−−14 Ω
100 200 − mS
Notes
1. Measured at f = 1 MHz; −V
= 25 V; VGS=0.
DS
2. −VGS= 0 to 10 V; −ID= 250 mA; −VDD=50V.
handbook, halfpage
0 V
−10 V
50 Ω
VDD = −50 V
I
D
MBB689
Fig.3 Switching times test circuit.
handbook, halfpage
INPUT
OUTPUT
10 %
90 %
90 %
t
on
t
off
MBB690
Fig.4 Input and output waveforms.
10 %
April 1995 4
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