Page 1
DATA SH EET
DISCRETE SEMICONDUCTORS
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
Product specification
Supersedes data of April 1991
1996 Aug 01
Page 2
NXP Semiconductors Product specification
Fig.1 Simplified outline (SOT143B)
and symbol; BF998.
Marking code: MOp.
handbook, halfpage
s,b
d
g
1
g
2
43
21
Top view MAM039
handbook, halfpage
s,b
d
g
1
g
2
MAM040
34
12
Top view
Fig.2 Simplified outline (SOT143R)
and symbol; BF998R.
Marking code: MOp.
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
FEATURES
Short channel transistor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
DESCRIPTION
Depletion type field effect transistor in a plastic
microminiature SOT143B or SOT143R package with
source and substrate interconnected. Th e transistors are
protected against excessive input voltage surges by
integrated back-to-back diodes between ga tes and
source.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handlin g.
PINNING
PIN SYMBOL DESCRIPTION
1s, bsource
2 d drain
3g
4g
gate 2
2
gate 1
1
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
V
DS
I
D
P
tot
forward transfer admittance 24 mS
y
fs
C
ig1-s
C
rs
drain-source voltage 12 V
drain current 30 mA
total power dissipation 200 mW
input capacitance at gate 1 2.1 pF
reverse transfer capacitance f = 1 MHz 25 fF
F noise figure f = 800 MHz 1 dB
T
j
1996 Aug 01 2
operating junction temperature 150 C
Page 3
NXP Semiconductors Product specification
Fig.3 Power derating curves; BF998.
handbook, halfpage
0
100
0 200100
200
(mW)
P
tot max
(1)(2)
MLA198
T
amb
( C)
o
(1) Ceramic substrate.
(2) Printed-circuit board.
Fig.4 Power derating curve; BF998R.
handbook, halfpage
0
100
0 200100
200
(mW)
P
tot max
MGA002
T
amb
(°C)
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
LIMITING VALUES
In accordance with the Absolu te Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
I
D
I
G1
I
G2
P
tot
P
tot
T
stg
T
j
Notes
1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm.
2. Device mounted on a printed-circuit board.
drain-source voltage 12 V
drain current 30 mA
gate 1 current 10 mA
gate 2 current 10 mA
total power dissipation; BF998 up to T
up to T
total power dissipation; BF998R up to T
=60C; see Fig.3; note 1 200 mW
amb
=50C; see Fig.3; note 2 200 mW
amb
=50C; see Fig.4; note 1 200 mW
amb
storage temperature 65 +150 C
operating junction temperature 150 C
1996 Aug 01 3
Page 4
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
R
th j-a
Notes
1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm.
2. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
=25C; unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)G1-SS
V
(BR)G2-SS
V
(P)G1-S
V
(P)G2-S
I
DSS
I
G1-SS
I
G2-SS
thermal resistance from junction to ambient in free air; BF998 note 1 460 K/W
note 2 500 K/W
thermal resistance from junction to ambient in free air; BF998R note 1 500 K/W
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
gate 1-source cut-off voltage V
gate 2-source cut-off voltage V
drain-source current V
gate 1 cut-off current V
gate 2 cut-off current V
G2-S=VDS
G1-S=VDS
G2-S
G1-S
G2-S
G2-S=VDS
G1-S=VDS
=0; I
=0; I
= 10 mA 6 20 V
G1-SS
= 10 mA 6 20 V
G2-SS
=4V; VDS=8V; ID=20A 2.0 V
=0; VDS=8V; ID=20A 1.5 V
=4V; VDS=8V; V
=0; V
G1-S
=0; V
G2-S
=0; note1 2 18 mA
G1-S
= 5V 50 nA
= 5V 50 nA
Note
1. Measured under pulse condition.
DYNAMIC CHARACTERISTICS
Common source; T
=25C; VDS=8V; V
amb
=4V; ID=10mA.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
forward transfer admittance f = 1 kHz 21 24 mS
y
fs
C
ig1-s
C
ig2-s
C
os
C
rs
F noise figure f = 200 MHz; G
input capacitance at gate 1 f = 1 MHz 2.1 2.5 pF
input capacitance at gate 2 f = 1 MHz 1.2 pF
output capacitance f = 1 MHz 1.05 pF
reverse transfer capacitance f = 1 MHz 25 fF
f=800MHz; G
=2mS; BS=B
S
= 3.3 mS; BS=B
S
Sopt
0.6 dB
1.0 dB
Sopt
1996 Aug 01 4
Page 5
NXP Semiconductors Product specification
Fig.5 Output characteristics; typical values.
handbook, halfpage
010
24
0
8
16
4
12
20
MGE813
2468
VDS (V)
I
D
(mA)
0.4 V
0.3 V
0.2 V
0.1 V
0 V
−0.5 V
−0.4 V
−0.3 V
−0.2 V
−0.1 V
V
G1-S
=
V
G2-S
=4V; T
amb
=25C.
Fig.6 Transfer characteristics; typical values.
handbook, halfpage
−11
24
0
8
16
4
12
20
MGE815
0
3 V
2 V
1 V
0 V
V
G2-S
= 4 V
V
G1
(V)
I
D
(mA)
VDS=8V; T
amb
=25C.
Fig.7 Drain current as a function of gate 1
voltage; typical values.
handbook, halfpage
−1600 −400−800−1200 400
24
0
8
16
4
12
20
MGE814
0
max
typ
min
V
G1
(mV)
I
D
(mA)
VDS=8V; V
G2-S
=4V; T
amb
=25C.
Fig.8 Forward transfer admittance as a func tion of
drain current; typical values.
handbook, halfpage
020
30
0
6
12
18
24
MGE811
161284
ID (mA)
0.5 V
4 V
1 V
2 V
3 V
V
G2-S
= 0 V
|yfs|
(mS)
VDS=8V; T
amb
=25C.
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 5
Page 6
NXP Semiconductors Product specification
Fig.9 Forward transfer admittance as a function of
gate 1 voltage; typical values.
VDS=8V; T
amb
=25C.
handbook, halfpage
−11
30
0
6
12
18
24
MGE812
0
VG1 (V)
0 V
1 V
2 V
3 V
V
G2-S
= 4 V
|yfs|
(mS)
Fig.10 Output capacitance as a function of
drain-source voltage; typical values.
handbook, halfpage
414
1.5
1.0
1.1
1.2
1.3
1.4
MGE810
C
os
(pF)
6 8 10 12
VDS (V)
12 mA
10 mA
8 mA
V
G2-S
=4V; f=1MHz; T
amb
=25C.
Fig.11 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values.
handbook, halfpage
−2.4 −1.6 −0.8 0.8
MGE809
0
2.1
1.9
1.7
2.3
1.5
1.3
C
is
(pF)
V
G1-S
(V)
VDS=8V; V
G2-S
= 4 V; f = 1 MHz; T
amb
=25C.
Fig.12 Gate 1 input capacitance as a function of
gate 2-source voltage; typical values.
handbook, halfpage
642
C
is
(pF)
−2
2.4
2.3
2.1
2.0
2.2
MBH479
0
V
G2−S
(V)
VDS=8V; V
G1-S
= 0 V; f = 1 MHz; T
amb
=25C.
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 6
Page 7
NXP Semiconductors Product specification
Fig.13 Input admittance as a function of the
frequency; typical values.
VDS=8V; V
G2-S
=4V; ID=10mA; T
amb
=25C.
10
3
MGC466
10
2
10
10
2
1
10
10
1
y
is
(mS)
f (MHz)
b
is
g
is
Fig.14 Reverse transfer admittance and ph ase as a
function of frequency; typical values.
VDS=8V; V
G2-S
=4V; ID=10mA; T
amb
=25C.
10
3
MGC467
10
2
10
10
3
10
2
10
1
y
rs
10
3
10
10
1
2
(μS)
f (MHz)
rs
y
rs
(deg)
rs
ϕ
ϕ
Fig.15 Forward transfer admittance and phase as a
function of frequency; typical values.
VDS=8V; V
G2-S
=4V; ID=10mA; T
amb
=25C.
10
3
MGC468
10
2
10
1
10
2
10
1
10
10
2
y
fs
(mS)
y
fs
f (MHz)
(deg)
fs
fs
ϕ
ϕ
Fig.16 O utput admittance as a function of the
frequency; typical values.
VDS=8V; V
G2-S
=4V; ID=10mA; T
amb
=25C.
10
3
MGC469
10
2
10
10
1
10
1
10
2
y
os
(mS)
f (MHz)
b
os
g
os
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 7
Page 8
NXP Semiconductors Product specification
handbook, full pagewidth
MGE802
330 kΩ
1.8 kΩ
360 Ω
100 kΩ
140 kΩ
1 nF
1 nF
47 μF
20 μH
1 nF
10 pF
D2
BB405
330 kΩ
1 nF
1 nF
V
tun
output
50 Ω
output
C1
5.5 pF
50 Ω
input
V
DD
V
DD
V
agc
47 kΩ
1 nF
1 nF
1 nF
L2
L1
1 nF
15 pF
D1
BB405
V
tun
input
VDD=12V; GS=2mS; GL= 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL= 0.5 mS. C1 adjusted for GS=2mS.
Fig.17 Gain control test circuit at f = 200 MHz.
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 8
Page 9
NXP Semiconductors Product specification
Fig.18 Gain control test circuit at f = 800 MHz.
VDD=12V; GS= 3.3 mS; GL=1mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4mm above ground plane.
handbook, full pagewidth
MGE801
1.8 kΩ
360 Ω
100 kΩ
1 nF
1 nF
1 nF
50 Ω
output
1 nF
50 Ω
input
V
DD
V
DD
V
DD
V
agc
270 kΩ
140 kΩ
1 nF
1 nF
L4
L1
L2
1 nF
C1
2 to 18 pFC20.5 to 3.5 pF
C3
0.5 to
3.5 pF
C4
4 to 40 pF
L3
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 9
Page 10
NXP Semiconductors Product specification
handbook, halfpage
010
0
−50
−40
−30
−20
−10
MGE808
ΔG
tr
(dB)
2468
V
agc
(V)
I
DSS
=
max
typ
min
Fig.19 Automatic gain control characteristics
measured in circuit of Fig.17.
VDD=12V; f=200MHz; T
amb
=25C.
handbook, halfpage
010
0
−50
−40
−30
−20
−10
MGE807
ΔG
tr
(dB)
2468
V
agc
(V)
I
DSS
=
max
typ
min
Fig.20 Automatic gain control characteristics
measured in circuit of Fig.18.
VDD=12V; f=800MHz; T
amb
=25C.
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 10
Page 11
NXP Semiconductors Product specification
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
1.1
0.9
A
1
max
0.1
b
1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
H
E
ywvQ
2.5
2.1
0.45
0.15
0.55
0.45
e
1.9
e
1
1.7
L
p
0.1 0.10.2
b
p
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143B
04-11-16
06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; 4 leads SOT143B
D
H
E
E
A
B
v M
A
X
A
A
1
L
p
Q
detail X
c
y
w M
e
1
e
B
21
34
b
1
b
p
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
PACKAGE OUTLINES
1996 Aug 01 11
Page 12
NXP Semiconductors Product specification
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
1.1
0.9
A
1
max
0.1
b
1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
H
E
ywvQ
2.5
2.1
0.55
0.25
0.45
0.25
e
1.9
e
1
1.7
L
p
0.1 0.10.2
b
p
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143R SC-61AA
04-11-16
06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; reverse pinning; 4 leads SOT143R
D
H
E
E
A
B
v M
A
X
A
A
1
L
p
Q
detail X
c
y
w M
e
1
e
B
12
43
b
1
b
p
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
1996 Aug 01 12
Page 13
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
DATA SHEET STATUS
DOCUMENT
STATUS
Objective data sheet Development This document contains data from the objective specification for product
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) desc ribed in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DEFINITIONS
Product specification The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
DISCLAIMERS
Limited warranty and liability Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
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removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
(1)
PRODUCT
STATUS
(2)
DEFINITION
development.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication he reof.
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not designed, authorized or warranted to be suitable for
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of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inc l usion and/or use is at
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Applications Applications that ar e described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
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Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the ris ks
associated with their applications and products.
1996 Aug 01 13
Page 14
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applicat ions and
products using NXP Semiconductors products in or de r to
avoid a default of the applications and the prod ucts or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Rec ommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
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http://www.nxp.com/profile/terms, unless otherwise
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Quick reference data The Quick reference data is an
extract of the product data given in t he Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
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or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
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In the event that customer uses the product for design-in
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may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights .
1996 Aug 01 14
Page 15
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
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Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and relia ble and may be change d
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands R77/02/pp15 Date of release:1996 Aug01
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