The Sil504 transfer interlacing signals to progressive signals. The advantage of progressive
signals is that the scanning rate doubling to let the screen more stable and non-flickering. Besides, the
sources of input may have 24 0r 30 or 25 frames per sec, so the de-interlaced chip shall tell from the
differences and processing the signals. The basic principle of de-interlaced IC is combined the odd and
even fields to a frame , and the processing needs a memory IC(SDRAM) to store these signals for
processing . For the improving the quality of image sake , more and more TVs or DVD players all
have the functions of progressive scanning.
e. Image Processor chip:PW171-20U(system on chip)
◎ Scaling function :
The Image scalars provide high quality up and down image scaling . For the applications of VIF , the
input signals could be VGA , SVGA , XGA formats , and its output fixed at 852 x 480 @60 HZ . For
example , SVGA format:800 x 600 @75Hz , first scaling down : Horizontal 800Î640、Vertical
600Î480 , 75 frames / sec after frame rate conversion become 60 frames per sec. Then scaling up
640Î852 , to accomplish the scaling function.
◎ Micro Processor Function :
This chip includes microprocessor(on-chip 80x86) ; selectable function and I/O interface control .
With 3 groups of 8-bit programmable I/O , 1 group of RS-232 communication port , IR
decoder ,timer and a PWM generator
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◎ OSD Function :
3
o/Video
S-VideoY/Cb/Cr
Video Decoder
Switc
V
The on-screen-display(OSD) can be used for startup screens , menus , and scribble functions.
2.1.2 Photos of VIF Board :
a. Video Module:
Audi
b 2nd PC Module:
D Y/C SEP
To VIF Main Board
Audio
To VIF Main Board
h
PC OUT
H B G R
PC Audio IN
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c. VIF Main Board:
J16
To DIF
J15
SDRAM
J17
Image
Processor
Tone
Control
Reset
SDRAM
J12
De_interlace
To Video/PC Module TMDS
ADC
D-SUB
DVI
2.1.3 Pin assignments of connectors :
a. J12 : Key Pad Signal
NO
ITEM PowerRight Left Up Down Menu Input Gnd
b. J11 : Receiver/Indicator Signal
1 2 3 4 5 6 7 8
J11
RS232
NO
ITEM NC Red LED Green LED Gnd Ir_Rcv +5V
1 2 3 4 5 6
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c. J17 : Audio Signal
NO 1 2 3 4 5 6
ITEM Mute L_Out L_Gnd R_Out R_Gnd
SPK
Int/Ext
d. J16 : Power –Control Signal
NO 1 2 3 4 5 6 7 8 9 10
+5V
ITEM
LV ON NC HV ON NC Gnd Fault Pwloss Fan Gnd
Standby
e. J15 : Power –Supply Voltage
NO 1 2 3 4 5 6 7 8 9
ITEM
+9V
Audio
+9V
Audio
GND GND
+5V
VCC
+5V
GND GND
VCC
f. J9:Output – Out to DIF
1/
SCL
2/
SDA
3/
NC
4/
NC
5/
Status
6/
GND
7/
R-00
8/
R-01
+5V
Standby
9/
R-02
10/
R-03
19/
G-02
28/
B-01
37/
GND
11/
GND
20/
G-03
29/
B-02
38/
H-sync
12/
R-04
21/
GND
30/
B-03
39/
GND
13/
R-05
22/
G-04
31/
GND
40/
V-sync
14/
R-06
23/
G-05
32/
B-04
41/
GND
15/
R-07
24/
G-06
33/
B-05
42/
Blanking
16/
GND
25/
G-07
34/
B-06
43/
GND
17/
G-00
26/
GND
35/
B-07
44/
PixelCLK
18/
G-01
27/
B-00
36/
GND
45/
GND
2.1.4 VIF (Video interface) :
a. When main switch is ON , the power board generates Vsby 5 volts to VIF board. The IC of
microprocessor become standby status waiting for a startup signal from key-pad or receiver.
b. When a startup signal is detected then microprocessor sending a ON signal to the power board
through CN connector , and the power board begins generating all voltage to PCB board(Vs ,
Vxg , Vw , Vf , Vdd , Vcc , 9volts) . At the same time VIF will generate background light and
OSD menu as select .After searching a input source , then will display on the PDP screen , if
there are audio signals , it will amplify and send to speakers through audio board.
c. If there are abnormal signals are detected(such as over voltage , over current , low voltage ..) , the
power board will send abnormal detective signal to shut down all the system.
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2.1.5 System Block diagram :
2.1.6 Some Waveforms:
J9_42 TP155
Blanking
21
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J9_42 TP155
Blanking
J9_40 TP154
Vsync
J9_38 TP152
Hsync
J9_44 TP156
PixelClock
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2.2. DIF board:
2.2.1 DIF 2.95 board:
DIF 2.95 board :
Fig. 1 The role of DIF board
Fig.2 The photo of a DIF board
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2.2.2 Equipments:
a. Power : 5V 3A power supply * 1
b Tools:
b-1 Oscilloscope
b-2 PMC
Fig. 3 Oscilloscope with 4 channels
b-3 45 pin FFC connector * 1
b-4 Multi-meter * 1
c. Test flow
c-1 Overall check:
To inspect the DIF board whether broken board occurred , components broken or short
circuit…. etc .
Ex:
(1)
Fig.4 PMC * 1
Fig. 5 Connector short circuit
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(2)
Fig.5 D to W connector broken
(3)
c-2 Power test:
Make sure that the power is normal without any short circuit happening.
2.2.3 Simple electric circuit test:
Checking all functions of the board is normal.
Test flow as Fig.7 shown.
Fig.6 Wrong DRAM
Fig.7 Test flow
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** LED : When DIF power on , the LED light on means that the FPGA download OK , at this time the
p
current will be about 1.3A .
a. Waveform testing :
a-1 Make sure that the waveforms of S , X , Y are normal . Repeat reading the data from IC to
make sure the downloading data is normal.
a-2 The Waveform of IC106 : If the waveforms of S , X , Y are normal. Then we can check
the functions of controlling waveforms of IC106.
a-3 Next procedure is going to check the waveform of V、Start、Wp、Wn、SF0~SF3、Esq.
Check Vf , Vf is signal after processing from V. SF0~SF3 , Esq is the setting time and
ending time of the sub-field .
a-4 Check the output of X and Y :
As Fig. 8 shown. Confirm that the waveform is normal.
X : DD1 Waveform
X : DD2 Waveform
Event =15 ,means that
ulse shown at block15
Fig.8 X : DD1 and DD2 output waveform
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b. Checking the function of APC:
b-1 The data of Adat are normal. Compared with look up table(LUT).
b-2 Checking the power of WAPC , Check the signal of SM and SF0 to make sure the power
WAPC functions OK.
b-3 Check the screen of PDP :
From the screen to check the functions of DIF’s performance is good or not.
c The debug flow chart as Fig.9 shown.
Fig.9 The debug flow chart
2.2.4 Advanced testing and checking:
The DIF board has three major functions.
a. Image signal process:
a-1 Purpose: To check the functions of image signal process are correct.
As Fig.10 shown ,
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data
buffe
age
source
a
ce
compute
deo
r
vi
Antenna
r
RAM
im
interf
Fig.10 Image signal process
a-2 As Fig.11 Shown , the image signals separated into R , G , B for processing.
Fig.11 Image signal process
a-3 Here we check the input / output signals is correct or not. Compared with the output
and input waveforms of Rx7-Rx0 , Gx7-Gx0 , Bx7-Bx0 are the same or not , and check
the waveforms of Vx , Hx , Blkx , BlkVx , Clkx are normal or not .
a-4 For IC101-103 , IC106 is passing a Wp signal to IC101-103 , as fig.11 image signal
process , IC101-IC103 output signals to panel , so the buffer and extension board ,
connector are checking points too.
a-5 Image process
EX : IC101 –> PANEL Output
IC101
LUT
7-9
8-9
Driver IC
Panel
In IC101 , There are 7 blocks for processing , from system trigging to output signal.
DRAM
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For example ,the process of VF signal as below shown:
V
The real waveform is as below , the length is 60μS.
VF
V
Fig.12 Real waveform
Ex : IC100 –> IC106
μ-com
VF
SRAM IC104 IC100 PMC
IC106
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Ex : Dividing panel into 30*28 , store the data into SRAM.
IC104 not only calculate the block sum , scan sum , total sum but also deal with the
Pattern A , pattern B , pattern judgment of the pattern check. The value of calculation
will be sent to up1 for operation . In the checking of buffer , we only compare the
waveforms between input and output.
b. Waveform controlling :
SRAM
b-1 Purpose : To check the waveform of X , Y is normal or not.
These parts of functions are accomplished by IC 106 to control the sustainer of
Fig.13 Driving signal (Sub-fielb period T Sfi)
X and Y. The controlling waveform is stored in IC170 and IC171 , that’s FlashX
and FlahY , the waveform is as Fig.13 shown.
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b-2 List of signal input
R Red Data Pixel_Red Data
G Green Data Pixel_Green Data
B Blue Data Pixel_Blue Data
CLK Clock dot clock
HD H_sync Horizontal synchronous
VD V_sync Vertical synchronous
BLK Blank blanking-invalid data period
EN Enable display enable
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b-3 Timing spec. – see with video signal input time chart
b-4 Sub-field:
Start End
The real information is:
1-SF 2-SF 3-SF 4-SF 5-SF 6-SF 7-SF 8SF 9-SF
SF0
SF1
SF1
SF2
c. Auto Power Control (APC):
c-1 Purpose : To check the functions of APC are normal or not.
The functions of APC are important to panel ; it may cause power failure or even
panel broken . The processing is as Fig.14 shown:
Fig.14 APC block diagram
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c-2 When signal data send to APC , the Calculate Display Ratio begins to calculate the ratio
of pattern .After checking and calculating pattern(A ,B , C) , the numbers of pattern , then
sending the data of display and switching count to the window memory .
Fig.15 Pattern A , Pattern B , Pattern C (CPT thousand-birds’ pattern)
c-3 The APC is performing mathematical calculations , by reducing the sustain frequency and
closing some sub-fields to accomplish. There is reference for judgment , as Fig.16 and Fig.17
shown . The parameters has been tested by experiments to determine , so if the parameters of
APC are not the optimal parameter , it may cause panel broken , scan IC burned , power supply
failure.
Fig.16 The curve of APC
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Fig.17 The limit of power vs. sustain frequency
c-4 The debug flow chart is as Fig.18 shown.
Fig.18 APC debug flow chart
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c-5 According to the past experiences , most of the errors of APC happened at SRAM and
buffer IC , so these parts will be the checking points.
2.2.5 IC100 - IC106 : Main signals measurement
Purpose : To check the action of FPGA from IC100 to IC106
The waveform is shown as below.
a. Take the Wp waveform as examples:
2. Observe
ch2 signal
1. Trigger
ch3 signal
a-1 Explanation of waveform :
1. Trigger
ch1 signals
2. Observe
ch2 signals
3. trigger
level
4.ch2 waveform
The scanning waveforms look correctly.
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b. The controlling waveforms of IC106 are checking below signals(CH3 trigger V signals):
V、Start、Wp、Wn、SF0~SF3、Esq
Test Pattern=Random
Main
signal
1
Singal
Name
V
P41(V
Remark
)
D
Make sure the DIF input signal of V signal is correct , and is the
trigger signals.
2
Wp
TP121
(Wp)
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3
Wn
TP123
(Wn)
4
5
SF0
SF1
TP126
(SF0)
TP127
(SF1)
37
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6
SF2
TP128
(SF2)
7
8
SF3
Esq
TP129
(SF3)
TP125
(ESQ)
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c. Checking the outputs of X and Y sustainer board
Make sure the waveform of X/Y are correct , the reference waveforms as below
( CH3 trigger V signals)
Test Pattern=random
IC106_Signal List
X
-side
1
Signal
Name
XSI1
Pin No
TP143
2
XTSC
TP141
39
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3
XSTB
TP142
4
5
XLE
XSI2
TP144
TP145
40
Page 42
6
XCLK
TP146
7
8
XNEH
XNEL
TP147
TP148
41
Page 43
9
XEFH
TP149
10
11
XEFL
XAEH
TP150
TP151
42
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12
XAEL
TP152
13
14
XSU
XG1H
TP133
TP134
43
Page 45
15
XG1L
TP135
16
17
XG3L
XG2L
TP136
TP137
44
Page 46
18
XP2L
TP138
19
20
XDD1
XDD2
TP139
TP140
45
Page 47
Y
-side
1
YSC2A J7-PIN2
YSC1A J7-PIN3
2
YNELA J7-PIN5
3
46
Page 48
YNEHA J7-PIN6
4
YEFLA J7-PIN8
5
6
YEFHA
J7-PIN9
47
Page 49
YSC2B J7-PIN11
7
YSC1B J7-PIN12
8
YNELB J7-PIN14
9
48
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YNEHB J7-PIN15
10
YEFLB J7-PIN17
11
YEFHB
12
J7-PIN18
49
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d. The function of APC checking, reference waveform as below (Aclk is trigger signals,Adata is
checking signals)
Test Pattern=Pattern A
Pin
Signal Name
Adata&
1
Aclk
No
TP21
&
TP24
( Complete thousands_birds )
Checking point
1-a
50
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1-b
1-c
2 SM&W
P
TP130
&
TP121
51
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e. IC100
Make sure the waveforms of IC100 is normal or not.(CH1 trigger V signal)
IC100_Signal List
Test Pattern=Pattern A ( Complete thousands_birds )
1
Singal
Name
Rx7-
Rx0
Pin No
P7-14
Remark
2 Gx7-Gx0
P15-19、
24-26
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3 Bx7
P27-31、
26-38
4 Vx P39
5 Hx P40
53
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6 BLKx P41
7 CLK 321 P46
8 CLK 324 P47
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9 R7-R0
P111-116、
119-120、
P122、
10 G7-G0
P135-136、
11 B7
125-128、
131-133
139-144
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12 HD P148
13 VD P149
14 BLK c P150
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f. IC101
Make sure the waveforms of IC101 is normal or not.(CH1 trigger V signal)
IC101_Signal List
Test Pattern=Pattern A ( Complete thousands_birds )
Singal
Name
RAD27 P7
1
Pin No Checking point
RACLKa P45
2
RACLKb P46
3
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SF0-SF3 P53-56 Same as (a)
4
5
6
7
WN P57 Same as (a)
WP P58 Same as (a)
BLHR P60
58
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VFR P62
8
HPR P63
9
10
VPR P64
59
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11
Rx7 P75
12
13
SM P86
RMBD0 P87
60
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RMBOE P111
14
RMBWE P112
15
RMBCS1 P113
16
61
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RMBRS P115
17
RMBA0 P116
18
RMAD0 P132
19
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RMAOE P158
20
RMAWE P159
21
RMACS1 P160
22
63
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RMARS P162
23
RMAA0 P174
24
25
RFI8 P192
64
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26
Vx P205
27
BLKx P207
g. IC104
Make sure the waveforms of IC104 is normal or not.(CH1 trigger V signal)
IC104_Signal List
Test Pattern=Pattern A
Singal
Name
( Complete thousands_birds )
Pin No
65
Page 67
1
EW P144
2 CLK324 P183
h. gamma flash and up2
The gamma functions can check with VIF , select the low , medium , high color temperature to see the
changes.
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2.3 POWER Board:
2.3.1 Introduction:
VXG
VF VCCVS
VSB
VW
Explanation :
Input voltage is from AC100V to 240V , frequency 47HZ~63HZ is available.
The maximum input AC voltage range is from 90V to 265V .
2.3.2 Output Power rating :
Voltage Adjustment
Danger ! High Voltage
VAU
Name Peak load
Vsb 5V 0.4A
Vdd 5V 2.0A
Ccc 5V 3.0A
Vau 9V 1.7A
Vfan 12V 0.5A
Vf 15V 0.6A
Vs 170V 290W 50A
Vw 65V 80W 6A
Vxg -160V 0.1A 1A
Vaux 310~380V 65W
Output Max Load
2.3.3 pin assignments of connectors
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a. Connector ; AC IN
Pin-No Name Voltage
1 AC 100~240V AC
2
3 AC 100~240V AC
b. Connector ; PD
Pin-No Name Voltage REMARK
1 Vcc 5V
2 Vcc 5V
3 VccG ( Vcc GND ) LV Ground
4 VccG ( Vcc GND ) LV Ground
c. Connector ; PX1
Pin-No Name Voltage REMARK
1 Vs 175V
2 NC
3 VsG Vs GND HV Ground
4 VwG Vw GND HV Ground
5 Vw 65V
6 Vf 15V
7 VfG (Vf GND) HV Ground
d. Connector ; PX2
Pin-No Name Voltage REMARK
1 Vcc 5V
2 VccG ( Vcc GND ) LV Ground
3 VxgG ( Vxg GND ) HV Ground
4 NC
5 Vxg -160V
e. Connector ; PY
Pin-No Name Voltage REMARK
1 Vs 175V
2 NC
3 VsG (Vs GND) HV Ground
4 VwG (Vw GND) HV Ground
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5 Vw 65V
6 Vf 15V
7 VfG (Vf GND) LV Ground
8 Vcc 5V
9 VccG (Vcc VGND) LV Ground
f. Connector ; Vaux
Pin-No Name Voltage
1 Vaux DC( + ) 300~380V ( primary)
2
3
VauxG DC( 一 )
Vaux G ( primary )
g. Connector ; PW
Pin-No Name Voltage REMARK
1 Vw 65V
2 Vw 65V
3 NC
4 VwG ( Vw GND) HV Ground
5 VwG (Vw GND) HV Ground
6 Vcc 5V
7 VccG (Vcc GND) LV Ground
h. Connector ; PV
Pin-No Name Voltage REMARK
1 Vau 9V
2 Vau 9V
3 VauG VIF GND VIF Ground
4 VauG VIF GND VIF Ground
5 Vdd 5V
6 Vdd 5V
7 VddG VIF GND VIF Ground
8 VsbG VIF GND VIF Ground
9 Vsb 5V 0.4A
i. Connector ; OH
Pin-No Name Voltage REMARK
1 OH Dry Contact
2 COM OH GND Connect to VccG
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j. Connector ; FAN1 FAN2
Pin-No Name Voltage REMARK
1 Vfan 12V
2 Fan_STS Fan Status
3 VfanG 12V GND FAN Ground
k. Connector ; CN
Pin-No Name Voltage REMARK
1 Vsb +5V Input Signal Voltage
2 VCC__ON 0V/OPEN Input Signal (O.C.)
3 Reserved
4 HV_ON 0V/OPEN Input Signal (O.C.)
5 Reserved
6 Vsb GND VGND VIF Ground
7 FLT 0V/OPEN Output Signal (O.C.)
8 PWRLOSS 0V/OPEN Output Signal (O.C.)
9 FAN _OK 0V/OPEN Output Signal (O.C.)
10 Vsb GND Vsb GND VIF Ground
2.3.4. Troubleshooting
a. Plug out CN connector but no Vsb voltage : Replace IC101 0254(TNY264P).
b. Vaux not enough 300~380 voltage : Replace IC001 FA5332 ; Q003 K2698 ; Q004 K2698 ;
R028 100Ω ; R030 100Ω.
c. Vcc , Vdd no 5 voltages : Replace IC201 M51995 ; Q201 K2717 ; R201 0.22Ω
3W.
d. Vw no 65 voltage : Replace IC301 M51995 ; Q301 K2717 ; R301 0.18Ω 3W.
e. Vs no 175 voltage : Replace IC501 M51995 ; Q501 K2607 ; Q502 K2607 ;
R511 0.22Ω 3W ; R512 0.22Ω 3W.
f.Vxg no –165 voltage : Replace Q703 K2638 ( Under Vs is normal )
g. The adjustment of all voltage : VR
5V…..…….1A…….….VR151 5V……..…5A…….…...VR253
15V…..…0.5A…..……VR251 9V……...1.7A…………VR252
65V……..1.7A………..VR351 175V……...2.5A…………VR551
160V…….0.1A……….VR751
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2.4 X-Sustainer board:
2.4.1 X-Sustainer board’s pin alignment :
a. Input Vlotage
Name Input Voltage Current(mA)Remark
Vcc 5 240
Vf 15
Vs 170 1.2A Normal 1.0~1.5A
Vxg -160 40
Vw 65 40
Vs 170 1.2A Normal 1.0~1.5A
Vxg -160 40
Vw 65 40
b. Photo of X sustainer :
J7:(VXDD-VXG)70
J3: W-side
70(全白)
R407: J7 VR
Normal 40~150mA
J6:(VXE-GND)60V
R417: J6 VR
J1:X-side
PX2:VXG,VCC input
J302:X-side
PX1:VF,VW,VS input
J301:X-side
output
c. Input signals: DIF-X sustainer 30 lead 5V TTL signal
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d. Output signal :
d-1 Output to PDP
Above figure shows the waveform from X and Y extension board(TP301~TP308)
; Green line is the X-side output and Red line is the Y-side output.
d-2 Output to W-extension board :
Vw 65V DC
2.4.2 X-side function explanation :
Low voltage and High voltage
There are two kinds of low voltages : 5V and 15V . They are used to provide the input
signals of driving waveform .
5V signal : Providing the power of ICs . The TC4426 and IR2113S(Driver IC) are for
driving MOS FET. IC :MC74244 and HCPL-M611 , provide signals to scan IC.
So the 5V of X sustainer includes the power of driver IC and input signals and DC
5V adapter.
15V signal : Providing the power of TC4426 and IR2113S , the input signals of 5V
switching to 15V to drive the signal of MOS. So we can check the 15V
only at the output of driver IC and the input of MOSFET(VG).
65 Voltage : The voltage of Vxe(Vw) at X-side is 65 voltage .There are two groups of
circuit: one generates 65V to get the waveform of NAMARI , the other
provide 65V for COF of W-side .
The 65V of Vysc of Y-side generates 35V at the address period of bulk-side.
High voltage:170V and -160V belong PDP high drive voltage.
170 Voltage: The control signals of EFH , EFL , NEH , NEL , XSU (170V)are generated
by the MOSFET after MOSFET got a control signal from GATE pin.
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Resister : 820Ω / 3W x 6 pcs . For generating the positive exponential