Philips AN10323 Service Manual

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Page 1

AN10323_1

PNX8550 Programmable Source Decoder with Integrated Peripherals

Rev. 02 — July 22 2004

Page 2

Philips Semiconductors

Aperture Map

M-Default Slv

0x00 0FFC . . . . . . . . . . . . . . . . . . . . . . . 4

MGIC Registers (Rev 1.6.1)

0x03 E000 int_priority_0 . . . . . . . . . . . . 4

0x03 E004 int_priority_1 . . . . . . . . . . . . 4

0x03 E100 int_vector_0 . . . . . . . . . . . . . 5

0x03 E104 int_vector_1 . . . . . . . . . . . . . 5

0x03 E200 int_pending_1_31 . . . . . . . . 6

0x03 E204 int_pending_32_63 . . . . . . . 6

0x03 E208 int_pending_64_70 . . . . . . . 6

0x03 E300 int_features . . . . . . . . . . . . . 6

0x03 E404 int_request_reg_1 . . . . . . . . 7

0x03 E408 int_request_reg_2 . . . . . . . . 8

0x03 E40C int_request_reg_3 . . . . . . . . 8

0x03 E410 int_request_reg_4 . . . . . . . . 8

0x03 E414 int_request_reg_5 . . . . . . . . 8

0x03 E418 int_request_reg_6 . . . . . . . . 9

0x03 E41C int_request_reg_7 . . . . . . . . 9

0x03 E420 int_request_reg_8 . . . . . . . . 9

0x03 E424 int_request_reg_9 . . . . . . . . 9

0x03 E428 int_request_reg_10 . . . . . . . 9

0x03 E42C int_request_reg_11 . . . . . . . 9

0x03 E430 int_request_reg_12 . . . . . . . 9

0x03 E434 int_request_reg_13 . . . . . . . 9

0x03 E438 int_request_reg_14 . . . . . . . 9

0x03 E43C int_request_reg_15 . . . . . . . 9

0x03 E440 int_request_reg_16 . . . . . . . 9

0x03 E444 int_request_reg_17 . . . . . . . 9

0x03 E448 int_request_reg_18 . . . . . . . 9

0x03 E44C int_request_reg_19 . . . . . . . 9

0x03 E450 int_request_reg_20 . . . . . . . 9

0x03 E454 int_request_reg_21 . . . . . . . 9

0x03 E458 int_request_reg_22 . . . . . . . 9

0x03 E45C int_request_reg_23 . . . . . . . 9

0x03 E460 int_request_reg_24 . . . . . . . 9

0x03 E464 int_request_reg_25 . . . . . . 10

0x03 E468 int_request_reg_26 . . . . . . 10

0x03 E46C int_request_reg_27 . . . . . . 10

0x03 E470 int_request_reg_28 . . . . . . 10

0x03 E474 int_request_reg_29 . . . . . . 10

0x03 E478 int_request_reg_30 . . . . . . 10

0x03 E47C int_request_reg_31 . . . . . . 10

0x03 E480 int_request_reg_32 . . . . . . 10

PNX8550

Programmable Source Decoder with Integrated Peripherals

0x03 E484 int_request_reg_33 . . . . . 10

0x03 E488 int_request_reg_34 . . . . . 10

0x03 E48C int_request_reg_35 . . . . . 10

0x03 E490 int_request_reg_36 . . . . . 10

0x03 E494 int_request_reg_37 . . . . . 10

0x03 E498 int_request_reg_38 . . . . . 10

0x03 E49C int_request_reg_39 . . . . . 10

0x03 E4A0 int_request_reg_40 . . . . . 10

0x03 E4A4 int_request_reg_41 . . . . . 10

0x03 E4A8 int_request_reg_42 . . . . . 10

0x03 E4AC int_request_reg_43 . . . . . 11

0x03 E4B0 int_request_reg_44 . . . . . 11

0x03 E4B4 int_request_reg_45 . . . . . 11

0x03 E4B8 int_request_reg_46 . . . . . 11

0x03 E4BC int_request_reg_47 . . . . . 11

0x03 E4C0 int_request_reg_48 . . . . . 11

0x03 E4C4 int_request_reg_49 . . . . . 11

0x03 E4C8 int_request_reg_50 . . . . . 11

0x03 E4CC int_request_reg_51 . . . . . 11

0x03 E4D0 int_request_reg_52 . . . . . 11

0x03 E4D4 int_request_reg_53 . . . . . 11

0x03 E4D8 int_request_reg_54 . . . . . 11

0x03 E4DC int_request_reg_55 . . . . . 11

0x03 E4E0 int_request_reg_56 . . . . . 11

0x03 E4E4 int_request_reg_57 . . . . . 11

0x03 E4E8 int_request_reg_58 . . . . . 11

0x03 E4EC int_request_reg_59 . . . . . 11

0x03 E4F0 int_request_reg_60 . . . . . 11

0x03 E4F4 int_request_reg_61 . . . . . 11

0x03 E4F8 int_request_reg_62 . . . . . 12

0x03 E4FC int_request_reg_63 . . . . . 12

0x03 E500 int_request_reg_64 . . . . . 12

0x03 E504 int_request_reg_65 . . . . . 12

0x03 E508 int_request_reg_66 . . . . . 12

0x03 E50C int_request_reg_67 . . . . . 12

0x03 E510 int_request_reg_68 . . . . . 12

0x03 E514 int_request_reg_69 . . . . . 12

0x03 E518 int_request_reg_70 . . . . . 12

0x03 EFFC MOD_ID . . . . . . . . . . . . . . 12

IPC_MIPS Registers (Rev 1.6.1)

0x03 F000 int_priority_0 . . . . . . . . . . . 12

0x03 F004 int_priority_1 . . . . . . . . . . . 13

0x03 F100 int_vector_0 . . . . . . . . . . . . 13

0x03 F104 int_vector_1 . . . . . . . . . . . . 14

0x03 F200 int_pending_1_8 . . . . . . . . 14

0x03 F300 int_features . . . . . . . . . . . . 14

0x03 F404 Message Register_1 . . . . . 14

0x03 F408 Message Register_2 . . . . 16

0x03 F40C Message Register_3 . . . . 16

0x03 F410 Message Register_4 . . . . 16

0x03 F414 Message Register_5 . . . . 16

0x03 F418 Message Register_6 . . . . 16

0x03 F41C Message Register_7 . . . . 16

0x03 F420 Message Register_8 . . . . 16

PCI-XIO Registers (Rev 0.9.6)

0x04 0010 PCI Setup . . . . . . . . . . . . . 16

0x04 0014 PCI Control . . . . . . . . . . . . 17

0x04 0018 PCI_Base1_lo . . . . . . . . . . 18

0x04 001C PCI_Base1_hi . . . . . . . . . . 18

0x04 0020 PCI_Base2_lo . . . . . . . . . . 18

0x04 0024 PCI_Base2_hi . . . . . . . . . . 19

0x04 0028 Read Data Lifetime Timer . 19 0x04 002C General Purpose PCI Master

0x04 0030 General Purpose PCI Master

0x04 0034 General Purpose PCI Master

0x04 0038 General Purpose PCI Master

Preliminary Rev. 02 — July 22 2004 i

(GPPM) Address . . . . . . . . 19

(GPPM) Write Data . . . . . . 19

(GPPM) Read Data . . . . . . 19

0x04 003C Unlock Register . . . . . . . . 19

0x04 0040 Image of Device ID and

0x04 0044 Image of Command/Status 20 0x04 0048 Image of Class Code/Revision

0x04 004C Image of Latency Timer/Cache

0x04 0050 Base Address 10 Image . . 20 0x04 0054 Base Address 14 Image . . 20 0x04 0058 Base Address 18 Image . . 21 0x04 006C Subsystem ID/Subsystem

(GPPM) Control . . . . . . . . 19

Vendor ID . . . . . . . . . . . . . 20

ID . . . . . . . . . . . . . . . . . . . 20

Line Size . . . . . . . . . . . . . 20

Vendor ID Write Port . . . . 21

Page 3

Philips Semiconductors

PNX8550

0x04 0074 Image of Configuration Reg 34

0x04 007C Image of Configuration Reg 3C

0x04 0080 Image of Configuration Reg 40

0x04 0084 Image of Configuration Reg 44

0x04 0088 PCI_IO . . . . . . . . . . . . . . . . 22

0x04 008C Slave DTL tuning . . . . . . . . 22

0x04 0090 DMA DTL tuning . . . . . . . . 22

0x04 0094—07FC Reserved . . . . . . . . . . . . . . 23

0x04 0800 DMA PCI Address . . . . . . . 23

0x04 0804 DMA Internal Address . . . . 23

0x04 0808 DMA Transfer Size . . . . . . 23

0x04 080C DMA Controls . . . . . . . . . . 23

0x04 0810 XIO Control Register . . . . . 23

0x04 0814 XIO Sel0 Profile . . . . . . . . . 24

0x04 0818 XIO Sel1 Profile . . . . . . . . . 24

0x04 081C XIO Sel2 Profile . . . . . . . . . 25

0x04 0820 GPXIO_address . . . . . . . . 26

0x04 0824 GPXIO_write_data . . . . . . . 26

EJTAG DMA Registers (Rev 2.3)

0x04 1000 Implementation Register . . 36 0x04 1FFC Module ID Register . . . . . 36

M-Default Slv

0x04 2FFC . . . . . . . . . . . . . . . . . . . . . . 37

Smartcard UART 1 Registers (Rev 2.04)

0x04 3000 Reset Register (RER) . . . . 37

0x04 3004 Clock Configuration Register

0x04 3008 Programmable Divider

0x04 300C UART Configuration Register

0x04 3010 DMA Read Address Register

0x04 3014 Guard Time Register (GTR) .

0x04 3018 UART Configuration Register

0x04 301C DMA Length Register (DLR) .

0x04 3020 Timeout Configuration

0x04 3024 Timeout Register 1 (TOR1) 43 0x04 3028 Timeout Register 2 (TOR2) 43 0x04 302C Timeout Register 3 (TOR3) 43

(CCR) . . . . . . . . . . . . . . . . 38

2 (UCR2) . . . . . . . . . . . . . . 39

(DRA) . . . . . . . . . . . . . . . . . 40

1 (UCR1) . . . . . . . . . . . . . . 40

0x04 0828 GPXIO_read_data . . . . . . 26

0x04 082C GPXIO_ctrl . . . . . . . . . . . . 26

0x04 0830 NAND-Flash controls . . . . 27

0x04 0834 XIO Sel3 Profile . . . . . . . . 27

0x04 0838 XIO Sel4 Profile . . . . . . . . 28

0x04 0FB0 GPXIO Interrupt Status . . 29 0x04 0FB4 GPXIO Interrupt Enable . . 29 0x04 0FB8 GPXIO Interrupt Clear . . . 29

0x04 0FBC GPXIO Interrupt Set . . . . . 29

0x04 0FC0 GPPM Interrupt Status . . . 30 0x04 0FC4 GPPM Interrupt Enable . . 30

0x04 0FC8 GPPM Interrupt Clear . . . . 30

0x04 0FCC GPPM Interrupt Set . . . . . 31

0x04 0FD0 DMA Interrupt Status . . . . 31

0x04 0FD4 DMA Interrupt Enable . . . . 31

0x04 0FD8 DMA Interrupt Clear . . . . . 32

0x04 0FDC DMA Interrupt Set . . . . . . 32

0x04 0FE0 PCI Interrupt Status . . . . . 32

0x04 0FE4 PCI Interrupt Enable . . . . . 33

0x04 0FE8 PCI Interrupt Clear . . . . . . 34

0x04 0FEC PCI Interrupt Set . . . . . . . 35

0x04 0FFC Module ID . . . . . . . . . . . . . 35

0x04 3030 Mixed Status Register (MSR)

0x04 3030 FIFO Control Register (FCR)

0x04 3034 UART Transmit Register

0x04 3034 UART Receive Register (URR)

0x04 3038 UART Status Register (USR)

0x04 303C DMA Write Address Register

0x04 3040 Command Register (CRE) 47

0x04 3FE0 SCIF_INT_STATUS . . . . . 47

0x04 3FE4 SCIF_INT_ENABLE . . . . . 47

0x04 3FE8 SCIF_INT_CLEAR . . . . . . 48

0x04 3FEC SCIF_INT_SET . . . . . . . . 48

0x04 3FF4 SCIF_POWERDOWN . . . 49

0x04 3FFC SCIF_MODULE_ID . . . . . 49

(UTR) . . . . . . . . . . . . . . . . 45

(DWA) . . . . . . . . . . . . . . . 47

Smartcard UART 2 Registers (Rev 2.04)

0x04 4000 Reset Register (RER) . . . . 49

0x04 4004 Clock Configuration Register

0x04 4008 Programmable Divider

0x04 400C UART Configuration Register

0x04 4010 DMA Read Address Register

0x04 4014 Guard Time Register (GTR) .

0x04 4018 UART Configuration Register

0x04 401C DMA Length Register (DLR) .

0x04 4020 Timeout Configuration

0x04 4024 Timeout Register 1 (TOR1) 55 0x04 4028 Timeout Register 2 (TOR2) 55 0x04 402C Timeout Register 3 (TOR3) 55

Preliminary Rev. 02 — July 22 2004 ii

(CCR) . . . . . . . . . . . . . . . . 50

2 (UCR2) . . . . . . . . . . . . . . 51

(DRA) . . . . . . . . . . . . . . . . . 52

1 (UCR1) . . . . . . . . . . . . . . 52

0x04 4030 Mixed Status Register (MSR)

0x04 4030 FIFO Control Register (FCR)

0x04 4034 UART Transmit Register

0x04 4034 UART Receive Register (URR)

0x04 4038 UART Status Register (USR)

0x04 403C DMA Write Address Register

0x04 4040 Command Register (CRE) 59

0x04 4FE0 SCIF_INT_STATUS . . . . . 59

0x04 4FE4 SCIF_INT_ENABLE . . . . . 59

0x04 4FE8 SCIF_INT_CLEAR . . . . . . 60

0x04 4FEC SCIF_INT_SET . . . . . . . . 60

0x04 4FF4 SCIF_POWERDOWN . . . 61

0x04 4FFC SCIF_MODULE_ID . . . . . 61

(UTR) . . . . . . . . . . . . . . . . 57

(DWA) . . . . . . . . . . . . . . . 59

Page 4

Philips Semiconductors

HP I2C 1 Registers (Rev 2.5)

0x04 5000 I2CCON . . . . . . . . . . . . . . . 61

0x04 5004 I2CSTAT . . . . . . . . . . . . . . 62

0x04 5008 I2CDAT . . . . . . . . . . . . . . . 62

0x04 500C I2CSLA . . . . . . . . . . . . . . . 62

0x04 5010 HSBIR . . . . . . . . . . . . . . . . 62

0x04 5014 FSBIR . . . . . . . . . . . . . . . . 62

0x04 5018 INTROG . . . . . . . . . . . . . . . 62

0x04 501C Reserved . . . . . . . . . . . . . . 63

0x04 5020 DMA_ADDR . . . . . . . . . . . 63

0x04 5024 DMA_LENGTH . . . . . . . . . 63

HP I2C 2 Registers (Rev 2.5)

0x04 6000 I2CCON . . . . . . . . . . . . . . . 66

0x04 6004 I2CSTAT . . . . . . . . . . . . . . 66

0x04 6008 I2CDAT . . . . . . . . . . . . . . . 66

0x04 600C I2CSLA . . . . . . . . . . . . . . . 66

0x04 6010 HSBIR . . . . . . . . . . . . . . . . 66

0x04 6014 FSBIR . . . . . . . . . . . . . . . . 66

0x04 6018 INTROG . . . . . . . . . . . . . . . 67

0x04 601C Reserved . . . . . . . . . . . . . . 67

0x04 6020 DMA_ADDR . . . . . . . . . . . 67

0x04 6024 DMA_LENGTH . . . . . . . . . 67

Clocks Module Registers (Rev 2.6)

0x04 7000 PLL0_CTL . . . . . . . . . . . . . 70

0x04 7004 PLL1_CTL . . . . . . . . . . . . . 70

0x04 7008 PLL2_CTL . . . . . . . . . . . . . 70

0x04 700C PLL3_CTL . . . . . . . . . . . . . 71

0x04 7010 RESERVED . . . . . . . . . . . . 71

0x04 7014 PLL5_CTL . . . . . . . . . . . . . 71

0x04 7018 PLL1_7GHZ_CTL . . . . . . . 71

0x04 701C DDS0_QVCP1_CTL . . . . . 72

0x04 7020 DDS1_QVCP2_CTL . . . . . 72

0x04 7024 Reserved . . . . . . . . . . . . . . 72

0x04 7028 DDS3_AI1_CTL . . . . . . . . . 72

0x04 702C DD4_AO1_CTL . . . . . . . . . 72

0x04 7030 DDS5_AI2_CTL . . . . . . . . . 72

0x04 7034 DDS6_AO2_CTL . . . . . . . . 72

0x04 7038 Reserved . . . . . . . . . . . . . . 72

0x04 703C DDS8_SPDO_CTL . . . . . . 72

0x04 7040 DDS9_TSDMA_CTL . . . . . 72

0x04 7044 POWER_DOWN_CTL . . . . 73

0x04 7048 PLL6_CTL . . . . . . . . . . . . . 73

0x04 704C—70FF Reserved . . . . . . . . . . . . . . 73

0x04 7100 CLK_MEM_CTL . . . . . . . . 74

0x04 7104 DFT_FREQ_CTR_CTL . . . 74

0x04 7108—71FF Reserved . . . . . . . . . . . . . . 74

0x04 7200 CLK_MIPS_CTL . . . . . . . . 74

0x04 7204 CLK_TM1_CTL . . . . . . . . . 74

0x04 7208 CLK_TM2_CTL . . . . . . . . . 74

0x04 720C CLK_M_DCS_CTL . . . . . . 75

0x04 7210 CLK_M_DTL_CTL . . . . . . . 75

0x04 7214 CLK_T_DCS_CTL . . . . . . . 75

0x04 7218 CLK_T_DTL_CTL . . . . . . . 76

0x04 721C CLK_TUNNEL_CTL . . . . . 76

0x04 7220—73FF Reserved . . . . . . . . . . . . . . 76

0x04 7400 CLK_VMPG_CTL . . . . . . . 77

0x04 7404 CLK_VLD_CTL . . . . . . . . . 77

0x04 7408—74FF Reserved . . . . . . . . . . . . . . 77

0x04 7500 CLK_MBS_CTL . . . . . . . . . 77

0x04 7504 CLK_QTNR_CTL . . . . . . . . 78

0x04 7508—75FF Reserved . . . . . . . . . . . . . . 78

0x04 7600 CLK_VIP1_CTL . . . . . . . . . 78

0x04 7604 CLK_VIP2_CTL . . . . . . . . . 78

0x04 7608—76FF Reserved . . . . . . . . . . . . . . 79

0x04 7700 Reserved . . . . . . . . . . . . . . 79

0x04 7704 CLK_D2D_CTL . . . . . . . . . 79

0x04 7708 CLK_PCI_CTL . . . . . . . . . . 79

0x04 770C CLK48_CTL . . . . . . . . . . . . 79

0x04 7710 CLK12_CTL . . . . . . . . . . . . 79

0x04 7714 CLK_IIC1_2_CTL . . . . . . . 80

0x04 7718 CLK_IIC3_4_CTL . . . . . . . 80

0x04 771C CLK_UART1_CTL . . . . . . . 80

0x04 7720 CLK_UART2_CTL . . . . . . . 80

0x04 7724 RESERVED . . . . . . . . . . . . 80

PNX8550

0x04 5028 DMA_COUNTER . . . . . . . 63

0x04 502C DMA_CONTROL . . . . . . . 63

0x04 5030 DMA_STATUS . . . . . . . . . 64

0x04 5FE0 INT_STATUS . . . . . . . . . . 64

0x04 5FE4 INT_ENABLE . . . . . . . . . . 64

0x04 5FE8 INT_CLEAR . . . . . . . . . . . 64

0x04 5FEC INT_SET . . . . . . . . . . . . . 64

0x04 5FF4 POWER DOWN . . . . . . . . 64

0x04 5FFC MODULE_ID . . . . . . . . . . 65

0x04 6028 DMA_COUNTER . . . . . . . 67

0x04 602C DMA_CONTROL . . . . . . . 68

0x04 6030 DMA_STATUS . . . . . . . . . 68

0x04 6FE0 INT_STATUS . . . . . . . . . . 68

0x04 6FE4 INT_ENABLE . . . . . . . . . . 68

0x04 6FE8 INT_CLEAR . . . . . . . . . . . 69

0x04 6FEC INT_SET . . . . . . . . . . . . . 69

0x04 6FF4 POWER DOWN . . . . . . . . 69

0x04 6FFC MODULE_ID . . . . . . . . . . 69

0x04 7728 CLK_SMART1_CTL . . . . . 80

0x04 772C CLK_SMART2_CTL . . . . . 81

0x04 7730 GPIO_CLK_Q0_CTL . . . . 81

0x04 7734 GPIO_CLK_Q1_CTL . . . . 81

0x04 7738 GPIO_CLK_Q2_CTL . . . . 81

0x04 773C GPIO_CLK_Q3_CTL . . . . 81

0x04 7740 GPIO_CLK_Q4_CTL . . . . 81

0x04 7744 GPIO_CLK_Q5_CTL . . . . 81

0x04 7750 CLK_MBS2_CTL . . . . . . . 81

0x04 7754—77FC Reserved . . . . . . . . . . . . . 82

0x04 7800 CLK_VMSP1_CTL . . . . . . 82

0x04 7804 CLK_VMSP2_CTL . . . . . . 82

0x04 7808—781C Reserved . . . . . . . . . . . . . 83

0x04 7820 CLK_TS_S11_CTL . . . . . 83

0x04 7824 CLK_TS_S12_CTL . . . . . 83

0x04 7828 CLK_TS_S21_CTL . . . . . 83

0x04 782c CLK_TS_S22_CTL . . . . . 83

0x04 7830 CLK_TS_S31_CTL . . . . . 83

0x04 7834 CLK_TS_S32_CTL . . . . . 83

0x04 7838 Reserved . . . . . . . . . . . . . 84

0x04 783C TSOUT_CLK0_OUT_CTL 84 0x04 7840 TSOUT_SERIAL_CLK0_CTL

0x04 7844—78FF Reserved . . . . . . . . . . . . . 84

0x04 7900—79FF RESERVED . . . . . . . . . . . 84

0x04 7A00 CLK_QVCP1_OUT_CTL . 84 0x04 7A04 CLK_QVCP1_PIX_CTL . . 85 0x04 7A08 CLK_QVCP2_OUT_CTL . 85 0x04 7A0C CLK_QVCP2_PIX_CTL . . 85

0x04 7A10—7A14 Reserved . . . . . . . . . . . . . 85

0x04 7A18 CLK_QVCP1_PROC_CTL 85 0x04 7A1C CLK_QVCP2_PROC_CTL 86

0x04 7A20 Reserved . . . . . . . . . . . . . 86

0x04 7A24—7AFF Reserved . . . . . . . . . . . . . 86

0x04 7B00 CLK_SPDO_CTL . . . . . . . 86

0x04 7B04 AI1_OSCLK_CTL . . . . . . . 86

0x04 7B08 AO1_OSCLK_CTL . . . . . . 87

0x04 7B0C AI2_OSCLK_CTL . . . . . . . 87

0x04 7B10 AO2_OSCLK_CTL . . . . . . 87

0x04 7B14 Reserved . . . . . . . . . . . . . 87

0x04 7B18 CLK_AI1_SCK_O_CTL . . 87 0x04 7B1C CLK_AO1_SCK_O_CTL . 87 0x04 7B20 CLK_AI2_SCK_O_CTL . . 87 0x04 7B24 CLK_AO2_SCK_O_CTL . 87

0x04 7B28 CLK_SPDI2_CTL . . . . . . . 88

0x04 7B2C CLK_SPDI_CTL . . . . . . . . 88

0x04 7B30 CLK_TSTAMP_CTL . . . . . 88

0x04 7B34 CLK_TSDMA_CTL . . . . . . 88

0x04 7B38 Reserved . . . . . . . . . . . . . 88

0x04 7B3C CLK_DVDD_CTL . . . . . . . 88

0x04 7B40 Reserved . . . . . . . . . . . . . 89

Preliminary Rev. 02 — July 22 2004 iii

Page 5

Philips Semiconductors

PNX8550

0x04 7B44 CLK_VPK_CTL . . . . . . . . . 89

0x04 7B48—7FDF Reserved . . . . . . . . . . . . . . 89

0x04 7FE0 INTERRUPT STATUS . . . . 89

0x04 7FE4 INTERRUPT ENABLE . . . . 90

USB Registers (Rev. 1.7.1)

0x4 8000 HcRevision . . . . . . . . . . . . 91

0x4 8004 HcControl . . . . . . . . . . . . . . 92

0x4 8008 HcCommandStatus . . . . . . 92

0x4 800C HcInterruptStatus . . . . . . . . 92

0x4 8010 HcInterruptEnable . . . . . . . 93

0x4 8014 HcInterruptDisable . . . . . . . 93

0x4 8018 HcHCCA . . . . . . . . . . . . . . 94

0x4 801C HcPCED . . . . . . . . . . . . . . 94

0x4 8020 HcCHED . . . . . . . . . . . . . . 94

0x4 8024 HcCCED . . . . . . . . . . . . . . 94

0x4 8028 HcBHED . . . . . . . . . . . . . . 94

0x4 802C HcBCED . . . . . . . . . . . . . . 94

0x4 8030 HcDH . . . . . . . . . . . . . . . . . 94

M-Default Slv

0x04 9FFC . . . . . . . . . . . . . . . . . . . . . . 98

UART1 Registers (Rev. 1.5)

0x4 A000 Line Control and FIFO Control

0x4 A004 Modem Control and Modem

0x4 A008 Baud Rate Register . . . . . 100

0x4 A00C Configuration Register . . . 100 0x4 A028 Receive/Transmit and FIFO

Status Register . . . . . . . . . 99

(RBR/THR/FIFO) Status

0x04 7FE8 INTERRUPT CLEAR . . . . 91

0x04 7FE8 SET INTERRUPT . . . . . . . 91

0x04 74FC—7FF8 RESERVED . . . . . . . . . . . 91

0x04 7FFC MODULE_ID . . . . . . . . . . 91

0x4 8034 HcFMInterval . . . . . . . . . . 94

0x4 8038 HcFMRemaining . . . . . . . 94

0x4 803C HcFMNumber . . . . . . . . . . 95

0x4 8040 HcPeriodic Start . . . . . . . . 95

0x4 8044 HcLSThreshold . . . . . . . . 95

0x4 8048 HcRHDescriptorA . . . . . . . 95

0x4 804C HcRHDescriptorB . . . . . . . 95

0x4 8050 HcRHStatus . . . . . . . . . . . 95

0x4 8054 HcRHPortStatus[1] . . . . . . 96

0x4 8058 HcRHPortStatus[2] . . . . . . 97

0x4 807C Clock Control . . . . . . . . . . 97

0x4 8FFC Module ID . . . . . . . . . . . . . 97

0x4 AFE0 Interrupt Status Register 101 0x4 AFE4 Interrupt Enable Register 102 0x4 AFE8 Interrupt Clear Register . 102 0x4 AFEC Interrupt Set Register . . . 102 0x4 AFF4 Power Down Register . . 102

0x4 AFFC Module ID Register . . . . 102

UART2 Registers (Rev. 1.5)

0x4 B000 Line Control and FIFO Control

0x4 B004 Modem Control and Modem

0x4 B008 Baud Rate Register . . . . . 104

0x4 B00C Configuration Register . . . 104 0x4 B028 Receive/Transmit and FIFO

Fast I2C 4 Registers (Rev. 1.9)

0x04 C000 I2C CONTROL . . . . . . . . 107

0x04 C004 I2C DATA REGISTER . . . 107 0x04 C008 I2C STATUS REGISTER 107 0x04 C00C I2C ADDRESS REGISTER . .

0x04 C010 I2C STOP REGISTER . . . 108

0x04 C014 I2C PD REGISTER . . . . . 108

0x04 C018 I2C BUS SET REGISTER 108 0x04 C01C I2C BUS OBSERVATION

0x04 C020—CFDC Reserved . . . . . . . . . . . . . 108

0x04 CFE0 I2C INTERRUPT STATUS

Global 2 Registers (Rev 0.92)

0x04 D000—D00C Reserved . . . . . . . . . . . . . 110

0x04 D010 MIPS_SUPPORT . . . . . . 110

0x04 D014 SYS_ENDIANNESS . . . . 110

0x04 D018—D04C Reserved . . . . . . . . . . . . . 110

0x04 D050 ENABLE_INTA_O . . . . . . 111

0x04 D054—D1FC Reserved . . . . . . . . . . . . . 111

0x04 D200 DMA_GATE_LO . . . . . . . 111

0x04 D204 DMA_GATE_HI . . . . . . . . 111

0x04 D208 APERTURE_WE . . . . . . . 111

0x04 D20C—D2FC Reserved . . . . . . . . . . . . . 111

0x04 D300 TSIN1_MODE . . . . . . . . . 111

Status Register . . . . . . . . 103

(RBR/THR/FIFO) Status

107

0x4 BFE0 Interrupt Status Register 105 0x4 BFE4 Interrupt Enable Register 106 0x4 BFE8 Interrupt Clear Register . 106 0x4 BFEC Interrupt Set Register . . . 106 0x4 BFF4 Power Down Register . . 106

0x4 BFFC Module ID Register . . . . 106

0x04 CFE4 I2C INTERRUPT ENABLE

0x04 CFE8 I2C INTERRUPT CLEAR

0x04 CFEC I2C INTERRUPT SET

0x04 CFF0 Reserved . . . . . . . . . . . . 109

0x04 CFF4 I2C POWERDOWN

0x04 CFF8 Reserved . . . . . . . . . . . . 109

0x04 CFFC I2C MODULE ID REGISTER

0x04 D304 TSIN2_MODE . . . . . . . . 112

0x04 D308 TSIN3_MODE . . . . . . . . 113

0x04 D30C MSPIN_ROUTE . . . . . . . 114

0x04 D310 TSOUT_MODE . . . . . . . 115

0x04 D314—D4FC Reserved . . . . . . . . . . . . 116

0x04 D500 SCRATCH0 . . . . . . . . . . 116

0x04 D504 SCRATCH1 . . . . . . . . . . 116

0x04 D508 SCRATCH2 . . . . . . . . . . 116

0x04 D50C SCRATCH3 . . . . . . . . . . 116

0x04 D510 SCRATCH4 . . . . . . . . . . 116

0x04 D514 SCRATCH . . . . . . . . . . . 116

109

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PNX8550

0x04 D518 SCRATCH6 . . . . . . . . . . . 116

0x04 D51C SCRATCH7 . . . . . . . . . . . 116

0x04 D520—D600 Reserved . . . . . . . . . . . . . 116

0x04 D604 VIP1_MUX_CTRL . . . . . . 116

0x04 D608 VIP2_MUX_CTRL . . . . . . 116

0x04 D60C MM_CTRL . . . . . . . . . . . . 117

0x04 D610 TUN_CTRL . . . . . . . . . . . 117

0x04 D614 GLBREG2_SPARE_CTRL . .

0x04 D618—D6FC Reserved . . . . . . . . . . . . . 117

0x04 D700 TM32_1_CONTROL . . . . 117

0x04 D704 TM32_1_STATUS . . . . . . 118

0x04 D708 TM32_2_CONTROL . . . . 118

0x04 D70C TM32_2_STATUS . . . . . . 118

0x04 D710—D7FC Reserved . . . . . . . . . . . . . 118

0x04 D800 SEMAPHORE0 . . . . . . . . 118

0x04 D804 SEMAPHORE1 . . . . . . . . 118

0x04 D808 SEMAPHORE2 . . . . . . . . 118

0x04 D80C SEMAPHORE3 . . . . . . . . 118

117

MIPS DCS Network Controller Configuration Registers (Rev 1.6)

0x04 E000 MBC_CTRL . . . . . . . . . . . 120

0x04 E00C MBC_ADDR . . . . . . . . . . 120

0x04 E010 MBC_STAT . . . . . . . . . . . 120

0x04 EFD8 MBC_INT_CLR_ENABLE 121 0x04 EFDC MBC_INT_SET_ENABLE 121

D2D Registers (Rev 1.13)

0x04 F400 Source Address Base . . . 122 0x04 F404 Destination Address Base 123

0x04 F408 Pixel Size . . . . . . . . . . . . . 123

0x04 F40C Source Linear . . . . . . . . . 123

0x04 F410 Destination Linear . . . . . . 123

0x04 F414 Source Stride . . . . . . . . . . 124

0x04 F418 Destination Stride . . . . . . 124

0x04 F41C Color Compare . . . . . . . . 124

0x04 F420 Mono Host F Color or

0x04 F424 Mono Host B Color or HAlpha

0x04 F428 Blt Control . . . . . . . . . . . . 124

0x04 F42C Source Address, XY

0x04 F430 Destination Address, XY

0x04 F434 BLT Size . . . . . . . . . . . . . 126

SurfAlpha . . . . . . . . . . . . . 124

Color . . . . . . . . . . . . . . . . 124

Coordinates . . . . . . . . . . . 126

0x04 D810 SEMAPHORE4 . . . . . . . 118

0x04 D814 SEMAPHORE5 . . . . . . . 119

0x04 D818 SEMAPHORE6 . . . . . . . 119

0x04 D81C SEMAPHORE7 . . . . . . . 119

0x04 D820 SEMAPHORE8 . . . . . . . 119

0x04 D824 SEMAPHORE9 . . . . . . . 119

0x04 D828 SEMAPHORE10 . . . . . . 119

0x04 D82C SEMAPHORE11 . . . . . . 119

0x04 D830 SEMAPHORE12 . . . . . . 119

0x04 D834 SEMAPHORE13 . . . . . . 119

0x04 D838 SEMAPHORE14 . . . . . . 119

0x04 D83C SEMAPHORE15 . . . . . . 119

0x04 D840—DFF0 Reserved . . . . . . . . . . . . 119

0x04 DFF4

0x04 DFF8 Reserved . . . . . . . . . . . . 119

0x04 DFFC GLB_REG_2_MOD _ID . 119

0x04 EFE0 MBC_INT_STATUS . . . . 121

0x04 EFE4 MBC_INT_EN . . . . . . . . 121

0x04 EFE8 MBC_INT_CLR . . . . . . . 122

0x04 EFEC MBC_INT_SET . . . . . . . 122

0x04 EFFC MBC_MODULE_ID . . . . 122

0x04 F438 Destination Address, XY2

0x04 F43C Vector Constant . . . . . . . 127

0x04 F440 Vector Count Control . . . 127

0x04 F444 TransMask . . . . . . . . . . . 127

0x04 F5F8 MonoPatFColor . . . . . . . 127

0x04 F5FC MonoPatBColor . . . . . . . 127

0x04 F800 EngineStatus . . . . . . . . . 127

0x04 F804 PanicControl . . . . . . . . . . 128

0x04 F808 EngineConfig . . . . . . . . . 128

0x04 F80C HostFIFOStatus . . . . . . . 129

0x04 FFF4 POWERDOWN . . . . . . . 129

0x04 FFFC DeviceID . . . . . . . . . . . . . 129

0x04 F600—F6FF PatRamMono . . . . . . . . . 129

0x04 F700—F7FF PatRamColor (256 bytes) 130 0x05 0000—FFFF Host Data (64 kB - Memory

GLB_REG_2_POWER_DOW

N . . . . . . . . . . . . . . . . . . . 119

Coordinates . . . . . . . . . . 126

Space) . . . . . . . . . . . . . . 130

Reset Registers (Rev 0.4)

0x06 0000 RST_CTL . . . . . . . . . . . . . 130

0x06 0004 RST_CAUSE . . . . . . . . . . 130

0x06 0008 EN_WATCHDOG_RST . . 130

0x06 000C—0FF8 Reserved . . . . . . . . . . . . 130

0x06 0FFC MODULE_ID . . . . . . . . . 130

TM3260_Debug 1 Registers (Rev 1.6.1)

0x06 1000 TM_DBG_1_DATA_IN . . 131 0x06 1004 TM_DBG_1_DATA_OUT 131

0x06 1008 TM_DBG_1_CTRL1 . . . . 131

0x06 100C TM_DBG_1_CTRL2 . . . . 131

0x06 1FE0 TM_DBG_1_INT_ST . . . . 131

0x06 1FE4 TM_DBG_1_INT_EN . . . . 131

0x06 1FE8 TM_DBG_1_INT_CLR . . 131 0x06 1FEC TM_DBG_1_INT_SET . . 131 0x06 1FF4 TM_DBG_1_POWER_DOWN

0x06 1FFC MODULE ID . . . . . . . . . . 132

131

TM3260_Debug 2 Registers (Rev 1.6.1)

0x06 2000 TM_DBG_1_DATA_IN . . 132 0x06 2004 TM_DBG_1_DATA_OUT 132

0x06 2008 TM_DBG_1_CTRL1 . . . . 132

0x06 200C TM_DBG_1_CTRL2 . . . . 132

0x06 2FE0 TM_DBG_1_INT_ST . . . . 132

0x06 2FE4 TM_DBG_1_INT_EN . . . . 132

0x06 2FE8 TM_DBG_1_INT_CLR . . 132 0x06 2FEC TM_DBG_1_INT_SET . . 132 0x06 2FF4 TM_DBG_1_POWER_DOWN

0x06 2FFC MODULE ID . . . . . . . . . . 133

133

Global 1 Registers (Rev 0.92)

Preliminary Rev. 02 — July 22 2004 v

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Philips Semiconductors

PNX8550

0x06 3500 SCRATCH0 . . . . . . . . . . . 133

0x06 3504 SCRATCH1 . . . . . . . . . . . 133

0x06 3508 SCRATCH2 . . . . . . . . . . . 133

0x06 350C SCRATCH3 . . . . . . . . . . . 133

0x06 3510—3700 Reserved . . . . . . . . . . . . . 133

0x06 3704 TM1_TIMER1MUX_CNTL 133 0x06 3708 TM1_TIMER2MUX_CNTL 133 0x06 370C TM1_TIMER3MUX_CNTL 134 0x06 3710 TM1_TIMER4MUX_CNTL 134 0x06 3714 TM2_TIMER1MUX_CNTL 134 0x06 3718 TM2_TIMER2MUX_CNTL 134

PMAN Hub Arbiter Registers (Rev 0.6)

0x06 4000—41FC Entries of TDMA Timing Wheel

0x06 4200—423C Entries of Priority List (Set A)

0x06 4280—42BC Entries of Round Robin List #1

0x06 4300—431C Entries of Round Robin List #2

0x06 4400—45FC Entries of TDMA Timing Wheel

0x06 4600—463F Entries of Priority List (Set B)

(Set A) . . . . . . . . . . . . . . . 137

137

(Set A) . . . . . . . . . . . . . . . 137

(Set B) . . . . . . . . . . . . . . . 137

DDR SDRAM Controller Registers (Rev 0.36)

0x06 5000 IP_2031_CTL . . . . . . . . . 139

0x06 5004

0x06 5008 IP_2031_AUTO_HALT_LIMIT

0x06 5010 IP_2031_RANK0_ADDR_LO

0x06 5014 IP_2031_RANK0_ADDR_HI .

0x06 5018 IP_2031_RANK1_ADDR_HI .

0x06 5040

0x06 5044

0x06 5048

0x06 5080 IP_2031_DDR_MR . . . . . 141

0x06 5084 IP_2031_DDR_EMR . . . . 141

0x06 5088

0x06 50C0

0x06 50C4

0x06 50D0

0x06 50D4

0x06 5100 IP_2031_DDR_TRCD . . . 142

0x06 5104 IP_2031_DDR_TRC . . . . 142

0x06 5108 IP_2031_DDR_TWTR . . . 142

0x06 510C IP_2031_DDR_TWR . . . . 142

0x06 5110 IP_2031_DDR_TRP . . . . 142

0x06 5114 IP_2031_DDR_TRAS . . . 142 0x06 511C IP_2031_DDR_TRRD . . .142 0x06 5120 IP_2031_DDR_TRFC . . . 142 0x06 5124 IP_2031_DDR_TMRD . . . 142 0x06 5128 IP_2031_DDR_TCAS . . . 142 0x06 512C IP_2031_DDR_RF_PERIOD .

0x06 5180 IP_2031_ARB_CTL . . . . . 143

IP_2031_DDR_DEF_BANK_S

WITCH . . . . . . . . . . . . . . . 139

140

IP_2031_DDR_REGION1_BA

SE . . . . . . . . . . . . . . . . . . 140

IP_2031_DDR_REGION1_MA

SK . . . . . . . . . . . . . . . . . . 140

IP_2031_DDR_REGION1_BA

NK_SWITCH . . . . . . . . . . 140

IP_2031_DDR_PRECHARGE

_BIT . . . . . . . . . . . . . . . . . 141

IP_2031_RANK0_ROW_WID

TH . . . . . . . . . . . . . . . . . . 141

IP_2031_RANK0_COLUMN_

WIDTH . . . . . . . . . . . . . . . 141

IP_2031_RANK1_ROW_WID

TH . . . . . . . . . . . . . . . . . . 141

IP_2031_RANK1_COLUMN_

WIDTH . . . . . . . . . . . . . . . 141

143

0x06 371C TM2_TIMER3MUX_CNTL 135 0x06 3720 TM2_TIMER4MUX_CNTL 135

0x06 3724—37FC Reserved . . . . . . . . . . . . 135

0x06 3800 SPDI1_MUX_SEL . . . . . 135

0x06 3804 SPDI2_MUX_SEL . . . . . 136

0x06 3808—3FF0 Reserved . . . . . . . . . . . . 136

0x06 3FF4

0x06 3FF8 Reserved . . . . . . . . . . . . 136

0x06 3FFC GLB_REG_1_MOD _ID . 136

0x06 4680—46BC Entries of Round Robin List #1

0x06 4700—471C Entries of Round Robin List #2

0x06 4800 NR_ENTRIES_A (Set A) 137 0x06 4804 NR_ENTRIES_B (Set B) 138

0x06 4900 Arbiter Control . . . . . . . . 138

0x06 4904 Arbiter Status . . . . . . . . . 138

0x06 4FFC Arbiter Module_ID . . . . . 138

0x06 5184

0x06 5188

0x06 51C0 IP_2031_ARB_CPU_LIMIT .

0x06 51C4 IP_2031_ARB_CPU_RATIO

0x06 51C8 IP_2031_ARB_CPU_CLIP . .

0x06 51CC IP_2031_ARB_CPU_DECR .

0x06 51D0 IP_2031_ARB_CPU1_LIMIT

0x06 51D4 IP_2031_ARB_CPU1_RATIO

0x06 51D8 IP_2031_ARB_CPU1_CLIP .

0x06 51DC IP_2031_ARB_CPU1_DECR

0x06 51E0 IP_2031_ARB_CPU2_LIMIT

0x06 51E4 IP_2031_ARB_CPU2_RATIO

0x06 51E8 IP_2031_ARB_CPU2_CLIP .

0x06 51EC IP_2031_ARB_CPU2_DECR

0x06 51F0 IP_2031_ARB_CPU3_LIMIT

0x06 51F4 IP_2031_ARB_CPU3_RATIO

0x06 51F8 IP_2031_ARB_CPU3_CLIP .

0x06 51FC IP_2031_ARB_CPU3_DECR

0x06 5200

0x06 5204

0x06 5208

0x06 520C

0x06 5210

GLB_REG_1_POWER_DOW

N . . . . . . . . . . . . . . . . . . . 136

137

(Set B) . . . . . . . . . . . . . . 137

IP_2031_ARB_HRT_WINDO

W . . . . . . . . . . . . . . . . . . 144

IP_2031_ARB_CPU_WINDO

W . . . . . . . . . . . . . . . . . . 144

144

145

146

IP_2031_PF_MTL0_RD_VALI

D . . . . . . . . . . . . . . . . . . . 146

IP_2031_PF_MTL0_WR_ACC

EPT . . . . . . . . . . . . . . . . 146

IP_2031_PF_MTL1_RD_VALI

D . . . . . . . . . . . . . . . . . . . 146

IP_2031_PF_MTL1_WR_ACC

EPT . . . . . . . . . . . . . . . . 146

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Philips Semiconductors

PNX8550

IP_2031_PF_MTL2_RD_VALI

0x06 5214

0x06 5218

0x06 521C

0x06 5240 IP_2031_PF_IDLE . . . . . . 146

D . . . . . . . . . . . . . . . . . . . 146

IP_2031_PF_MTL2_WR_ACC

EPT . . . . . . . . . . . . . . . . . 146

IP_2031_PF_MTL3_RD_VALI

D . . . . . . . . . . . . . . . . . . . 146

IP_2031_PF_MTL3_WR_ACC

EPT . . . . . . . . . . . . . . . . . 146

PMAN Security Registers (Rev 0.6)

0x06 6000 Protection Error Address . 147 0x06 6004 Register Write Protect . . . 147

0x06 6080 Sandbox 1 Lower . . . . . . . 147

0x06 6084 Sandbox 1 Upper . . . . . . . 148

0x06 6088 Sandbox 2 Lower . . . . . . . 148

0x06 608C Sandbox 2 Upper . . . . . . . 148

0x06 6090 Sandbox 3 Lower . . . . . . . 148

0x06 6094 Sandbox 3 Upper . . . . . . . 148

0x06 6098 Sandbox 4 Lower . . . . . . . 148

0x06 609C Sandbox 4 Upper . . . . . . . 148

0x06 6100 Sandbox Assignment VMPG .

0x06 6104 Sandbox Assignment DVDD .

0x06 6108 Sandbox Assignment EDMA .

0x06 610C Sandbox Assignment VLD . . .

0x06 6110 Sandbox Assignment QVCP2L

0x06 6114 Sandbox Assignment MBS_R

0x06 6118 Sandbox Assignment MBS_W

0x06 611C Sandbox Assignment

0x06 6120 Sandbox Assignment

0x06 6124 Sandbox Assignment

0x06 6128 Sandbox Assignment

0x06 612C Sandbox Assignment QVCP5L

0x06 6130 Sandbox Assignment ID12 . .

148

149

150

MBS2_R . . . . . . . . . . . . . 150

MBS2_W . . . . . . . . . . . . . 150

QTNR_R . . . . . . . . . . . . . 151

QTNR_W . . . . . . . . . . . . . 151

151

0x06 5280 IP_2031_ERR_VALID . . 147 0x06 5284 IP_2031_ERR_MTL_PORT .

0x06 5288

0x06 528C

0x06 5290 IP_2031_ERR_MTL_CMD_ID

0x06 0FFC IP_2031_MODULE_ID . . 147

0x06 6134 Sandbox Assignment

0x06 6138 Sandbox Assignment USB . .

0x06 613C Sandbox Assignment DE 153 0x06 6140 Sandbox Assignment PCI 153 0x06 6144 Sandbox Assignment

0x06 6148 Sandbox Assignment I2C 154 0x06 614C Sandbox Assignment MGATE

0x06 6150 Sandbox Assignment VIP1 .

0x06 6154 Sandbox Assignment VIP2 .

0x06 6158 Sandbox Assignment VPK . .

0x06 615C Sandbox Assignment TSDMA

0x06 6160 Sandbox Assignment MSP1

0x06 6164 Sandbox Assignment MSP2

0x06 6168-6FDC Reserved . . . . . . . . . . . . 156

0x06 6FE0 PMAN Security Interrupt

0x06 6FE4 PMAN Security Interrupt

0x06 6FE8 PMAN Security Interrupt Clear

0x06 6FEC PMAN Security Interrupt Set

0x06 6FFC Module ID . . . . . . . . . . . . 156

147

IP_2031_ERR_MTL_CMD_A

DDR . . . . . . . . . . . . . . . . 147

IP_2031_ERR_MTL_CMD_R

EAD . . . . . . . . . . . . . . . . 147

147

151

TUNNEL . . . . . . . . . . . . . 152

152

SMC(1+2) . . . . . . . . . . . . 153

154

155

Status . . . . . . . . . . . . . . . 156

Enable . . . . . . . . . . . . . . 156

156

Memory Bandwidth Monitor Registers (Rev 0.6)

0x06 7000 count1_device_&_mode . 156 0x06 7004 count2_device_&_mode . 157 0x06 7008 count3_device_&_mode . 157

0x06 700C counter_control . . . . . . . . 157

0x06 7010 counter1_value_lo . . . . . . 158

0x06 7014 counter1_value_hi . . . . . . 158

0x06 7018 counter2_value_lo . . . . . . 158

0x06 701C counter2_value_hi . . . . . . 158

0x06 7020 counter3_value_lo . . . . . 158

0x06 7024 counter3_value_hi . . . . . 158

0x06 7025—7FEC Reserved . . . . . . . . . . . . 158

0x06 7FF0 Software_reset . . . . . . . . 158

0x06 7FF4 Powerdown . . . . . . . . . . 158

0x06 7FF8 Module_ID_ext . . . . . . . . 159

0x06 7FFC Module_ID . . . . . . . . . . . 159

MDCS Controller Security Registers (Rev 1.6)

0x06 8000 MBC_CONFIG (Bus Controller

0x06 8004 MBC_SEC (Bus Controller

Configuration Aperture

Security Setting) . . . . . . . 159

Security Aperture Security

0x06 8200-8274 Target Security Registers

0x06 8278-8FFC Reserved . . . . . . . . . . . . 160

0x06 8FFC MBCSEC_MODULE_ID . 160

Setting) . . . . . . . . . . . . . . 159

(One for each target) . . . 159

Fast I2C 3 Registers (Rev 1.9)

0x06 9000 I2C CONTROL . . . . . . . . 160

0x06 9004 I2C DATA REGISTER . . . 160 0x06 9008 I2C STATUS REGISTER 161 0x06 900C I2C ADDRESS REGISTER . .

0x06 9010 I2C STOP REGISTER . . . 161

Preliminary Rev. 02 — July 22 2004 vii

161

0x06 9014 I2C PD REGISTER . . . . 161

0x06 9018 I2C BUS SET REGISTER 161 0x06 901C I2C BUS OBSERVATION

0x06 9020—9FDC Reserved . . . . . . . . . . . . 162

0x06 9FE0 I2C INTERRUPT STATUS

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Philips Semiconductors

PNX8550

0x06 9FE4 I2C INTERRUPT ENABLE

0x06 9FE8 I2C INTERRUPT CLEAR

0x06 9FEC I2C INTERRUPT SET

M-Default Slv

0x06 AFFC . . . . . . . . . . . . . . . . . . . . . 163

T-Default Slv

0x10 0FFC . . . . . . . . . . . . . . . . . . . . . 163

GIC_TM32_1 Registers (Rev 1.6.1)

0x10 2000 int_priority_0 . . . . . . . . . . 163

0x10 2004 int_priority_1 . . . . . . . . . . 164

0x10 2100 int_vector_0 . . . . . . . . . . . 164

0x10 2104 int_vector_1 . . . . . . . . . . . 165

0x10 2200 int_pending_1_31 . . . . . . 165

0x10 2204 int_pending_32_63 . . . . . 165

0x10 2208 int_pending_64_70 . . . . . 166

0x10 2300 int_features . . . . . . . . . . . 166

0x10 2404 int_request_reg_1 . . . . . . 166

0x10 2408 int_request_reg_2 . . . . . . 168

0x10 240C int_request_reg_3 . . . . . . 168

0x10 2410 int_request_reg_4 . . . . . . 168

0x10 2414 int_request_reg_5 . . . . . . 168

0x10 2418 int_request_reg_6 . . . . . . 168

0x10 241C int_request_reg_7 . . . . . . 168

0x10 2420 int_request_reg_8 . . . . . . 168

0x10 2424 int_request_reg_9 . . . . . . 168

0x10 2428 int_request_reg_10 . . . . . 168

0x10 242C int_request_reg_11 . . . . . 168

0x10 2430 int_request_reg_12 . . . . . 168

0x10 2434 int_request_reg_13 . . . . . 168

0x10 2438 int_request_reg_14 . . . . . 168

0x10 243C int_request_reg_15 . . . . . 168

0x10 2440 int_request_reg_16 . . . . . 169

0x10 2444 int_request_reg_17 . . . . . 169

0x10 2448 int_request_reg_18 . . . . . 169

0x10 244C int_request_reg_19 . . . . . 169

0x10 2450 int_request_reg_20 . . . . . 169

0x10 2454 int_request_reg_21 . . . . . 169

0x10 2458 int_request_reg_22 . . . . . 169

0x10 245C int_request_reg_23 . . . . . 169

0x10 2460 int_request_reg_24 . . . . . 169

0x10 2464 int_request_reg_25 . . . . . 169

0x10 2468 int_request_reg_26 . . . . . 169

0x10 246C int_request_reg_27 . . . . . 169

0x10 2470 int_request_reg_28 . . . . . 169

0x10 2474 int_request_reg_29 . . . . . 169

0x10 2478 int_request_reg_30 . . . . . 169

0x10 247C int_request_reg_31 . . . . . 169

0x10 2480 int_request_reg_32 . . . . . 169

0x06 9FF0 Reserved . . . . . . . . . . . . 162

0x06 9FF4 I2C POWERDOWN

0x06 9FF8 Reserved . . . . . . . . . . . . 162

0x06 9FFC I2C MODULE ID REGISTER

0x10 2484 int_request_reg_33 . . . . 169

0x10 2488 int_request_reg_34 . . . . 169

0x10 248C int_request_reg_35 . . . . 170

0x10 2490 int_request_reg_36 . . . . 170

0x10 2494 int_request_reg_37 . . . . 170

0x10 2498 int_request_reg_38 . . . . 170

0x10 249C int_request_reg_39 . . . . 170

0x10 24A0 int_request_reg_40 . . . . 170

0x10 24A4 int_request_reg_41 . . . . 170

0x10 24A8 int_request_reg_42 . . . . 170

0x10 24AC int_request_reg_43 . . . . 170

0x10 24B0 int_request_reg_44 . . . . 170

0x10 24B4 int_request_reg_45 . . . . 170

0x10 24B8 int_request_reg_46 . . . . 170

0x10 24BC int_request_reg_47 . . . . 170

0x10 24C0 int_request_reg_48 . . . . 170

0x10 24C4 int_request_reg_49 . . . . 170

0x10 24C8 int_request_reg_50 . . . . 170

0x10 24CC int_request_reg_51 . . . . 170

0x10 24D0 int_request_reg_52 . . . . 170

0x10 24D4 int_request_reg_53 . . . . 171

0x10 24D8 int_request_reg_54 . . . . 171

0x10 24DC int_request_reg_55 . . . . 171

0x10 24E0 int_request_reg_56 . . . . 171

0x10 24E4 int_request_reg_57 . . . . 171

0x10 24E8 int_request_reg_58 . . . . 171

0x10 24EC int_request_reg_59 . . . . 171

0x10 24F0 int_request_reg_60 . . . . 171

0x10 24F4 int_request_reg_61 . . . . 171

0x10 24F8 int_request_reg_62 . . . . 171

0x10 24FC int_request_reg_63 . . . . 171

0x10 2500 int_request_reg_64 . . . . 171

0x10 2504 int_request_reg_65 . . . . 171

0x10 2508 int_request_reg_66 . . . . 171

0x10 250C int_request_reg_67 . . . . 171

0x10 2510 int_request_reg_68 . . . . 171

0x10 2514 int_request_reg_69 . . . . 171

0x10 2518 int_request_reg_70 . . . . 171

0x10 2FFC MOD_ID . . . . . . . . . . . . . 172

163

TriMedia DCS Network Controller Configuration Registers (Rev 1.6)

0x10 3000 TMBC_CTRL . . . . . . . . . . 172

0x10 300C TMBC_ADDR . . . . . . . . . 172

0x10 3010 TMBC_STAT . . . . . . . . . . 172

0x10 3FD8 TMBC_INT_CLR_ENABLE . .

0x10 3FDC TMBC_INT_SET_ENABLE . .

173

0x10 3FE0 TMBC_INT_STATUS . . . 174

0x10 3FE4 TMBC_INT_EN . . . . . . . 174

0x10 3FE8 TMBC_INT_CLR . . . . . . 174

0x10 3FEC TMBC_INT_SET . . . . . . 174

0x10 3FFC TMBC_MODULE_ID . . . 174

173

GPIO Registers (Rev 1.2)

0x10 4000 Mode Control for GPIOs 15—0

0x10 4004 Mode Control for GPIOs 31—

0x10 4008 Mode Control for GPIOs 47—

0x10 400C Mode Control for GPIOs 63—

Preliminary Rev. 02 — July 22 2004 viii

175

16 . . . . . . . . . . . . . . . . . . . 175

32 . . . . . . . . . . . . . . . . . . . 176

0x10 4010 Mask and IO Data for GPIOs

0x10 4014 Mask and IO Data for GPIOs

0x10 4018 Mask and IO Data for GPIOs

48 . . . . . . . . . . . . . . . . . . 176

15—0 . . . . . . . . . . . . . . . 176

31—16 . . . . . . . . . . . . . . 177

47—32 . . . . . . . . . . . . . . 177

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Philips Semiconductors

PNX8550

0x10 401C Mask and IO Data for GPIOs

0x10 4080 Internal Signals . . . . . . . . 177

0x10 40C0 TIME_CTR . . . . . . . . . . . . 178

0x10 40D0 IRW_LOW . . . . . . . . . . . . 178

0x10 40D4 IRW_HIGH . . . . . . . . . . . . 178

0x10 40D8 IRW_CTRL . . . . . . . . . . . 178

0x10 4100 EQ0_CTL . . . . . . . . . . . . . 179

0x10 4104 EQ0_IO_SEL . . . . . . . . . . 181

0x10 4108 EQ0_BUF_CTRL . . . . . . . 181

0x10 410C EQ0_BASE1_PTR . . . . . . 182

0x10 4110 EQ0_BASE2_PTR . . . . . . 182

0x10 4114 EQ0_SIZE . . . . . . . . . . . . 182

0x10 4118 EQ0_DIVIDER . . . . . . . . . 182

0x10 4140 EQ1_CTL . . . . . . . . . . . . . 183

0x10 4144 EQ1_IO_SEL . . . . . . . . . . 183

0x10 4148 EQ1_BUF_CTRL . . . . . . . 183

0x10 414C EQ1_BASE1_PTR . . . . . . 183

0x10 4150 EQ1_BASE2_PTR . . . . . . 183

0x10 4154 EQ1_SIZE . . . . . . . . . . . . 184

0x10 4158 EQ1_DIVIDER . . . . . . . . . 184

0x10 4180 EQ2_CTL . . . . . . . . . . . . . 184

0x10 4184 EQ2_IO_SEL . . . . . . . . . . 184

0x10 4188 EQ2_BUF_CTRL . . . . . . . 184

0x10 418C EQ2_BASE1_PTR . . . . . . 184

0x10 4190 EQ2_BASE2_PTR . . . . . . 184

0x10 4194 EQ2_SIZE . . . . . . . . . . . . 184

0x10 4198 EQ2_DIVIDER . . . . . . . . . 184

0x10 41C0 EQ3_CTL . . . . . . . . . . . . . 184

0x10 41C4 EQ3_IO_SEL . . . . . . . . . . 184

0x10 41C8 EQ3_BUF_CTRL . . . . . . . 184

0x10 41CC EQ3_BASE1_PTR . . . . . . 184

0x10 41D0 EQ3_BASE2_PTR . . . . . . 184

0x10 41D4 EQ3_SIZE . . . . . . . . . . . . 184

0x10 41D8 EQ3_DIVIDER . . . . . . . . . 184

0x10 4200 EQ4_CTL . . . . . . . . . . . . . 184

0x10 4204 EQ4_IO_SEL . . . . . . . . . . 184

0x10 4208 EQ4_BUF_CTRL . . . . . . . 184

0x10 420C EQ4_BASE1_PTR . . . . . . 185

0x10 4210 EQ4_BASE2_PTR . . . . . . 185

0x10 4214 EQ4_SIZE . . . . . . . . . . . . 185

0x10 4218 EQ4_DIVIDER . . . . . . . . . 185

0x10 4240 EQ5_CTL . . . . . . . . . . . . . 185

0x10 4244 EQ5_IO_SEL . . . . . . . . . . 185

0x10 4248 EQ5_BUF_CTRL . . . . . . . 185

0x10 424C EQ5_BASE1_PTR . . . . . . 185

0x10 4250 EQ5_BASE2_PTR . . . . . . 185

0x10 4254 EQ5_SIZE . . . . . . . . . . . . 185

0x10 4258 EQ5_DIVIDER . . . . . . . . . 185

0x10 4400 TSU0_CTL . . . . . . . . . . . . 185

0x10 4404 TSU0_DATA . . . . . . . . . . 185

0x10 4410 TSU1_CTL . . . . . . . . . . . . 185

0x10 4414 TSU1_DATA . . . . . . . . . . 186

0x10 4420 TSU2_CTL . . . . . . . . . . . . 186

0x10 4424 TSU2_DATA . . . . . . . . . . 186

0x10 4430 TSU3_CTL . . . . . . . . . . . . 186

0x10 4434 TSU3_DATA . . . . . . . . . . 186

0x10 4440 TSU4_CTL . . . . . . . . . . . . 186

0x10 4444 TSU4_DATA . . . . . . . . . . 186

0x10 4450 TSU5_CTL . . . . . . . . . . . . 186

0x10 4454 TSU5_DATA . . . . . . . . . . 186

0x10 4460 TSU6_CTL . . . . . . . . . . . . 186

0x10 4464 TSU6_DATA . . . . . . . . . . 186

0x10 4470 TSU7_CTL . . . . . . . . . . . . 186

0x10 4474 TSU7_DATA . . . . . . . . . . 186

0x10 4480 TSU8_CTL . . . . . . . . . . . . 186

0x10 4484 TSU8_DATA . . . . . . . . . . 186

0x10 4490 TSU9_CTL . . . . . . . . . . . . 186

0x10 4494 TSU9_DATA . . . . . . . . . . 186

0x10 44A0 TSU10_CTL . . . . . . . . . . . 186

0x10 44A4 TSU10_DATA . . . . . . . . . 186

0x10 44B0 TSU11_CTL . . . . . . . . . . . 187

0x10 44B4 TSU11_DATA . . . . . . . . . 187

0x10 44C0 TSU12_CTL . . . . . . . . . . . 187

0x10 44C4 TSU12_DATA . . . . . . . . . 187

0x10 44D0 TSU13_CTL . . . . . . . . . . . 187

0x10 44D4 TSU13_DATA . . . . . . . . . 187

0x10 44E0 TSU14_CTL . . . . . . . . . . . 187

0x10 44E4 TSU14_DATA . . . . . . . . . 187

0x10 44F0 TSU15_CTL . . . . . . . . . . . 187

63—48 . . . . . . . . . . . . . . . 177

0x10 44F4 TSU15_DATA . . . . . . . . 187

0x10 4500 DIRQ_0 Select . . . . . . . . 187

0x10 4504 DIRQ_1 Select . . . . . . . . 187

0x10 4508 DIRQ_2 Select . . . . . . . . 187

0x10 450C DIRQ_3 Select . . . . . . . . 187

0x10 4510 DIRQ_4 Select . . . . . . . . 187

0x10 4514 DIRQ_5 Select . . . . . . . . 187

0x10 4518 DIRQ_6 Select . . . . . . . . 187

0x10 451C DIRQ_7 Select . . . . . . . . 187

0x10 4600 CTU0_CTL . . . . . . . . . . . 188

0x10 4604 CTU0_PRESET . . . . . . . 188

0x10 4608 CTU0_MATCH . . . . . . . . 188

0x10 460C CTU0_CURRENT . . . . . 188

0x10 4610 CTU1_CTL . . . . . . . . . . . 188

0x10 4614 CTU1_PRESET . . . . . . . 189

0x10 4618 CTU1_MATCH . . . . . . . . 189

0x10 461C CTU1_CURRENT . . . . . 189

0x10 4620 CTU2_CTL . . . . . . . . . . . 189

0x10 4624 CTU2_PRESET . . . . . . . 189

0x10 4628 CTU2_MATCH . . . . . . . . 189

0x10 462C CTU2_CURRENT . . . . . 189

0x10 4630 CTU3_CTL . . . . . . . . . . . 189

0x10 4634 CTU3_PRESET . . . . . . . 189

0x10 4638 CTU3_MATCH . . . . . . . . 189

0x10 463C CTU3_CURRENT . . . . . 189

0x10 4F30 INT_STATUS0 (EQ 0) . . 189 0x10 4F34 INT_ENABLE0 (EQ0) . . . 190

0x10 4F38 INT_CLEAR0 (EQ0) . . . . 190

0x10 4F3C INT_SET0 (EQ0) . . . . . . 190

0x10 4F40 INT_STATUS1 (EQ 1) . . 190 0x10 4F44 INT_ENABLE1 (EQ1) . . . 190

0x10 4F48 INT_CLEAR1 (EQ1) . . . . 190

0x10 4F4C INT_SET1 (EQ1) . . . . . . 190

0x10 4F50 INT_STATUS2 (EQ 2) . . 190 0x10 4F54 INT_ENABLE2 (EQ2) . . . 191

0x10 4F58 INT_CLEAR2 (EQ2) . . . . 191

0x10 4F5C INT_SET2 (EQ2) . . . . . . 191

0x10 4F60 INT_STATUS3 (EQ 3) . . 191 0x10 4F64 INT_ENABLE3 (EQ3) . . . 191

0x10 4F68 INT_CLEAR3 (EQ3) . . . . 191

0x10 4F6C INT_SET3 (EQ3) . . . . . . 191

0x10 4F70 INT_STATUS4 (EQ 4) . . 191 0x10 4F74 INT_ENABLE4 (EQ4) . . . 191

0x10 4F78 INT_CLEAR4 (EQ4) . . . . 191

0x10 4F7C INT_SET4 (EQ4) . . . . . . 191

0x10 4F80 INT_STATUS5 (EQ 5) . . 191 0x10 4F84 INT_ENABLE5 (EQ5) . . . 191

0x10 4F88 INT_CLEAR5 (EQ5) . . . . 191

0x10 4F8C INT_SET5 (EQ5) . . . . . . 191

0x10 4F90 INT_STATUS6 (TSU[7:0] for

0x10 4F94 INT_ENABLE6 (TSU[7:0] for

0x10 4F98 INT_CLEAR6 (TSU[7:0] for

0x10 4F9C INT_SET6 (TSU[7:0] for

0x10 4FA0 INT_STATUS7 (TSU[7:0] for

0x10 4FA4 INT_ENABLE7 (TSU[7:0] for

0x10 4FA8 INT_CLEAR7 (TSU[7:0] for

0x10 4FAC INT_SET7 (TSU[7:0] for MIPS)

0x10 4FB0 INT_STATUS8 (TSU[15:8] for

0x10 4FB4 INT_ENABLE8 (TSU[15:8] for

0x10 4FB8 INT_CLEAR8 (TSU[15:8] for

0x10 4FBC INT_SET8 (TSU[15:8] for

0x10 4FC0 INT_STATUS9 (TSU[15:8] for

0x10 4FC4 INT_ENABLE9 (TSU[15:8] for

0x10 4FC8 INT_CLEAR9 (TSU[15:8] for

0x10 4FCC INT_SET9 (TSU[15:8] for

TriMedia) . . . . . . . . . . . . 191

TriMedia) . . . . . . . . . . . . 192

TriMedia) . . . . . . . . . . . . 193

MIPS) . . . . . . . . . . . . . . . 194

194

TriMedia) . . . . . . . . . . . . 194

TriMedia) . . . . . . . . . . . . 195

TriMedia) . . . . . . . . . . . . 196

MIPS) . . . . . . . . . . . . . . . 197

Preliminary Rev. 02 — July 22 2004 ix

Page 11

Philips Semiconductors

PNX8550

0x10 4FD0 INT_STATUS10

0x10 4FD4 INT_ENABLE10

0x10 4FD8 INT_CLEAR10

0x10 4FDC INT_SET10 (IRW+CTU[3:0]

MIPS) . . . . . . . . . . . . . . . . 197

(IRW+CTU[3:0] for TriMedia) 197

(IRW+CTU[3:0] for TriMedia) 198

MPEG Video Decoder Registers (Rev 0.5)

0x10 5000 VLD_COMMAND . . . . . . . 199

0x10 5004 VLD_SR . . . . . . . . . . . . . . 199

0x10 5008 VLD_QS . . . . . . . . . . . . . 199

0x10 500C VLD_PI . . . . . . . . . . . . . . 199

0x10 5010 VLD_MC_STATUS . . . . . 200

0x10 5014 VLD_IE . . . . . . . . . . . . . . 201

0x10 5018 VLD_CTL . . . . . . . . . . . . . 201

0x10 501C VLD_INP_ADR . . . . . . . . 202

0x10 5020 VLD_INP_CNT . . . . . . . . 202

0x10 5024 VLD_MBH_ADR . . . . . . . 202

0x10 5028 VLD_MBH_CNT . . . . . . . 202

0x10 502C VLD_RL_ADR . . . . . . . . . 202

0x10 5030 VLD_RL_CNT . . . . . . . . . 202

0x10 5034 VLD_BIT_CNT . . . . . . . . . 202

0x10 5038 LINE_SIZE . . . . . . . . . . . . 202

0x10 5040 W_TBL0_W0 . . . . . . . . . . 203

0x10 5044 W_TBL0_W1 . . . . . . . . . . 203

0x10 5048 W_TBL0_W2 . . . . . . . . . . 203

0x10 504C W_TBL0_W3( . . . . . . . . . 203

0x10 5050 W_TBL0_W4 . . . . . . . . . . 203

0x10 5054 W_TBL0_W5 . . . . . . . . . . 203

0x10 5058 W_TBL0_W6 . . . . . . . . . . 203

0x10 505C W_TBL0_W7 . . . . . . . . . . 204

0x10 5060 W_TBL0_W8 . . . . . . . . . . 204

0x10 5064 W_TBL0_W9 . . . . . . . . . . 204

0x10 5068 W_TBL0_W10 . . . . . . . . . 204

0x10 506C W_TBL0_W11 . . . . . . . . . 204

0x10 5070 W_TBL0_W12 . . . . . . . . . 204

0x10 5074 W_TBL0_W13 . . . . . . . . . 204

0x10 5078 W_TBL0_W14 . . . . . . . . . 205

0x10 507C W_TBL0_W15 . . . . . . . . . 205

0x10 5080 W_TBL1_W0 . . . . . . . . . . 205

0x10 5084 W_TBL1_W1 . . . . . . . . . . 205

0x10 5088 W_TBL1_W2 . . . . . . . . . . 205

0x10 508C W_TBL1_W3 . . . . . . . . . . 205

0x10 4FE0 INT_STATUS11

0x10 4FE4 INT_ENABLE11

0x10 4FE8 INT_CLEAR11

0x10 4FEC INT_SET11 (IRW+CTU[3:0]

0x10 4FF4 POWERDOWN . . . . . . . 198

0x10 4FFC MODULE_ID . . . . . . . . . 198

0x10 5090 W_TBL1_W4 . . . . . . . . . 205

0x10 5094 W_TBL1_W5 . . . . . . . . . 206

0x10 5098 W_TBL1_W6 . . . . . . . . . 206

0x10 509C W_TBL1_W7 . . . . . . . . . 206

0x10 50A0 W_TBL1_W8 . . . . . . . . . 206

0x10 50A4 W_TBL1_W9 . . . . . . . . . 206

0x10 50A8 W_TBL1_W10 . . . . . . . . 206

0x10 50AC W_TBL1_W11 . . . . . . . . 206

0x10 50B0 W_TBL1_W12 . . . . . . . . 207

0x10 50B4 W_TBL1_W13 . . . . . . . . 207

0x10 50B8 W_TBL1_W14 . . . . . . . . 207

0x10 50BC W_TBL1_W15 . . . . . . . . 207

0x10 50C0 Extra_Pic_Info . . . . . . . . 207

0x10 50C4 RL_STATS . . . . . . . . . . . 207

0x10 50C8 MP_IQ_SEL_0 . . . . . . . . 208

0x10 50CC MP_IQ_SEL_1 . . . . . . . . 208

0x10 5200 MC_PICINFO0 . . . . . . . . 208

0x10 5208 MC_PICINFO2 . . . . . . . . 208

0x10 520C MC_FREFY0 . . . . . . . . . 209

0x10 5210 MC_FREFY1 . . . . . . . . . 209

0x10 5214 MC_FREFUV0 . . . . . . . . 209

0x10 5218 MC_FREFUV1 . . . . . . . . 209

0x10 521C MC_BREFY0 . . . . . . . . . 209

0x10 5220 MC_BREFY1 . . . . . . . . . 209

0x10 5224 MC_BREFUV0 . . . . . . . . 209

0x10 5228 MC_BREFUV1 . . . . . . . . 209

0x10 522C MC_DESTY0 . . . . . . . . . 209

0x10 5230 MC_DESTY1 . . . . . . . . . 209

0x10 5234 MC_DESTUV0 . . . . . . . . 209

0x10 5238 MC_DESTUV1 . . . . . . . . 209

0x10 523C MC_COMMAND . . . . . . . 209

0x10 5240 MC_PFCOUNT . . . . . . . 210

0x10 5244 MC_STATUS . . . . . . . . . 210

0x10 5FF4 POWER_DOWN . . . . . . 210

0x10 5FFC MODULE_ID . . . . . . . . . 210

for TriMedia) . . . . . . . . . . 198

(IRW+CTU[3:0] for MIPS) 198

for MIPS) . . . . . . . . . . . . 198

Video Input Processor (VIP) 1 Registers (Rev 3.0.1)

0x10 6000 VIP Mode Control . . . . . . 210

0x10 6020 ANC Identifier Codes - Field 0

0x10 6024 ANC Identifier Codes - Field 1

0x10 6040 VIP Line Threshold . . . . . 212

0x10 6100 Video Input Format . . . . . 212

0x10 6104 Video Test Pattern Generator

0x10 6140 Video Acquisition Window

0x10 6144 Video Acquisition Window End

0x10 6160 Pre-Dither Control . . . . . . 214

0x10 6164 Post-Dither Control . . . . . 214

0x10 6180 Auxiliary Acquisition Window

0x10 6184 Auxiliary Acquisition Window

0x10 6200 Initial Zoom . . . . . . . . . . . 216

0x10 6204 Phase Control . . . . . . . . . 216

0x10 6208 Initial Zoom delta . . . . . . . 217

0x10 620C Zoom delta change . . . . . 217

0x10 6220 Color space matrix coefficients

0x10 6224 Color space matrix coefficients

Preliminary Rev. 02 — July 22 2004 x

212

Control . . . . . . . . . . . . . . . 213

Start . . . . . . . . . . . . . . . . . 214

214

Start . . . . . . . . . . . . . . . . . 215

End . . . . . . . . . . . . . . . . . 215

C00 - C02 . . . . . . . . . . . . 217

C10 - C12 . . . . . . . . . . . . 217

0x10 6228 Color space matrix coefficients

0x10 622C Color space matrix offset

0x10 6230 Color space matrix offset

0x10 6284 Color Key Components . 218 0x10 6300 Video Output Format . . . 218

0x10 6304 Target Window Size . . . . 219

0x10 6340 Target Base Address #1 219

0x10 6344 Target Line Pitch #1 . . . . 219

0x10 6348 Target Base Address #2 219

0x10 634C Target Line Pitch #2 . . . . 219

0x10 6350 Target Base Address #3 220 0x10 6354 Target Base Address #4 220 0x10 6358 Target Base Address #5 220 0x10 635C Target Base Address #6 220 0x10 6380 Auxiliary Capture Output

0x10 6390 Auxiliary Capture Base

0x10 6394 Auxiliary Capture Line Pitch .

0x10 6800—69FC Coefficient Table #1 Taps 0-5

0x10 6FE0 Interrupt Status . . . . . . . . 221

0x10 6FE4 Interrupt Enable . . . . . . . 222

C20 - C22 . . . . . . . . . . . . 217

coefficients D0 - D2 . . . . 217

coefficients E0 - E2 . . . . 218

Format . . . . . . . . . . . . . . 220

Address . . . . . . . . . . . . . 221

221

(Horizontal) . . . . . . . . . . . 221

Page 12

Philips Semiconductors

PNX8550

0x10 6FE8 Interrupt Clear . . . . . . . . .222

0x10 6FEC Interrupt Set . . . . . . . . . . . 222

Video Input Processor (VIP) 2 Registers (Rev 3.0.1)

0x10 7000 VIP Mode Control . . . . . . 223

0x10 7020 ANC Identifier Codes - Field 0

0x10 7024 ANC Identifier Codes - Field 1

0x10 7040 VIP Line Threshold . . . . . 225

0x10 7100 Video Input Format . . . . . 225

0x10 7104 Video Test Pattern Generator

0x10 7140 Video Acquisition Window

0x10 7144 Video Acquisition Window End

0x10 7160 Pre-Dither Control . . . . . . 227

0x10 7164 Post-Dither Control . . . . . 227

0x10 7180 Auxiliary Acquisition Window

0x10 7184 Auxiliary Acquisition Window

0x10 7200 Initial Zoom . . . . . . . . . . . 228

0x10 7204 Phase Control . . . . . . . . . 228

0x10 7208 Initial Zoom delta . . . . . . . 229

0x10 720C Zoom delta change . . . . . 229

0x10 7220 Color space matrix coefficients

0x10 7224 Color space matrix coefficients

0x10 7228 Color space matrix coefficients

224

225

Control . . . . . . . . . . . . . . . 226

Start . . . . . . . . . . . . . . . . . 226

227

Start . . . . . . . . . . . . . . . . . 228

End . . . . . . . . . . . . . . . . . 228

C00 - C02 . . . . . . . . . . . . 229

C10 - C12 . . . . . . . . . . . . 229

C20 - C22 . . . . . . . . . . . . 230

0x10 6FF4 Powerdown . . . . . . . . . . 223

0x10 6FFC Module ID . . . . . . . . . . . . 223

0x10 722C Color space matrix offset

0x10 7230 Color space matrix offset

0x10 7284 Color Key Components . 230 0x10 7300 Video Output Format . . . 231

0x10 7304 Target Window Size . . . . 231

0x10 7340 Target Base Address #1 232

0x10 7344 Target Line Pitch #1 . . . . 232

0x10 7348 Target Base Address #2 232

0x10 734C Target Line Pitch #2 . . . . 232

0x10 7350 Target Base Address #3 232 0x10 7354 Target Base Address #4 232 0x10 7358 Target Base Address #5 233 0x10 735C Target Base Address #6 233 0x10 7380 Auxiliary Capture Output

0x10 7390 Auxiliary Capture Base

0x10 7394 Auxiliary Capture Line Pitch .

0x10 7800—79FC Coefficient Table #1 Taps 0-5

0x10 7FE0 Interrupt Status . . . . . . . . 234

0x10 7FE4 Interrupt Enable . . . . . . . 234

0x10 7FE8 Interrupt Clear . . . . . . . . 235

0x10 7FEC Interrupt Set . . . . . . . . . . 235

0x10 7FF4 Powerdown . . . . . . . . . . 235

0x10 7FFC Module ID . . . . . . . . . . . . 235

coefficients D0 - D2 . . . . 230

coefficients E0 - E2 . . . . 230

Format . . . . . . . . . . . . . . 233

Address . . . . . . . . . . . . . 233

233

(Horizontal) . . . . . . . . . . . 234

VLD Registers (Rev 0.6.1)

0x10 8000 VLD_COMMAND . . . . . . . 236

0x10 8004 VLD_SR . . . . . . . . . . . . . . 236

0x10 8008 VLD_QS . . . . . . . . . . . . . 236

0x10 800C VLD_PI . . . . . . . . . . . . . . 236

0x10 8010 VLD_MC_STATUS . . . . . 237

0x10 8014 VLD_IE . . . . . . . . . . . . . . 237

0x10 8018 VLD_CTL . . . . . . . . . . . . . 237

0x10 801C VLD_INP_ADR . . . . . . . . 238

SPDO Registers (Rev 2.10)

0x10 9000 SPDO_STATUS . . . . . . . 239

0x10 9004 SPDO_CTL . . . . . . . . . . . 239

0x10 9008 Reserved . . . . . . . . . . . . . 240

0x10 900C SPDO_BASE1 . . . . . . . . . 240

0x10 9010 SPDO_BASE2 . . . . . . . . . 240

SPDIF IN 1 Registers (Rev 2.1.5)

0x10 A000 SPDI_CTL . . . . . . . . . . . . 241

0x10 A004 SPDI_BASE1 . . . . . . . . . . 242

0x10 A008 SPDI_BASE2 . . . . . . . . . . 242

0x10 A00C SPDI_SIZE . . . . . . . . . . . 242

0x10 A010 SPDI_BPTR . . . . . . . . . . . 242

0x10 A014 SPDI_SMPMASK . . . . . . 242

0x10 A018 SPDI_CBITS1 . . . . . . . . . 243

0x10 A01C SPDI_CBITS2 . . . . . . . . . 243

0x10 A020 SPDI_CBITS3 . . . . . . . . . 243

0x10 A024 SPDI_CBITS4 . . . . . . . . . 243

0x10 A028 SPDI_CBITS5 . . . . . . . . . 243

0x10 A02C SPDI_CBITS6 . . . . . . . . . 243

0x10 A030 SPDI_UBITS1 . . . . . . . . . 243

0x10 8020 VLD_INP_CNT . . . . . . . . 238

0x10 8024 VLD_MBH_ADR . . . . . . . 238

0x10 8028 VLD_MBH_CNT . . . . . . . 238

0x10 802C VLD_RL_ADR . . . . . . . . 238

0x10 8030 VLD_RL_CNT . . . . . . . . 238

0x10 8034 VLD_BIT_CNT . . . . . . . . 238

0x10 8FF4 POWER_DOWN . . . . . . 238

0x10 8FFC MODULE_ID . . . . . . . . . 238

0x10 9014 SPDO_SIZE . . . . . . . . . . 240

0x10 9018—9FF0 Reserved . . . . . . . . . . . . 240

0x10 9FF4 SPDO_PWR_DWN . . . . 240

0x10 9FFC SPDO_MODULE_ID . . . 240

0x10 A034 SPDI_UBITS2 . . . . . . . . 243

0x10 A038 SPDI_UBITS3 . . . . . . . . 244

0x10 A03C SPDI_UBITS4 . . . . . . . . 244

0x10 A040 SPDI_UBITS5 . . . . . . . . 244

0x10 A044 SPDI_UBITS6 . . . . . . . . 244

0x10 A048—AFDC Reserved . . . . . . . . . . . . 244

0x10 AFE0 SPDI_STATUS . . . . . . . . 244

0x10 AFE4 SPDI_INTEN . . . . . . . . . 245

0x10 AFE8 SPDI_INTCLR . . . . . . . . 246

0x10 AFEC SPDI_INTSET . . . . . . . . 246

0x10 AFF4 SPDI_PWR_DWN . . . . . 247

0x10 AFFC SPDI_MODULE_ID . . . . 247

DVDD Registers (Rev 0.4)

Memory Based Scaler (MBS) Registers (Rev 1.70)

0x10 C000 MBS Mode Control . . . . . 248 0x10 C040 Task FIFO . . . . . . . . . . . 249

Preliminary Rev. 02 — July 22 2004 xi

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Philips Semiconductors

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0x10 C044 Task Status 1 . . . . . . . . . . 250

0x10 C048 Task Status 2 . . . . . . . . . . 250

0x10 C100 Input Format . . . . . . . . . . 250

0x10 C104 Source Window Size . . . .250

0x10 C108 Variable Format Register . 251 0x10 C140 Source Base Address #1 . 251

0x10 C144 Source Line Pitch #1 . . . . 251

0x10 C148 Source Base Address #2 . 251

0x10 C14C Source Line Pitch #2 . . . . 251

0x10 C150 Source Base Address #3 . 252 0x10 C154 Source Base Address #4 . 252 0x10 C158 Source Base Address #5 . 252 0x10 C15C Source Base Address #6 . 252

0x10 C200 Initial Zoom . . . . . . . . . . . 252

0x10 C204 Phase Control . . . . . . . . . 253

0x10 C208 Initial Zoom delta . . . . . . . 253

0x10 C20C Zoom delta change . . . . . 254

0x10 C220 Color space matrix coefficients

0x10 C224 Color space matrix coefficients

0x10 C228 Color space matrix coefficients

0x10 C22C Color space matrix offset

0x10 C230 Color space matrix offset

0x10 C240 Initial Zoom . . . . . . . . . . . 255

0x10 C244 Phase Control . . . . . . . . . 255

0x10 C248 Initial Zoom delta . . . . . . . 256

0x10 C24C Zoom delta change . . . . . 256

0x10 C260 EDDI Control Register 1 . 256 0x10 C264 EDDI Control Register 2 . 256 0x10 C270 VTL Dynamic Control Register

0x10 C280 Color Key Control . . . . . . 257

0x10 C284 Color Key Components . .257

0x10 C300 Video Output Format . . . . 258

0x10 C304 Target Window Size . . . . 258

0x10 C340 Target Base Address #1 . 259

0x10 C344 Target Line Pitch #1 . . . . 259

0x10 C348 Target Base Address #2 . 259

0x10 C34C Target Line Pitch #2 . . . . 259

0x10 C350 Target Base Address #3 . 259 0x10 C354 Target Base Address #4 . 259 0x10 C358 Target Base Address #5 . 259 0x10 C35C Target Base Address #6 . 260

0x10 C400—C7FC Color Look Up Table . . . . 260

0x10 C800—C9FC Coefficient Table #1 Taps 0-5

0x10 CA00—CBFC Coefficient Table #2 Taps 0-5

0x10 CC00—CDFC Coefficient Table #3 Taps 0-5

0x10 CE0C Flaggen Control Registers 261

0x10 CE00 Format Control . . . . . . . . . 261

0x10 CE10 Histogram Control Register . .

C00 - C02 . . . . . . . . . . . . 254

C10 - C12 . . . . . . . . . . . . 254

C20 - C22 . . . . . . . . . . . . 254

coefficients D0 - D2 . . . . . 254

coefficients E0 - E2 . . . . . 254

256

(Horizontal) . . . . . . . . . . . 260

(Vertical - Luma) . . . . . . . 260

(Vertical - Chroma) . . . . . 260

262

0x10 CE18 Histogram Window Start 262 0x10 CE1C Histogram Window End . 262 0x10 CE8C Histogram Data Output 1 263 0x10 CE90 Histogram Data Output 2 263 0x10 CE94 Histogram Data Output 3 263 0x10 CE98 Histogram Data Output 4 263 0x10 CE9C Histogram Data Output 5 263 0x10 CEA0 Histogram Data Output 6 263 0x10 CEA4 Histogram Data Output 7 263 0x10 CEA8 Histogram Data Output 8 264 0x10 CEAC Histogram Data Output 9 264 0x10 CE20 Noise Estimator Control

0x10 CE24 Noise Estimator Control

0x10 CE28 Noise Estimator Window Start

0x10 CE2C Noise Estimator Window End

0x10 CEB0 Noise Estimator Data Output 1

0x10 CEB4 Noise Estimator Data Output 2

0x10 CE30 Black Bar Detector Control

0x10 CE38 Black Bar Detection Window

0x10 CE3C Black Bar Detection Window

0x10 CEB8 Black Bar Detection Data

0x10 CEBC Black Bar Detection Data

0x10 CE40 Black Level Detection Control

0x10 CE48 Black Level Detection Window

0x10 CE4C Black Level Detection Window

0x10 CEC0 Black Level Detection Control /

0x10 CE50 Bandwidth Detection Control

0x10 CE58 Bandwidth Detection Window

0x10 CE5C Bandwidth Detection Window

0x10 CEC4 Bandwidth Detection Output 1

0x10 CEC8 Bandwidth Detection Data

0x10 CFE0 Interrupt Status . . . . . . . . 267

0x10 CFE4 Interrupt Enable . . . . . . . 267

0x10 CFE8 Interrupt Clear . . . . . . . . 268

0x10 CFEC Interrupt Set . . . . . . . . . . 268

0x10 CFF4 Powerdown . . . . . . . . . . 268

0x10 CFFC Module ID . . . . . . . . . . . . 268

264

265

Start . . . . . . . . . . . . . . . . 265

End . . . . . . . . . . . . . . . . . 265

Output 1 . . . . . . . . . . . . . 265

output 2 . . . . . . . . . . . . . 266

266

Start . . . . . . . . . . . . . . . . 266

End . . . . . . . . . . . . . . . . . 266

Output . . . . . . . . . . . . . . 266

266

Start . . . . . . . . . . . . . . . . 266

End . . . . . . . . . . . . . . . . . 267

267

Output 2 . . . . . . . . . . . . . 267

Quality Temporal Noise Reduction (QTNR) Registers (Rev 0.9.1)

0x10 D000 QTNR Mode Control . . . . 269

0x10 D040 Task FIFO . . . . . . . . . . . . 269

0x10 D044 Task status . . . . . . . . . . . 269

0x10 D048 Task monitor . . . . . . . . . . 269

0x10 D100 Input Format . . . . . . . . . . 270

0x10 D104 Source Window Size . . . .270

0x10 D108 line_cntr_thresh . . . . . . . . 270

0x10 D140 Source Base Address #1 . 270

0x10 D144 Source Line Pitch #1 . . . . 271

0x10 D148 Source Base Address #2 . 271

0x10 D14C Source Line Pitch #2 . . . . 271

0x10 D154 Source Base Address #4 . 271 0x10 D158 Source Base Address #5 . 271

0x10 D260 TNR Control . . . . . . . . . . . 271

0x10 D264 LUT1 for Y . . . . . . . . . . . . 272

0x10 D268 LUT2 for Y . . . . . . . . . . . . 273

0x10 D26C LUT1 for UV . . . . . . . . . . . 273

0x10 D270 LUT2 for UV . . . . . . . . . . . 273

0x10 D300 Video Output Format . . . . 273

Preliminary Rev. 02 — July 22 2004 xii

0x10 D304 Target Window Size . . . . 273

0x10 D340 Target Base Address #1 274

0x10 D344 Target Line Pitch #1 . . . . 274

0x10 D348 Target Base Address #2 274

0x10 D34C Target Line Pitch #2 . . . . 274

0x10 DE00 Formatter Control . . . . . . 274

0x10 DE10 Histogram Control Register .

0x10 DE18 Histogram Window Start 276 0x10 DE1C Histogram Window End . 276 0x10 DE8C Histogram Data Output 1 . . . 276 0x10 DE90 Histogram Data Output 2 276 0x10 DE94 Histogram Data Output 3 276 0x10 DE98 Histogram Data Output 4 276 0x10 DE9C Histogram Data Output 5 277 0x10 DEA0 Histogram Data Output 6 277 0x10 DEA4 Histogram Data Output 7 277 0x10 DEA8 Histogram Data Output 8 277 0x10 DEAC Histogram Data Output 9 277

275

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Philips Semiconductors

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0x10 DE20 Noise Estimator Control

0x10 DE24 Noise Estimator Control

0x10 DE28 Noise Estimator Window Start

0x10 DE2C Noise Estimator Window End

0x10 DEB0 Noise Estimator Data Output 1

0x10 DEB4 Noise Estimator Data Output 2

0x10 DE30 Black Bar Detector Control

0x10 DE38 Black Bar Detection Window

0x10 DE3C Black Bar Detection Window

0x10 DEB8 Black Bar Detection Data

0x10 DEBC Black Bar Detection Data

0x10 DE40 Black Level Detection Control

278

Start . . . . . . . . . . . . . . . . . 279

End . . . . . . . . . . . . . . . . . 279

Output 1 . . . . . . . . . . . . . . 279

output 2 . . . . . . . . . . . . . . 279

279

0x10 DE48 Black Level Detection Window

0x10 DE4C Black Level Detection Window

0x10 DEC0 Black Level Detection Control /

0x10 DE50 Bandwidth Detection Control

0x10 DE58 Bandwidth Detection Window

0x10 DE5C Bandwidth Detection Window

0x10 DEC4 Bandwidth Detection Output 1

0x10 DEC8 Bandwidth Detection Data

0x10 DE0C Flaggen Control Registers 280

0x10 DFE0 Interrupt Status . . . . . . . . 281

0x10 DFE4 Interrupt Enable . . . . . . . 281

0x10 DFE8 Interrupt Clear . . . . . . . . 282

0x10 DFEC Interrupt Set . . . . . . . . . . 282

0x10 DFF4 Powerdown . . . . . . . . . . 282

0x10 DFFC Module ID . . . . . . . . . . . . 282

Start . . . . . . . . . . . . . . . . 279

End . . . . . . . . . . . . . . . . . 279

Output . . . . . . . . . . . . . . 280

280

Start . . . . . . . . . . . . . . . . 280

End . . . . . . . . . . . . . . . . . 280

280

Output 2 . . . . . . . . . . . . . 280

QVCP 5L Registers (Rev 1.43)

0x10 E000 Total . . . . . . . . . . . . . . . . . 282

0x10 E004 HBlank . . . . . . . . . . . . . . . 283

0x10 E008 VBlank . . . . . . . . . . . . . . . 283

0x10 E00C HSYNC . . . . . . . . . . . . . . 283

0x10 E010 VSYNC(Time Stamp at

0x10 E014 VInterrupt . . . . . . . . . . . . . 283

0x10 E018 Features . . . . . . . . . . . . . 284

0x10 E01C Default Background Color 284

0x10 E020 Control . . . . . . . . . . . . . . . 285

0x10 E024 Final_Layer_Assignment . 286

0x10 E028 INTLCTRL1 . . . . . . . . . . . 287

0x10 E02C INTLCTRL2 . . . . . . . . . . . 287

0x10 E030 VBI SRC Address . . . . . . 287

0x10 E034 VBI_CTRL . . . . . . . . . . . . 287

0x10 E038 VBI_Sent_Offset . . . . . . . 287

0x10 E03C OUT_CTRL . . . . . . . . . . . 287

0x10 E040 Pool_Resource_ID . . . . . 289

0x10 E044

0x10 E048 Resource_ID . . . . . . . . . . 290

0x10 E04C FU_Assignment . . . . . . . . 290

0x10 E050 Signature1 . . . . . . . . . . . . 290

0x10 E054 Signature2 . . . . . . . . . . . . 291

0x10 E058 Signature3 . . . . . . . . . . . . 291

0x10 E05C Output Pedestals1 . . . . . . 291

0x10 E060 Output Pedestals2 . . . . . . 291

0x10 E064 Output GNSH LUT Data Upper

0x10 E068 Output GNSH LUT Data

0x10 E06C Output GNSH LUT Data Lower

0x10 E070 Output ONSH Ctrl . . . . . . 292

0x10 E074 Output GAMMA Ctrl . . . . . 292

0x10 E078 Output CBSC Brightness &

0x10 E07C Output CBSC Matrix

0x10 E080 Output CBSC Matrix

0x10 E084 Output CBSC Matrix

0x10 E088 Output CBSC Matrix

0x10 E08C Output CBSC Ctrl . . . . . . 294

0x10 E090 Output CBSC LUT Data . 295 0x10 E094 Output CBSC Face Detector

0x10 E098 Output CBSC Face Detector

0x10 E09C Output CBSC Face Detector

Preliminary Rev. 02 — July 22 2004 xiii

System Level) . . . . . . . . . 283

Pool_Resource_Layer_Assign

ment . . . . . . . . . . . . . . . . . 289

291

Middle . . . . . . . . . . . . . . . 291

292

Contrast Ctrl . . . . . . . . . . 293

Coefficients 1 . . . . . . . . . . 293

Coefficients 2 . . . . . . . . . . 293

Coefficients 3 . . . . . . . . . . 293

Coefficients 4 . . . . . . . . . . 293

Ctrl . . . . . . . . . . . . . . . . . . 295

Bin 1 . . . . . . . . . . . . . . . . 295

0x10 E0A0 Output CBSC Face Detector

0x10 E0A4 Output CBSC Face Detector

0x10 E0A8 Output CBSC Face Detector

0x10 E0AC Output CBSC Face Detector

0x10 E0B0 Output CBSC Face Detector

0x10 E0B4 Output ABCL Ctrl . . . . . . 295

0x10 E0B8 Output ABCL Upper LUT Data

0x10 E0BC Output ABCL Middle LUT Data

0x10 E0C0 Output ABCL Lower LUT Data

0x10 E0C4 Output ABCL Upper Total

0x10 E0C8 Output ABCL Middle Total

0x10 E0CC Output ABCL Lower Total

0x10 E1F0 Shadow_Reload . . . . . . . 297

0x10 E1F8 Field_Info . . . . . . . . . . . . 297

0x10 E1FC XY_Position . . . . . . . . . . 297

0x10 E200 Layer Source Address A

0x10 E400 Layer Source Address A

0x10 E600 Layer Source Address A

0x10 E800 Layer Source Address A

0x10 EA00 Layer Source Address A

0x10 E204 Layer Pitch A (Packed/Semi

0x10 E404 Layer Pitch A (Packed/Semi

0x10 E604 Layer Pitch A (Packed/Semi

0x10 E804 Layer Pitch A (Packed/Semi

0x10 EA04 Layer Pitch A (Packed/Semi

0x10 E208 Layer Source Width (Packed/

Bin 2 . . . . . . . . . . . . . . . . 295

Bin 3 . . . . . . . . . . . . . . . . 295

Bin 4 . . . . . . . . . . . . . . . . 295

Bin 5 . . . . . . . . . . . . . . . . 295

Bin 6 . . . . . . . . . . . . . . . . 295

Bin 7 . . . . . . . . . . . . . . . . 295

296

Power Reading . . . . . . . . 296

Power Reading . . . . . . . . 297

(Packed/Semi Planar Y) —

Layer 1 . . . . . . . . . . . . . . 298

(Packed/Semi Planar Y) —

Layer 2 . . . . . . . . . . . . . . 298

(Packed/Semi Planar Y) —

Layer 3 . . . . . . . . . . . . . . 298

(Packed/Semi Planar Y) —

Layer 4 . . . . . . . . . . . . . . 298

(Packed/Semi Planar Y) —

Layer 5 . . . . . . . . . . . . . . 298

Planar Y) — Layer 1 . . . . 298

Planar Y) — Layer 2 . . . . 298

Planar Y) — Layer 3 . . . . 298

Planar Y) — Layer 4 . . . . 298

Planar Y) — Layer 5 . . . . 298

Page 15

Philips Semiconductors

PNX8550

Semi Planar- Y) — Layer 1 . .

0x10 E408 Layer Source Width (Packed/

0x10 E608 Layer Source Width (Packed/

0x10 E808 Layer Source Width (Packed/

0x10 EA08 Layer Source Width (Packed/

0x10 E20C Layer Source Address B

0x10 E40C Layer Source Address B

0x10 E60C Layer Source Address B

0x10 E80C Layer Source Address B

0x10 EA0C Layer Source Address B

0x10 E210 Layer Pitch B (Packed/Semi

0x10 E410 Layer Pitch B (Packed/Semi

0x10 E610 Layer Pitch B (Packed/Semi

0x10 E810 Layer Pitch B (Packed/Semi

0x10 EA10 Layer Pitch B (Packed/Semi

0x10 E214 Dummy Pixel Count — Layer 1

0x10 E414 Dummy Pixel Count — Layer 2

0x10 E614 Dummy Pixel Count — Layer 3

0x10 E814 Dummy Pixel Count — Layer 4

0x10 EA14 Dummy Pixel Count — Layer 5

0x10 E218 Layer Source Address A (Semi

0x10 E418 Layer Source Address A (Semi

0x10 E618 Layer Source Address A (Semi

0x10 E818 Layer Source Address A (Semi

0x10 EA18 Layer Source Address A (Semi

0x10 E21C Layer Source Address B (Semi

0x10 E41C Layer Source Address B (Semi

0x10 E61C Layer Source Address B (Semi

0x10 E81C Layer Source Address B (Semi

0x10 EA1C Layer Source Address B (Semi

0x10 E220 Line Increment (Packed) —

0x10 E420 Line Increment (Packed) —

0x10 E620 Line Increment (Packed) —

0x10 E820 Line Increment (Packed) —

0x10 EA20 Line Increment (Packed) —

0x10 E224 Line Increment (Semi Planar)

298

Semi Planar- Y) — Layer 2 . . 298

Semi Planar- Y) — Layer 3 . . 298

Semi Planar- Y) — Layer 4 . . 298

Semi Planar- Y) — Layer 5 . . 298

(Packed/Semi Planar-Y) —

Layer 1 . . . . . . . . . . . . . . . 299

(Packed/Semi Planar-Y) —

Layer 2 . . . . . . . . . . . . . . . 299

(Packed/Semi Planar-Y) —

Layer 3 . . . . . . . . . . . . . . . 299

(Packed/Semi Planar-Y) —

Layer 4 . . . . . . . . . . . . . . . 299

(Packed/Semi Planar-Y) —

Layer 5 . . . . . . . . . . . . . . . 299

Planar Y) — Layer 1 . . . . 299

Planar Y) — Layer 2 . . . . 299

Planar Y) — Layer 3 . . . . 299

Planar Y) — Layer 4 . . . . 299

Planar Y) — Layer 5 . . . . 299

299

Planar UV) — Layer 1 . . . 299

Planar UV) — Layer 2 . . . 299

Planar UV) — Layer 3 . . . 299

Planar UV) — Layer 4 . . . 299

Planar UV) — Layer 5 . . . 299

Planar UV) — Layer 1 . . . 300

Planar UV) — Layer 2 . . . 300

Planar UV) — Layer 3 . . . 300

Planar UV) — Layer 4 . . . 300

Planar UV) — Layer 5 . . . 300

Layer 1 . . . . . . . . . . . . . . . 300

Layer 2 . . . . . . . . . . . . . . . 300

Layer 3 . . . . . . . . . . . . . . . 300

Layer 4 . . . . . . . . . . . . . . . 300

Layer 5 . . . . . . . . . . . . . . . 300

0x10 E424 Line Increment (Semi Planar)

0x10 E624 Line Increment (Semi Planar)

0x10 E824 Line Increment (Semi Planar)

0x10 EA24 Line Increment (Semi Planar)

0x10 E228 Layer Pitch (Semi Planar/

0x10 E428 Layer Pitch (Semi Planar/

0x10 E628 Layer Pitch (Semi Planar/

0x10 E828 Layer Pitch (Semi Planar/

0x10 EA28 Layer Pitch (Semi Planar/

0x10 E22C Layer Source Width (Semi

0x10 E42C Layer Source Width (Semi

0x10 E62C Layer Source Width (Semi

0x10 E82C Layer Source Width (Semi

0x10 EA2C Layer Source Width (Semi

0x10 E230 Layer Start — Layer 1 . . 301 0x10 E430 Layer Start — Layer 2 . . 301 0x10 E630 Layer Start — Layer 3 . . 301 0x10 E830 Layer Start — Layer 4 . . 301 0x10 EA30 Layer Start — Layer 5 . . 301 0x10 E234 Layer Size — Layer 1 . . . 302 0x10 E434 Layer Size — Layer 2 . . . 302 0x10 E634 Layer Size — Layer 3 . . . 302 0x10 E834 Layer Size — Layer 4 . . . 302 0x10 EA34 Layer Size — Layer 5 . . . 302 0x10 E238 Pedestal and O/P format —

0x10 E438 Pedestal and O/P format —

0x10 E638 Pedestal and O/P format —

0x10 E838 Pedestal and O/P format —

0x10 EA38 Pedestal and O/P format —

0x10 E23C Layer Pixel Processing —

0x10 E43C Layer Pixel Processing —

0x10 E63C Layer Pixel Processing —

0x10 E83C Layer Pixel Processing —

0x10 EA3C Layer Pixel Processing —

0x10 E240 Layer Status/Control — Layer

0x10 E440 Layer Status/Control — Layer

0x10 E640 Layer Status/Control — Layer

0x10 E840 Layer Status/Control — Layer

0x10 EA40 Layer Status/Control — Layer

0x10 E244 LUT Programming — Layer 1

0x10 E444 LUT Programming — Layer 2

0x10 E644 LUT Programming — Layer 3

0x10 E844 LUT Programming — Layer 4

0x10 EA44 LUT Programming — Layer 5

0x10 E248 LUT Addressing — Layer 1 .

— Layer 1 . . . . . . . . . . . . 300

— Layer 2 . . . . . . . . . . . . 300

— Layer 3 . . . . . . . . . . . . 300

— Layer 4 . . . . . . . . . . . . 300

— Layer 5 . . . . . . . . . . . . 300

Planar) — Layer 1 . . . . . 300

Planar) — Layer 2 . . . . . 300

Planar) — Layer 3 . . . . . 300

Planar) — Layer 4 . . . . . 300

Planar) — Layer 5 . . . . . 300

Planar) — Layer 1 . . . . . 301

Planar) — Layer 2 . . . . . 301

Planar) — Layer 3 . . . . . 301

Planar) — Layer 4 . . . . . 301

Planar) — Layer 5 . . . . . 301

Layer 1 . . . . . . . . . . . . . . 302

Layer 2 . . . . . . . . . . . . . . 302

Layer 3 . . . . . . . . . . . . . . 302

Layer 4 . . . . . . . . . . . . . . 302

Layer 5 . . . . . . . . . . . . . . 302

Layer 1 . . . . . . . . . . . . . . 302

Layer 2 . . . . . . . . . . . . . . 302

Layer 3 . . . . . . . . . . . . . . 302

Layer 4 . . . . . . . . . . . . . . 302

Layer 5 . . . . . . . . . . . . . . 302

1 . . . . . . . . . . . . . . . . . . . 303

2 . . . . . . . . . . . . . . . . . . . 303

3 . . . . . . . . . . . . . . . . . . . 303

4 . . . . . . . . . . . . . . . . . . . 303

5 . . . . . . . . . . . . . . . . . . . 303

304

Preliminary Rev. 02 — July 22 2004 xiv

Page 16

Philips Semiconductors

PNX8550

0x10 E448 LUT Addressing — Layer 2 . .

0x10 E648 LUT Addressing — Layer 3 . .

0x10 E848 LUT Addressing — Layer 4 . .

0x10 EA48 LUT Addressing — Layer 5 . .

0x10 E24C Pixel Key AND Register —

0x10 E44C Pixel Key AND Register —

0x10 E64C Pixel Key AND Register —

0x10 E84C Pixel Key AND Register —

0x10 EA4C Pixel Key AND Register —

0x10 E250 Color Key1 AND Mask —

0x10 E450 Color Key1 AND Mask —

0x10 E650 Color Key1 AND Mask —

0x10 E850 Color Key1 AND Mask —

0x10 EA50 Color Key1 AND Mask —

0x10 E254 Color Key Up1 — Layer 1 305 0x10 E454 Color Key Up1 — Layer 2 305 0x10 E654 Color Key Up1 — Layer 3 305 0x10 E854 Color Key Up1 — Layer 4 305 0x10 EA54 Color Key Up1 — Layer 5 305 0x10 E258 Color Key Low1 — Layer 1 . .

0x10 E458 Color Key Low1 — Layer 2 . .

0x10 E658 Color Key Low1 — Layer 3 . .

0x10 E858 Color Key Low1 — Layer 4 . .

0x10 EA58 Color Key Low1 — Layer 5 . .

0x10 E25C Color Key Replace1 — Layer 1

0x10 E45C Color Key Replace1 — Layer 2

0x10 E65C Color Key Replace1 — Layer 3

0x10 E85C Color Key Replace1 — Layer 4

0x10 EA5C Color Key Replace1 — Layer 5

0x10 E260 Color Key2 AND Mask —

0x10 E460 Color Key2 AND Mask —

0x10 E660 Color Key2 AND Mask —

0x10 E860 Color Key2 AND Mask —

0x10 EA60 Color Key2 AND Mask —

0x10 E264 Color Key Up2 — Layer 1 305 0x10 E464 Color Key Up2 — Layer 2 305 0x10 E664 Color Key Up2 — Layer 3 305 0x10 E864 Color Key Up2 — Layer 4 305 0x10 EA64 Color Key Up2 — Layer 5 305 0x10 E268 Color Key Low2 — Layer 1 . .

0x10 E468 Color Key Low2 — Layer 2 . .

0x10 E668 Color Key Low2 — Layer 3 . .

0x10 E868 Color Key Low2 — Layer 4 . .

0x10 EA68 Color Key Low2 — Layer 5 . .

0x10 E26C Color Key Replace2 — Layer 1

304

Layer 1 . . . . . . . . . . . . . . . 304

Layer 2 . . . . . . . . . . . . . . . 304

Layer 3 . . . . . . . . . . . . . . . 304

Layer 4 . . . . . . . . . . . . . . . 304

Layer 5 . . . . . . . . . . . . . . . 304

Layer 1 . . . . . . . . . . . . . . . 304

Layer 2 . . . . . . . . . . . . . . . 304

Layer 3 . . . . . . . . . . . . . . . 304

Layer 4 . . . . . . . . . . . . . . . 304

Layer 5 . . . . . . . . . . . . . . . 304

305

Layer 1 . . . . . . . . . . . . . . . 305

Layer 2 . . . . . . . . . . . . . . . 305

Layer 3 . . . . . . . . . . . . . . . 305

Layer 4 . . . . . . . . . . . . . . . 305

Layer 5 . . . . . . . . . . . . . . . 305

306

0x10 E46C Color Key Replace2 — Layer 2

0x10 E66C Color Key Replace2 — Layer 3

0x10 E86C Color Key Replace2 — Layer 4

0x10 EA6C Color Key Replace2 — Layer 5

0x10 E270 Color Key3 AND Mask —

0x10 E470 Color Key3 AND Mask —

0x10 E670 Color Key3 AND Mask —

0x10 E870 Color Key3 AND Mask —

0x10 EA70 Color Key3 AND Mask —

0x10 E274 Color Key Up3 — Layer 1 306 0x10 E474 Color Key Up3 — Layer 2 306 0x10 E674 Color Key Up3 — Layer 3 306 0x10 E874 Color Key Up3 — Layer 4 306 0x10 EA74 Color Key Up3 — Layer 5 306 0x10 E278 Color Key Low3 — Layer 1 .

0x10 E478 Color Key Low3 — Layer 2 .

0x10 E678 Color Key Low3 — Layer 3 .

0x10 E878 Color Key Low3 — Layer 4 .

0x10 EA78 Color Key Low3 — Layer 5 .

0x10 E27C Color Key Replace3 — Layer 1

0x10 E47C Color Key Replace3 — Layer 2

0x10 E67C Color Key Replace3 — Layer 3

0x10 E87C Color Key Replace3 — Layer 4

0x10 EA7C Color Key Replace3 — Layer 5

0x10 E280 Color Key4 AND Mask —

0x10 E480 Color Key4 AND Mask —

0x10 E680 Color Key4 AND Mask —

0x10 E880 Color Key4 AND Mask —

0x10 EA80 Color Key4 AND Mask —

0x10 E284 Color Key Up4 — Layer 1 307 0x10 E484 Color Key Up4 — Layer 2 307 0x10 E684 Color Key Up4 — Layer 3 307 0x10 E884 Color Key Up4 — Layer 4 307 0x10 EA84 Color Key Up4 — Layer 5 307 0x10 E288 Color Key Low4 — Layer 1 .

0x10 E488 Color Key Low4 — Layer 2 .

0x10 E688 Color Key Low4 — Layer 3 .

0x10 E888 Color Key Low4 — Layer 4 .

0x10 EA88 Color Key Low4 — Layer 5 .

0x10 E28C Color Key Replace4 — Layer 1

0x10 E48C Color Key Replace4 — Layer 2

0x10 E68C Color Key Replace4 — Layer 3

0x10 E88C Color Key Replace4 — Layer 4

0x10 EA8C Color Key Replace4 — Layer 5

0x10 E290 Color Key Mask/ROP — Layer

306

Layer 1 . . . . . . . . . . . . . . 306

Layer 2 . . . . . . . . . . . . . . 306

Layer 3 . . . . . . . . . . . . . . 306

Layer 4 . . . . . . . . . . . . . . 306

Layer 5 . . . . . . . . . . . . . . 306

306

307

Layer 1 . . . . . . . . . . . . . . 307

Layer 2 . . . . . . . . . . . . . . 307

Layer 3 . . . . . . . . . . . . . . 307

Layer 4 . . . . . . . . . . . . . . 307

Layer 5 . . . . . . . . . . . . . . 307

307

Preliminary Rev. 02 — July 22 2004 xv

Page 17

Philips Semiconductors

PNX8550

0x10 E490 Color Key Mask/ROP — Layer

0x10 E690 Color Key Mask/ROP — Layer

0x10 E890 Color Key Mask/ROP — Layer

0x10 EA90 Color Key Mask/ROP — Layer

0x10 E294 Pixel Invert/Select ROP —

0x10 E494 Pixel Invert/Select ROP —

0x10 E694 Pixel Invert/Select ROP —

0x10 E894 Pixel Invert/Select ROP —

0x10 EA94 Pixel Invert/Select ROP —

0x10 E298 Alpha Blend/Key Pass —

0x10 E498 Alpha Blend/Key Pass —

0x10 E698 Alpha Blend/Key Pass —

0x10 E898 Alpha Blend/Key Pass —

0x10 EA98 Alpha Blend/Key Pass —

0x10 E29C Alpha Pass — Layer 1 . . . 309 0x10 E49C Alpha Pass — Layer 2 . . . 309 0x10 E69C Alpha Pass — Layer 3 . . . 309 0x10 E89C Alpha Pass — Layer 4 . . . 309 0x10 EA9C Alpha Pass — Layer 5 . . . 309 0x10 E2A0 Color Key ROPs 1/2 — Layer 1

0x10 E4A0 Color Key ROPs 1/2 — Layer 2

0x10 E6A0 Color Key ROPs 1/2 — Layer 3

0x10 E8A0 Color Key ROPs 1/2 — Layer 4

0x10 EAA0 Color Key ROPs 1/2 — Layer 5

0x10 E2A4 Color Key ROPs 3/4 — Layer 1

0x10 E4A4 Color Key ROPs 3/4 — Layer 2

0x10 E6A4 Color Key ROPs 3/4 — Layer 3

0x10 E8A4 Color Key ROPs 3/4 — Layer 4

0x10 EAA4 Color Key ROPs 3/4 — Layer 5

0x10 E2A8 INTR — Layer 1 . . . . . . . . 310

0x10 E4A8 INTR — Layer 2 . . . . . . . . 310

0x10 E6A8 INTR — Layer 3 . . . . . . . . 310

0x10 E8A8 INTR — Layer 4 . . . . . . . . 310

0x10 EAA8 INTR — Layer 5 . . . . . . . . 310

0x10 E2AC HSRU Phase — Layer 1 . 310 0x10 E4AC HSRU Phase — Layer 2 . 310 0x10 E6AC HSRU Phase — Layer 3 . 310 0x10 E8AC HSRU Phase — Layer 4 . 310 0x10 EAAC HSRU Phase — Layer 5 . 310 0x10 E2B0 HSRU Delta Phase — Layer 1

0x10 E4B0 HSRU Delta Phase — Layer 2

0x10 E6B0 HSRU Delta Phase — Layer 3

0x10 E8B0 HSRU Delta Phase — Layer 4

0x10 EAB0 HSRU Delta Phase — Layer 5

0x10 E2B4 Layer Size (Final) — Layer 1 .

0x10 E4B4 Layer Size (Final) — Layer 2 .

0x10 E6B4 Layer Size (Final) — Layer 3 .

1 . . . . . . . . . . . . . . . . . . . . 308

2 . . . . . . . . . . . . . . . . . . . . 308

3 . . . . . . . . . . . . . . . . . . . . 308

4 . . . . . . . . . . . . . . . . . . . . 308

5 . . . . . . . . . . . . . . . . . . . . 308

Layer 1 . . . . . . . . . . . . . . . 308

Layer 2 . . . . . . . . . . . . . . . 308

Layer 3 . . . . . . . . . . . . . . . 308

Layer 4 . . . . . . . . . . . . . . . 308

Layer 5 . . . . . . . . . . . . . . . 308

Layer 1 . . . . . . . . . . . . . . . 309

Layer 2 . . . . . . . . . . . . . . . 309

Layer 3 . . . . . . . . . . . . . . . 309

Layer 4 . . . . . . . . . . . . . . . 309

Layer 5 . . . . . . . . . . . . . . . 309

309

310

311

0x10 E8B4 Layer Size (Final) — Layer 4

0x10 EAB4 Layer Size (Final) — Layer 5

0x10 E2B8 Output and Alpha Manipulation

0x10 E4B8 Output and Alpha Manipulation

0x10 E6B8 Output and Alpha Manipulation

0x10 E8B8 Output and Alpha Manipulation

0x10 EAB8 Output and Alpha Manipulation

0x10 E2BC Formats — Layer 1 . . . . 313

0x10 E4BC Formats — Layer 2 . . . . 313

0x10 E6BC Formats — Layer 3 . . . . 313

0x10 E8BC Formats — Layer 4 . . . . 313

0x10 EABC Formats — Layer 5 . . . . 313

0x10 E2C0 Layer Background Color —

0x10 E4C0 Layer Background Color —

0x10 E6C0 Layer Background Color —

0x10 E8C0 Layer Background Color —

0x10 EAC0 Layer Background Color —

0x10 E2C4 Variable Format Register —

0x10 E4C4 Variable Format Register —

0x10 E6C4 Variable Format Register —

0x10 E8C4 Variable Format Register —

0x10 EAC4 Variable Format Register —

0x10 E2C8 Start Fetch — Layer 1 . . 314 0x10 E4C8 Start Fetch — Layer 2 . . 314 0x10 E6C8 Start Fetch — Layer 3 . . 314 0x10 E8C8 Start Fetch — Layer 4 . . 314 0x10 EAC8 Start Fetch — Layer 5 . . 314 0x10 E2CC Brightness & Contrast — Layer

0x10 E4CC Brightness & Contrast — Layer

0x10 E6CC Brightness & Contrast — Layer

0x10 E8CC Brightness & Contrast — Layer

0x10 EACC Brightness & Contrast — Layer

0x10 E2D0 Matrix Coefficients 1 — Layer

0x10 E4D0 Matrix Coefficients 1 — Layer

0x10 E6D0 Matrix Coefficients 1 — Layer

0x10 E8D0 Matrix Coefficients 1 — Layer

0x10 EAD0 Matrix Coefficients 1 — Layer

0x10 E2D4 Matrix Coefficients 2 — Layer

0x10 E4D4 Matrix Coefficients 2 — Layer

0x10 E6D4 Matrix Coefficients 2 — Layer

0x10 E8D4 Matrix Coefficients 2 — Layer

0x10 EAD4 Matrix Coefficients 2 — Layer

0x10 E2D8 Matrix Coefficients 3 — Layer

0x10 E4D8 Matrix Coefficients 3 — Layer

0x10 E6D8 Matrix Coefficients 3 — Layer

311

— Layer 1 . . . . . . . . . . . . 311

— Layer 2 . . . . . . . . . . . . 311

— Layer 3 . . . . . . . . . . . . 311

— Layer 4 . . . . . . . . . . . . 311

— Layer 5 . . . . . . . . . . . . 311

Layer 1 . . . . . . . . . . . . . . 313

Layer 2 . . . . . . . . . . . . . . 313

Layer 3 . . . . . . . . . . . . . . 313

Layer 4 . . . . . . . . . . . . . . 313

Layer 5 . . . . . . . . . . . . . . 313

Layer 1 . . . . . . . . . . . . . . 314

Layer 2 . . . . . . . . . . . . . . 314

Layer 3 . . . . . . . . . . . . . . 314

Layer 4 . . . . . . . . . . . . . . 314

Layer 5 . . . . . . . . . . . . . . 314

1 . . . . . . . . . . . . . . . . . . . 315

2 . . . . . . . . . . . . . . . . . . . 315

3 . . . . . . . . . . . . . . . . . . . 315

4 . . . . . . . . . . . . . . . . . . . 315

5 . . . . . . . . . . . . . . . . . . . 315

1 . . . . . . . . . . . . . . . . . . . 316

2 . . . . . . . . . . . . . . . . . . . 316

3 . . . . . . . . . . . . . . . . . . . 316

4 . . . . . . . . . . . . . . . . . . . 316

5 . . . . . . . . . . . . . . . . . . . 316

1 . . . . . . . . . . . . . . . . . . . 316

2 . . . . . . . . . . . . . . . . . . . 316

3 . . . . . . . . . . . . . . . . . . . 316

4 . . . . . . . . . . . . . . . . . . . 316

5 . . . . . . . . . . . . . . . . . . . 316

1 . . . . . . . . . . . . . . . . . . . 316

2 . . . . . . . . . . . . . . . . . . . 316

3 . . . . . . . . . . . . . . . . . . . 316

Preliminary Rev. 02 — July 22 2004 xvi

Page 18

Philips Semiconductors

PNX8550

0x10 E8D8 Matrix Coefficients 3 — Layer

0x10 EAD8 Matrix Coefficients 3 — Layer

0x10 E2DC Matrix Coefficients 4 — Layer

0x10 E4DC Matrix Coefficients 4 — Layer

0x10 E6DC Matrix Coefficients 4 — Layer

0x10 E8DC Matrix Coefficients 4 — Layer

0x10 EADC Matrix Coefficients 4 — Layer

0x10 E2E0 Matrix Coefficients 5 — Layer

0x10 E4E0 Matrix Coefficients 5 — Layer

0x10 E6E0 Matrix Coefficients 5 — Layer

0x10 E8E0 Matrix Coefficients 5 — Layer

0x10 EAE0 Matrix Coefficients 5 — Layer

0x10 E2E8 LSHR_PAR_0 — Layer 1 317 0x10 E4E8 LSHR_PAR_0 — Layer 2 317 0x10 E6E8 LSHR_PAR_0 — Layer 3 317 0x10 E8E8 LSHR_PAR_0 — Layer 4 317 0x10 EAE8 LSHR_PAR_0 — Layer 5 317 0x10 E2EC LSHR_PAR_1 — Layer 1 318 0x10 E4EC LSHR_PAR_1 — Layer 2 318 0x10 E6EC LSHR_PAR_1 — Layer 3 318 0x10 E8EC LSHR_PAR_1 — Layer 4 318 0x10 EAEC LSHR_PAR_1 — Layer 5 318 0x10 E2F0 LSHR_PAR_2 — Layer 1 318 0x10 E4F0 LSHR_PAR_2 — Layer 2 318 0x10 E6F0 LSHR_PAR_2 — Layer 3 318 0x10 E8F0 LSHR_PAR_2 — Layer 4 318 0x10 EAF0 LSHR_PAR_2 — Layer 5 318 0x10 E2F4 LSHR_PAR_3 — Layer 1 319 0x10 E4F4 LSHR_PAR_3 — Layer 2 319 0x10 E6F4 LSHR_PAR_3 — Layer 3 319 0x10 E8F4 LSHR_PAR_3 — Layer 4 319 0x10 EAF4 LSHR_PAR_3 — Layer 5 319 0x10 E2F8 LSHR_E_max — Layer 1 319 0x10 E4F8 LSHR_E_max — Layer 2 319 0x10 E6F8 LSHR_E_max — Layer 3 319 0x10 E8F8 LSHR_E_max — Layer 4 319 0x10 EAF8 LSHR_E_max — Layer 5 319 0x10 E2FC LSHR_E_Sum — Layer 1 320 0x10 E4FC LSHR_E_Sum — Layer 2 320 0x10 E6FC LSHR_E_Sum — Layer 3 320 0x10 E8FC LSHR_E_Sum — Layer 4 320 0x10 EAFC LSHR_E_Sum — Layer 5 320 0x10 E300 LSHR Measurement Window

0x10 E500 LSHR Measurement Window

0x10 E700 LSHR Measurement Window

0x10 E900 LSHR Measurement Window

0x10 EB00 LSHR Measurement Window

0x10 E304 LSHR Measurement Window

0x10 E504 LSHR Measurement Window

0x10 E704 LSHR Measurement Window

0x10 E904 LSHR Measurement Window

0x10 EB04 LSHR Measurement Window

0x10 E320 Layer Solid Color — Layer 1 .

0x10 E520 Layer Solid Color — Layer 2 .

0x10 E720 Layer Solid Color — Layer 3 .

4 . . . . . . . . . . . . . . . . . . . . 316

5 . . . . . . . . . . . . . . . . . . . . 316

1 . . . . . . . . . . . . . . . . . . . . 317

2 . . . . . . . . . . . . . . . . . . . . 317

3 . . . . . . . . . . . . . . . . . . . . 317

4 . . . . . . . . . . . . . . . . . . . . 317

5 . . . . . . . . . . . . . . . . . . . . 317

1 . . . . . . . . . . . . . . . . . . . . 317

2 . . . . . . . . . . . . . . . . . . . . 317

3 . . . . . . . . . . . . . . . . . . . . 317

4 . . . . . . . . . . . . . . . . . . . . 317

5 . . . . . . . . . . . . . . . . . . . . 317

Start — Layer 1 . . . . . . . . 320

Start — Layer 2 . . . . . . . . 320

Start — Layer 3 . . . . . . . . 320

Start — Layer 4 . . . . . . . . 320

Start — Layer 5 . . . . . . . . 320

End — Layer 1 . . . . . . . . . 320

End — Layer 2 . . . . . . . . . 320

End — Layer 3 . . . . . . . . . 320

End — Layer 4 . . . . . . . . . 320

End — Layer 5 . . . . . . . . . 320

320

0x10 E920 Layer Solid Color — Layer 4

0x10 EB20 Layer Solid Color — Layer 5

0x10 E324 Layer LUT-HIST Bins 00 to 03

0x10 E524 Layer LUT-HIST Bins 00 to 03

0x10 E724 Layer LUT-HIST Bins 00 to 03

0x10 E924 Layer LUT-HIST Bins 00 to 03

0x10 EB24 Layer LUT-HIST Bins 00 to 03

0x10 E328 Layer LUT-HIST Bins 04 to 07

0x10 E528 Layer LUT-HIST Bins 04 to 07

0x10 E728 Layer LUT-HIST Bins 04 to 07

0x10 E928 Layer LUT-HIST Bins 04 to 07

0x10 EB28 Layer LUT-HIST Bins 04 to 07

0x10 E32C Layer LUT-HIST Bins 08 to

0x10 E52C Layer LUT-HIST Bins 08 to

0x10 E72C Layer LUT-HIST Bins 08 to

0x10 E92C Layer LUT-HIST Bins 08 to

0x10 EB2C Layer LUT-HIST Bins 08 to

0x10 E330 Layer LUT-HIST Bins 12 to 15

0x10 E530 Layer LUT-HIST Bins 12 to 15

0x10 E730 Layer LUT-HIST Bins 12 to 15

0x10 E930 Layer LUT-HIST Bins 12 to 15

0x10 EB30 Layer LUT-HIST Bins 12 to 15

0x10 E334 Layer LUT-HIST Bins 16 to 19

0x10 E534 Layer LUT-HIST Bins 16 to 19

0x10 E734 Layer LUT-HIST Bins 16 to 19

0x10 E934 Layer LUT-HIST Bins 16 to 19

0x10 EB34 Layer LUT-HIST Bins 16 to 19

0x10 E338 Layer LUT-HIST Bins 20 to 23

0x10 E538 Layer LUT-HIST Bins 20 to 23

0x10 E738 Layer LUT-HIST Bins 20 to 23

0x10 E938 Layer LUT-HIST Bins 20 to 23

0x10 EB38 Layer LUT-HIST Bins 20 to 23

0x10 E33C Layer LUT-HIST Bins 24 to

0x10 E53C Layer LUT-HIST Bins 24 to

0x10 E73C Layer LUT-HIST Bins 24 to

0x10 E93C Layer LUT-HIST Bins 24 to

0x10 EB3C Layer LUT-HIST Bins 24 to

0x10 E340 Layer LUT-HIST Bins 28 to 31

0x10 E540 Layer LUT-HIST Bins 28 to 31

0x10 E740 Layer LUT-HIST Bins 28 to 31

320

— Layer 1 . . . . . . . . . . . . 321

— Layer 2 . . . . . . . . . . . . 321

— Layer 3 . . . . . . . . . . . . 321

— Layer 4 . . . . . . . . . . . . 321

— Layer 5 . . . . . . . . . . . . 321

— Layer 1 . . . . . . . . . . . . 321

— Layer 2 . . . . . . . . . . . . 321

— Layer 3 . . . . . . . . . . . . 321

— Layer 4 . . . . . . . . . . . . 321

— Layer 5 . . . . . . . . . . . . 321

011 — Layer 1 . . . . . . . . 321

011 — Layer 2 . . . . . . . . 321

011 — Layer 3 . . . . . . . . 321

011 — Layer 4 . . . . . . . . 321

011 — Layer 5 . . . . . . . . 321

— Layer 1 . . . . . . . . . . . . 321

— Layer 2 . . . . . . . . . . . . 321

— Layer 3 . . . . . . . . . . . . 321

— Layer 4 . . . . . . . . . . . . 321

— Layer 5 . . . . . . . . . . . . 321

— Layer 1 . . . . . . . . . . . . 322

— Layer 2 . . . . . . . . . . . . 322

— Layer 3 . . . . . . . . . . . . 322

— Layer 4 . . . . . . . . . . . . 322

— Layer 5 . . . . . . . . . . . . 322

— Layer 1 . . . . . . . . . . . . 322

— Layer 2 . . . . . . . . . . . . 322

— Layer 3 . . . . . . . . . . . . 322

— Layer 4 . . . . . . . . . . . . 322

— Layer 5 . . . . . . . . . . . . 322

027 — Layer 1 . . . . . . . . 322

027 — Layer 2 . . . . . . . . 322

027 — Layer 3 . . . . . . . . 322

027 — Layer 4 . . . . . . . . 322

027 — Layer 5 . . . . . . . . 322

— Layer 1 . . . . . . . . . . . . 322

— Layer 2 . . . . . . . . . . . . 322

— Layer 3 . . . . . . . . . . . . 322

Preliminary Rev. 02 — July 22 2004 xvii

Page 19

Philips Semiconductors

PNX8550

0x10 E940 Layer LUT-HIST Bins 28 to 31

0x10 EB40 Layer LUT-HIST Bins 28 to 31

0x10 E344 Layer Histogram Control —

0x10 E544 Layer Histogram Control —

0x10 E744 Layer Histogram Control —

0x10 E944 Layer Histogram Control —

0x10 EB44 Layer Histogram Control —

0x10 E348 Layer CFTR Blue — Layer 1 .

0x10 E548 Layer CFTR Blue — Layer 2 .

0x10 E748 Layer CFTR Blue — Layer 3 .

0x10 E948 Layer CFTR Blue — Layer 4 .

0x10 EB48 Layer CFTR Blue — Layer 5 .

0x10 E34C Layer CFTR Green — Layer 1

— Layer 4 . . . . . . . . . . . . 322

— Layer 5 . . . . . . . . . . . . 322

Layer 1 . . . . . . . . . . . . . . . 323

Layer 2 . . . . . . . . . . . . . . . 323

Layer 3 . . . . . . . . . . . . . . . 323

Layer 4 . . . . . . . . . . . . . . . 323

Layer 5 . . . . . . . . . . . . . . . 323

323

0x10 E54C Layer CFTR Green — Layer 2

0x10 E74C Layer CFTR Green — Layer 3

0x10 E94C Layer CFTR Green — Layer 4

0x10 EB4C Layer CFTR Green — Layer 5

0x10 E350 Layer DCTI Control — Layer 1

0x10 E550 Layer DCTI Control — Layer 2

0x10 E750 Layer DCTI Control — Layer 3

0x10 E950 Layer DCTI Control — Layer 4

0x10 EB50 Layer DCTI Control — Layer 5

0x10 EFE0 Interrupt Status QVCP . . 325 0x10 EFE4 Interrupt Enable QVCP . 326 0x10 EFE8 Interrupt Clear QVCP . . . 326

0x10 EFEC Interrupt Set QVCP . . . . 326

0x10 EFF4 Powerdown . . . . . . . . . . 326

0x10 EFFC Module ID . . . . . . . . . . . . 326

324

QVCP 2L Registers (Rev 1.43)

0x10 F000 Total . . . . . . . . . . . . . . . . . 327

0x10 F004 HBlank . . . . . . . . . . . . . . . 327

0x10 F008 VBlank . . . . . . . . . . . . . . . 327

0x10 F00C HSYNC . . . . . . . . . . . . . . 327

0x10 F010 VSYNC(Time Stamp at

0x10 F014 VInterrupt . . . . . . . . . . . . . 328

0x10 F018 Features . . . . . . . . . . . . . 328

0x10 F01C Default Background Color 329

0x10 F020 Control . . . . . . . . . . . . . . . 329

0x10 F024 Final_Layer_Assignment . 330

0x10 F028 INTLCTRL1 . . . . . . . . . . . 331

0x10 F02C INTLCTRL2 . . . . . . . . . . . 331

0x10 F030 VBI SRC Address . . . . . . 331

0x10 F034 VBI_CTRL . . . . . . . . . . . . 331

0x10 F038 VBI_Sent_Offset . . . . . . . 332

0x10 F03C OUT_CTRL . . . . . . . . . . . 332

0x10 F040 Pool_Resource_ID . . . . . 333

0x10 F044

0x10 F048 Resource_ID . . . . . . . . . . 334

0x10 F04C FU_Assignment . . . . . . . . 334

0x10 F050 Signature1 . . . . . . . . . . . . 335

0x10 F054 Signature2 . . . . . . . . . . . . 335

0x10 F058 Signature3 . . . . . . . . . . . . 335

0x10 F05C Output Pedestals1 . . . . . . 335

0x10 F060 Output Pedestals2 . . . . . . 336

0x10 F064 Output GNSH LUT Data Upper

0x10 F068 Output GNSH LUT Data

0x10 F06C Output GNSH LUT Data Lower

0x10 F070 Output ONSH Ctrl . . . . . . 336

0x10 F074 Output GAMMA Ctrl . . . . . 337

0x10 F078 Output CBSC Brightness &

0x10 F07C Output CBSC Matrix

0x10 F080 Output CBSC Matrix

0x10 F084 Output CBSC Matrix

0x10 F088 Output CBSC Matrix

0x10 F08C Output CBSC Ctrl . . . . . . 338

0x10 F090 Output CBSC LUT Data . 339 0x10 F094 Output CBSC Face Detector

0x10 F098 Output CBSC Face Detector

Preliminary Rev. 02 — July 22 2004 xviii

System Level) . . . . . . . . . 327

Pool_Resource_Layer_Assign

ment . . . . . . . . . . . . . . . . . 334

336

Middle . . . . . . . . . . . . . . . 336

336

Contrast Ctrl . . . . . . . . . . 337

Coefficients 1 . . . . . . . . . . 337

Coefficients 2 . . . . . . . . . . 337

Coefficients 3 . . . . . . . . . . 338

Coefficients 4 . . . . . . . . . . 338

Ctrl . . . . . . . . . . . . . . . . . . 339

Bin 1 . . . . . . . . . . . . . . . . 339

0x10 F09C Output CBSC Face Detector

0x10 F0A0 Output CBSC Face Detector

0x10 F0A4 Output CBSC Face Detector

0x10 F0A8 Output CBSC Face Detector

0x10 F0AC Output CBSC Face Detector

0x10 F0B0 Output CBSC Face Detector

0x10 F0B4 Output ABCL Ctrl . . . . . . 340

0x10 F0B8 Output ABCL Upper LUT Data

0x10 F0BC Output ABCL Middle LUT Data

0x10 F0C0 Output ABCL Lower LUT Data

0x10 F0C4 Output ABCL Upper Total

0x10 F0C8 Output ABCL Middle Total

0x10 F0CC Output ABCL Lower Total

0x10 F1F0 Shadow_Reload . . . . . . . 341

0x10 F1F8 Field_Info . . . . . . . . . . . . 341

0x10 F1FC XY_Position . . . . . . . . . . 341

0x10 F200 Layer Source Address A

0x10 F400 Layer Source Address A

0x10 F600 Layer Source Address A

0x10 F800 Layer Source Address A

0x10 FA00 Layer Source Address A

0x10 F204 Layer Pitch A (Packed/Semi

0x10 F404 Layer Pitch A (Packed/Semi

0x10 F604 Layer Pitch A (Packed/Semi

0x10 F804 Layer Pitch A (Packed/Semi

0x10 FA04 Layer Pitch A (Packed/Semi

Bin 2 . . . . . . . . . . . . . . . . 339

Bin 3 . . . . . . . . . . . . . . . . 339

Bin 4 . . . . . . . . . . . . . . . . 339

Bin 5 . . . . . . . . . . . . . . . . 340

Bin 6 . . . . . . . . . . . . . . . . 340

Bin 7 . . . . . . . . . . . . . . . . 340

340

341

Power Reading . . . . . . . . 341

(Packed/Semi Planar Y) —

Layer 1 . . . . . . . . . . . . . . 342

(Packed/Semi Planar Y) —

Layer 2 . . . . . . . . . . . . . . 342

(Packed/Semi Planar Y) —

Layer 3 . . . . . . . . . . . . . . 342

(Packed/Semi Planar Y) —

Layer 4 . . . . . . . . . . . . . . 342

(Packed/Semi Planar Y) —

Layer 5 . . . . . . . . . . . . . . 342

Planar Y) — Layer 1 . . . . 342

Planar Y) — Layer 2 . . . . 342

Planar Y) — Layer 3 . . . . 342

Planar Y) — Layer 4 . . . . 342

Page 20

Philips Semiconductors

PNX8550

0x10 F208 Layer Source Width (Packed/

0x10 F408 Layer Source Width (Packed/

0x10 F608 Layer Source Width (Packed/

0x10 F808 Layer Source Width (Packed/

0x10 FA08 Layer Source Width (Packed/

0x10 F20C Layer Source Address B

0x10 F40C Layer Source Address B

0x10 F60C Layer Source Address B

0x10 F80C Layer Source Address B

0x10 FA0C Layer Source Address B

0x10 F210 Layer Pitch B (Packed/Semi

0x10 F410 Layer Pitch B (Packed/Semi

0x10 F610 Layer Pitch B (Packed/Semi

0x10 F810 Layer Pitch B (Packed/Semi

0x10 FA10 Layer Pitch B (Packed/Semi

0x10 F214 Dummy Pixel Count — Layer 1

0x10 F414 Dummy Pixel Count — Layer 2

0x10 F614 Dummy Pixel Count — Layer 3

0x10 F814 Dummy Pixel Count — Layer 4

0x10 FA14 Dummy Pixel Count — Layer 5

0x10 F218 Layer Source Address A (Semi

0x10 F418 Layer Source Address A (Semi

0x10 F618 Layer Source Address A (Semi

0x10 F818 Layer Source Address A (Semi

0x10 FA18 Layer Source Address A (Semi

0x10 F21C Layer Source Address B (Semi

0x10 F41C Layer Source Address B (Semi

0x10 F61C Layer Source Address B (Semi

0x10 F81C Layer Source Address B (Semi

0x10 FA1C Layer Source Address B (Semi

0x10 F220 Line Increment (Packed) —

0x10 F420 Line Increment (Packed) —

0x10 F620 Line Increment (Packed) —

0x10 F820 Line Increment (Packed) —

0x10 FA20 Line Increment (Packed) —

Planar Y) — Layer 5 . . . . 342

Semi Planar- Y) — Layer 1 . . 342

Semi Planar- Y) — Layer 2 . . 342

Semi Planar- Y) — Layer 3 . . 342

Semi Planar- Y) — Layer 4 . . 342

Semi Planar- Y) — Layer 5 . . 342

(Packed/Semi Planar-Y) —

Layer 1 . . . . . . . . . . . . . . . 343

(Packed/Semi Planar-Y) —

Layer 2 . . . . . . . . . . . . . . . 343

(Packed/Semi Planar-Y) —

Layer 3 . . . . . . . . . . . . . . . 343

(Packed/Semi Planar-Y) —

Layer 4 . . . . . . . . . . . . . . . 343

(Packed/Semi Planar-Y) —

Layer 5 . . . . . . . . . . . . . . . 343

Planar Y) — Layer 1 . . . . 343

Planar Y) — Layer 2 . . . . 343

Planar Y) — Layer 3 . . . . 343

Planar Y) — Layer 4 . . . . 343

Planar Y) — Layer 5 . . . . 343

343

Planar UV) — Layer 1 . . . 343

Planar UV) — Layer 2 . . . 343

Planar UV) — Layer 3 . . . 343

Planar UV) — Layer 4 . . . 343

Planar UV) — Layer 5 . . . 343

Planar UV) — Layer 1 . . . 344

Planar UV) — Layer 2 . . . 344

Planar UV) — Layer 3 . . . 344

Planar UV) — Layer 4 . . . 344

Planar UV) — Layer 5 . . . 344

Layer 1 . . . . . . . . . . . . . . . 344

Layer 2 . . . . . . . . . . . . . . . 344

Layer 3 . . . . . . . . . . . . . . . 344

Layer 4 . . . . . . . . . . . . . . . 344

0x10 F224 Line Increment (Semi Planar)

0x10 F424 Line Increment (Semi Planar)

0x10 F624 Line Increment (Semi Planar)

0x10 F824 Line Increment (Semi Planar)

0x10 FA24 Line Increment (Semi Planar)

0x10 F228 Layer Pitch (Semi Planar/

0x10 F428 Layer Pitch (Semi Planar/

0x10 F628 Layer Pitch (Semi Planar/

0x10 F828 Layer Pitch (Semi Planar/

0x10 FA28 Layer Pitch (Semi Planar/

0x10 F22C Layer Source Width (Semi

0x10 F42C Layer Source Width (Semi

0x10 F62C Layer Source Width (Semi

0x10 F82C Layer Source Width (Semi

0x10 FA2C Layer Source Width (Semi

0x10 F230 Layer Start — Layer 1 . . 345 0x10 F430 Layer Start — Layer 2 . . 345 0x10 F630 Layer Start — Layer 3 . . 345 0x10 F830 Layer Start — Layer 4 . . 345 0x10 FA30 Layer Start — Layer 5 . . 345 0x10 F234 Layer Size — Layer 1 . . . 346 0x10 F434 Layer Size — Layer 2 . . . 346 0x10 F634 Layer Size — Layer 3 . . . 346 0x10 F834 Layer Size — Layer 4 . . . 346 0x10 FA34 Layer Size — Layer 5 . . . 346 0x10 F238 Pedestal and O/P format —

0x10 F438 Pedestal and O/P format —

0x10 F638 Pedestal and O/P format —

0x10 F838 Pedestal and O/P format —

0x10 FA38 Pedestal and O/P format —

0x10 F23C Layer Pixel Processing —

0x10 F43C Layer Pixel Processing —

0x10 F63C Layer Pixel Processing —

0x10 F83C Layer Pixel Processing —

0x10 FA3C Layer Pixel Processing —

0x10 F240 Layer Status/Control — Layer

0x10 F440 Layer Status/Control — Layer

0x10 F640 Layer Status/Control — Layer

0x10 F840 Layer Status/Control — Layer

0x10 FA40 Layer Status/Control — Layer

0x10 F244 LUT Programming — Layer 1

0x10 F444 LUT Programming — Layer 2

0x10 F644 LUT Programming — Layer 3

0x10 F844 LUT Programming — Layer 4

0x10 FA44 LUT Programming — Layer 5

Layer 5 . . . . . . . . . . . . . . 344

— Layer 1 . . . . . . . . . . . . 344

— Layer 2 . . . . . . . . . . . . 344

— Layer 3 . . . . . . . . . . . . 344

— Layer 4 . . . . . . . . . . . . 344

— Layer 5 . . . . . . . . . . . . 344

Planar) — Layer 1 . . . . . 344

Planar) — Layer 2 . . . . . 344

Planar) — Layer 3 . . . . . 344

Planar) — Layer 4 . . . . . 344

Planar) — Layer 5 . . . . . 344

Planar) — Layer 1 . . . . . 345

Planar) — Layer 2 . . . . . 345

Planar) — Layer 3 . . . . . 345

Planar) — Layer 4 . . . . . 345

Planar) — Layer 5 . . . . . 345

Layer 1 . . . . . . . . . . . . . . 346

Layer 2 . . . . . . . . . . . . . . 346

Layer 3 . . . . . . . . . . . . . . 346

Layer 4 . . . . . . . . . . . . . . 346

Layer 5 . . . . . . . . . . . . . . 346

Layer 1 . . . . . . . . . . . . . . 346

Layer 2 . . . . . . . . . . . . . . 346

Layer 3 . . . . . . . . . . . . . . 346

Layer 4 . . . . . . . . . . . . . . 346

Layer 5 . . . . . . . . . . . . . . 346

1 . . . . . . . . . . . . . . . . . . . 347

2 . . . . . . . . . . . . . . . . . . . 347

3 . . . . . . . . . . . . . . . . . . . 347

4 . . . . . . . . . . . . . . . . . . . 347

5 . . . . . . . . . . . . . . . . . . . 347

348

Preliminary Rev. 02 — July 22 2004 xix

Page 21

Philips Semiconductors

PNX8550

0x10 F248 LUT Addressing — Layer 1 . .

0x10 F448 LUT Addressing — Layer 2 . .

0x10 F648 LUT Addressing — Layer 3 . .

0x10 F848 LUT Addressing — Layer 4 . .

0x10 FA48 LUT Addressing — Layer 5 . .

0x10 F24C Pixel Key AND Register —

0x10 F44C Pixel Key AND Register —

0x10 F64C Pixel Key AND Register —

0x10 F84C Pixel Key AND Register —

0x10 FA4C Pixel Key AND Register —

0x10 F250 Color Key1 AND Mask —

0x10 F450 Color Key1 AND Mask —

0x10 F650 Color Key1 AND Mask —

0x10 F850 Color Key1 AND Mask —

0x10 FA50 Color Key1 AND Mask —

0x10 F254 Color Key Up1 — Layer 1 349 0x10 F454 Color Key Up1 — Layer 2 349 0x10 F654 Color Key Up1 — Layer 3 349 0x10 F854 Color Key Up1 — Layer 4 349 0x10 FA54 Color Key Up1 — Layer 5 349 0x10 F258 Color Key Low1 — Layer 1 . .

0x10 F458 Color Key Low1 — Layer 2 . .

0x10 F658 Color Key Low1 — Layer 3 . .

0x10 F858 Color Key Low1 — Layer 4 . .

0x10 FA58 Color Key Low1 — Layer 5 . .

0x10 F25C Color Key Replace1 — Layer 1

0x10 F45C Color Key Replace1 — Layer 2

0x10 F65C Color Key Replace1 — Layer 3

0x10 F85C Color Key Replace1 — Layer 4

0x10 FA5C Color Key Replace1 — Layer 5

0x10 F260 Color Key2 AND Mask —

0x10 F460 Color Key2 AND Mask —

0x10 F660 Color Key2 AND Mask —

0x10 F860 Color Key2 AND Mask —

0x10 FA60 Color Key2 AND Mask —

0x10 F264 Color Key Up2 — Layer 1 349 0x10 F464 Color Key Up2 — Layer 2 349 0x10 F664 Color Key Up2 — Layer 3 349 0x10 F864 Color Key Up2 — Layer 4 349 0x10 FA64 Color Key Up2 — Layer 5 349 0x10 F268 Color Key Low2 — Layer 1 . .

0x10 F468 Color Key Low2 — Layer 2 . .

0x10 F668 Color Key Low2 — Layer 3 . .

0x10 F868 Color Key Low2 — Layer 4 . .

0x10 FA68 Color Key Low2 — Layer 5 . .

348

Layer 1 . . . . . . . . . . . . . . . 348

Layer 2 . . . . . . . . . . . . . . . 348

Layer 3 . . . . . . . . . . . . . . . 348

Layer 4 . . . . . . . . . . . . . . . 348

Layer 5 . . . . . . . . . . . . . . . 348

Layer 1 . . . . . . . . . . . . . . . 348

Layer 2 . . . . . . . . . . . . . . . 348

Layer 3 . . . . . . . . . . . . . . . 348

Layer 4 . . . . . . . . . . . . . . . 348

Layer 5 . . . . . . . . . . . . . . . 348

349

Layer 1 . . . . . . . . . . . . . . . 349

Layer 2 . . . . . . . . . . . . . . . 349

Layer 3 . . . . . . . . . . . . . . . 349

Layer 4 . . . . . . . . . . . . . . . 349

Layer 5 . . . . . . . . . . . . . . . 349

350

0x10 F26C Color Key Replace2 — Layer 1

0x10 F46C Color Key Replace2 — Layer 2

0x10 F66C Color Key Replace2 — Layer 3

0x10 F86C Color Key Replace2 — Layer 4

0x10 FA6C Color Key Replace2 — Layer 5

0x10 F270 Color Key3 AND Mask —

0x10 F470 Color Key3 AND Mask —

0x10 F670 Color Key3 AND Mask —

0x10 F870 Color Key3 AND Mask —

0x10 FA70 Color Key3 AND Mask —

0x10 F274 Color Key Up3 — Layer 1 350 0x10 F474 Color Key Up3 — Layer 2 350 0x10 F674 Color Key Up3 — Layer 3 350 0x10 F874 Color Key Up3 — Layer 4 350 0x10 FA74 Color Key Up3 — Layer 5 350 0x10 F278 Color Key Low3 — Layer 1 .

0x10 F478 Color Key Low3 — Layer 2 .

0x10 F678 Color Key Low3 — Layer 3 .

0x10 F878 Color Key Low3 — Layer 4 .

0x10 FA78 Color Key Low3 — Layer 5 .

0x10 F27C Color Key Replace3 — Layer 1

0x10 F47C Color Key Replace3 — Layer 2

0x10 F67C Color Key Replace3 — Layer 3

0x10 F87C Color Key Replace3 — Layer 4

0x10 FA7C Color Key Replace3 — Layer 5

0x10 F280 Color Key4 AND Mask —

0x10 F480 Color Key4 AND Mask —

0x10 F680 Color Key4 AND Mask —

0x10 F880 Color Key4 AND Mask —

0x10 FA80 Color Key4 AND Mask —

0x10 F284 Color Key Up4 — Layer 1 351 0x10 F484 Color Key Up4 — Layer 2 351 0x10 F684 Color Key Up4 — Layer 3 351 0x10 F884 Color Key Up4 — Layer 4 351 0x10 FA84 Color Key Up4 — Layer 5 351 0x10 F288 Color Key Low4 — Layer 1 .

0x10 F488 Color Key Low4 — Layer 2 .

0x10 F688 Color Key Low4 — Layer 3 .

0x10 F888 Color Key Low4 — Layer 4 .

0x10 FA88 Color Key Low4 — Layer 5 .

0x10 F28C Color Key Replace4 — Layer 1

0x10 F48C Color Key Replace4 — Layer 2

0x10 F68C Color Key Replace4 — Layer 3

0x10 F88C Color Key Replace4 — Layer 4

0x10 FA8C Color Key Replace4 — Layer 5

350

Layer 1 . . . . . . . . . . . . . . 350

Layer 2 . . . . . . . . . . . . . . 350

Layer 3 . . . . . . . . . . . . . . 350

Layer 4 . . . . . . . . . . . . . . 350

Layer 5 . . . . . . . . . . . . . . 350

350

351

Layer 1 . . . . . . . . . . . . . . 351

Layer 2 . . . . . . . . . . . . . . 351

Layer 3 . . . . . . . . . . . . . . 351

Layer 4 . . . . . . . . . . . . . . 351

Layer 5 . . . . . . . . . . . . . . 351

351

Preliminary Rev. 02 — July 22 2004 xx

Page 22

Philips Semiconductors

PNX8550

0x10 F290 Color Key Mask/ROP — Layer

0x10 F490 Color Key Mask/ROP — Layer

0x10 F690 Color Key Mask/ROP — Layer

0x10 F890 Color Key Mask/ROP — Layer

0x10 FA90 Color Key Mask/ROP — Layer

0x10 F294 Pixel Invert/Select ROP —

0x10 F494 Pixel Invert/Select ROP —

0x10 F694 Pixel Invert/Select ROP —

0x10 F894 Pixel Invert/Select ROP —

0x10 FA94 Pixel Invert/Select ROP —

0x10 F298 Alpha Blend/Key Pass —

0x10 F498 Alpha Blend/Key Pass —

0x10 F698 Alpha Blend/Key Pass —

0x10 F898 Alpha Blend/Key Pass —

0x10 FA98 Alpha Blend/Key Pass —

0x10 F29C Alpha Pass — Layer 1 . . . 353 0x10 F49C Alpha Pass — Layer 2 . . . 353 0x10 F69C Alpha Pass — Layer 3 . . . 353 0x10 F89C Alpha Pass — Layer 4 . . . 353 0x10 FA9C Alpha Pass — Layer 5 . . . 353 0x10 F2A0 Color Key ROPs 1/2 — Layer 1

0x10 F4A0 Color Key ROPs 1/2 — Layer 2

0x10 F6A0 Color Key ROPs 1/2 — Layer 3

0x10 F8A0 Color Key ROPs 1/2 — Layer 4

0x10 FAA0 Color Key ROPs 1/2 — Layer 5

0x10 F2A4 Color Key ROPs 3/4 — Layer 1

0x10 F4A4 Color Key ROPs 3/4 — Layer 2

0x10 F6A4 Color Key ROPs 3/4 — Layer 3

0x10 F8A4 Color Key ROPs 3/4 — Layer 4

0x10 FAA4 Color Key ROPs 3/4 — Layer 5

0x10 F2A8 INTR — Layer 1 . . . . . . . . 354

0x10 F4A8 INTR — Layer 2 . . . . . . . . 354

0x10 F6A8 INTR — Layer 3 . . . . . . . . 354

0x10 F8A8 INTR — Layer 4 . . . . . . . . 354

0x10 FAA8 INTR — Layer 5 . . . . . . . . 354

0x10 F2AC HSRU Phase — Layer 1 . 354 0x10 F4AC HSRU Phase — Layer 2 . 354 0x10 F6AC HSRU Phase — Layer 3 . 354 0x10 F8AC HSRU Phase — Layer 4 . 354 0x10 FAAC HSRU Phase — Layer 5 . 354 0x10 F2B0 HSRU Delta Phase — Layer 1

0x10 F4B0 HSRU Delta Phase — Layer 2

0x10 F6B0 HSRU Delta Phase — Layer 3

0x10 F8B0 HSRU Delta Phase — Layer 4

0x10 FAB0 HSRU Delta Phase — Layer 5

0x10 F2B4 Layer Size (Final) — Layer 1 .

0x10 F4B4 Layer Size (Final) — Layer 2 .

351

1 . . . . . . . . . . . . . . . . . . . . 352

2 . . . . . . . . . . . . . . . . . . . . 352

3 . . . . . . . . . . . . . . . . . . . . 352

4 . . . . . . . . . . . . . . . . . . . . 352

5 . . . . . . . . . . . . . . . . . . . . 352

Layer 1 . . . . . . . . . . . . . . . 352

Layer 2 . . . . . . . . . . . . . . . 352

Layer 3 . . . . . . . . . . . . . . . 352

Layer 4 . . . . . . . . . . . . . . . 352

Layer 5 . . . . . . . . . . . . . . . 352

Layer 1 . . . . . . . . . . . . . . . 353

Layer 2 . . . . . . . . . . . . . . . 353

Layer 3 . . . . . . . . . . . . . . . 353

Layer 4 . . . . . . . . . . . . . . . 353

Layer 5 . . . . . . . . . . . . . . . 353

353

354

355

0x10 F6B4 Layer Size (Final) — Layer 3

0x10 F8B4 Layer Size (Final) — Layer 4

0x10 FAB4 Layer Size (Final) — Layer 5

0x10 F2B8 Output and Alpha Manipulation

0x10 F4B8 Output and Alpha Manipulation

0x10 F6B8 Output and Alpha Manipulation

0x10 F8B8 Output and Alpha Manipulation

0x10 FAB8 Output and Alpha Manipulation

0x10 F2BC Formats — Layer 1 . . . . 357

0x10 F4BC Formats — Layer 2 . . . . 357

0x10 F6BC Formats — Layer 3 . . . . 357

0x10 F8BC Formats — Layer 4 . . . . 357

0x10 FABC Formats — Layer 5 . . . . 357

0x10 F2C0 Layer Background Color —

0x10 F4C0 Layer Background Color —

0x10 F6C0 Layer Background Color —

0x10 F8C0 Layer Background Color —

0x10 FAC0 Layer Background Color —

0x10 F2C4 Variable Format Register —

0x10 F4C4 Variable Format Register —

0x10 F6C4 Variable Format Register —

0x10 F8C4 Variable Format Register —

0x10 FAC4 Variable Format Register —

0x10 F2C8 Start Fetch — Layer 1 . . 358 0x10 F4C8 Start Fetch — Layer 2 . . 358 0x10 F6C8 Start Fetch — Layer 3 . . 358 0x10 F8C8 Start Fetch — Layer 4 . . 358 0x10 FAC8 Start Fetch — Layer 5 . . 358 0x10 F2CC Brightness & Contrast — Layer

0x10 F4CC Brightness & Contrast — Layer

0x10 F6CC Brightness & Contrast — Layer

0x10 F8CC Brightness & Contrast — Layer

0x10 FACC Brightness & Contrast — Layer

0x10 F2D0 Matrix Coefficients 1 — Layer

0x10 F4D0 Matrix Coefficients 1 — Layer

0x10 F6D0 Matrix Coefficients 1 — Layer

0x10 F8D0 Matrix Coefficients 1 — Layer

0x10 FAD0 Matrix Coefficients 1 — Layer

0x10 F2D4 Matrix Coefficients 2 — Layer

0x10 F4D4 Matrix Coefficients 2 — Layer

0x10 F6D4 Matrix Coefficients 2 — Layer

0x10 F8D4 Matrix Coefficients 2 — Layer

0x10 FAD4 Matrix Coefficients 2 — Layer

0x10 F2D8 Matrix Coefficients 3 — Layer

0x10 F4D8 Matrix Coefficients 3 — Layer

355

— Layer 1 . . . . . . . . . . . . 355

— Layer 2 . . . . . . . . . . . . 355

— Layer 3 . . . . . . . . . . . . 355

— Layer 4 . . . . . . . . . . . . 355

— Layer 5 . . . . . . . . . . . . 355

Layer 1 . . . . . . . . . . . . . . 357

Layer 2 . . . . . . . . . . . . . . 357

Layer 3 . . . . . . . . . . . . . . 357

Layer 4 . . . . . . . . . . . . . . 357

Layer 5 . . . . . . . . . . . . . . 357

Layer 1 . . . . . . . . . . . . . . 358

Layer 2 . . . . . . . . . . . . . . 358

Layer 3 . . . . . . . . . . . . . . 358

Layer 4 . . . . . . . . . . . . . . 358

Layer 5 . . . . . . . . . . . . . . 358

1 . . . . . . . . . . . . . . . . . . . 359

2 . . . . . . . . . . . . . . . . . . . 359

3 . . . . . . . . . . . . . . . . . . . 359

4 . . . . . . . . . . . . . . . . . . . 359

5 . . . . . . . . . . . . . . . . . . . 359

1 . . . . . . . . . . . . . . . . . . . 360

2 . . . . . . . . . . . . . . . . . . . 360

3 . . . . . . . . . . . . . . . . . . . 360

4 . . . . . . . . . . . . . . . . . . . 360

5 . . . . . . . . . . . . . . . . . . . 360

1 . . . . . . . . . . . . . . . . . . . 360

2 . . . . . . . . . . . . . . . . . . . 360

3 . . . . . . . . . . . . . . . . . . . 360

4 . . . . . . . . . . . . . . . . . . . 360

5 . . . . . . . . . . . . . . . . . . . 360

1 . . . . . . . . . . . . . . . . . . . 360

2 . . . . . . . . . . . . . . . . . . . 360

Preliminary Rev. 02 — July 22 2004 xxi

Page 23

Philips Semiconductors

PNX8550

0x10 F6D8 Matrix Coefficients 3 — Layer

0x10 F8D8 Matrix Coefficients 3 — Layer

0x10 FAD8 Matrix Coefficients 3 — Layer

0x10 F2DC Matrix Coefficients 4 — Layer

0x10 F4DC Matrix Coefficients 4 — Layer

0x10 F6DC Matrix Coefficients 4 — Layer

0x10 F8DC Matrix Coefficients 4 — Layer

0x10 FADC Matrix Coefficients 4 — Layer

0x10 F2E0 Matrix Coefficients 5 — Layer

0x10 F4E0 Matrix Coefficients 5 — Layer

0x10 F6E0 Matrix Coefficients 5 — Layer

0x10 F8E0 Matrix Coefficients 5 — Layer

0x10 FAE0 Matrix Coefficients 5 — Layer

0x10 F2E8 LSHR_PAR_0 — Layer 1 361 0x10 F4E8 LSHR_PAR_0 — Layer 2 361 0x10 F6E8 LSHR_PAR_0 — Layer 3 361 0x10 F8E8 LSHR_PAR_0 — Layer 4 361 0x10 FAE8 LSHR_PAR_0 — Layer 5 361 0x10 F2EC LSHR_PAR_1 — Layer 1 362 0x10 F4EC LSHR_PAR_1 — Layer 2 362 0x10 F6EC LSHR_PAR_1 — Layer 3 362 0x10 F8EC LSHR_PAR_1 — Layer 4 362 0x10 FAEC LSHR_PAR_1 — Layer 5 362 0x10 F2F0 LSHR_PAR_2 — Layer 1 362 0x10 F4F0 LSHR_PAR_2 — Layer 2 362 0x10 F6F0 LSHR_PAR_2 — Layer 3 362 0x10 F8F0 LSHR_PAR_2 — Layer 4 362 0x10 FAF0 LSHR_PAR_2 — Layer 5 362 0x10 F2F4 LSHR_PAR_3 — Layer 1 363 0x10 F4F4 LSHR_PAR_3 — Layer 2 363 0x10 F6F4 LSHR_PAR_3 — Layer 3 363 0x10 F8F4 LSHR_PAR_3 — Layer 4 363 0x10 FAF4 LSHR_PAR_3 — Layer 5 363 0x10 F2F8 LSHR_E_max — Layer 1 363 0x10 F4F8 LSHR_E_max — Layer 2 363 0x10 F6F8 LSHR_E_max — Layer 3 363 0x10 F8F8 LSHR_E_max — Layer 4 363 0x10 FAF8 LSHR_E_max — Layer 5 363 0x10 F2FC LSHR_E_Sum — Layer 1 364 0x10 F4FC LSHR_E_Sum — Layer 2 364 0x10 F6FC LSHR_E_Sum — Layer 3 364 0x10 F8FC LSHR_E_Sum — Layer 4 364 0x10 FAFC LSHR_E_Sum — Layer 5 364 0x10 F300 LSHR Measurement Window

0x10 F500 LSHR Measurement Window

0x10 F700 LSHR Measurement Window

0x10 F900 LSHR Measurement Window

0x10 FB00 LSHR Measurement Window

0x10 F304 LSHR Measurement Window

0x10 F504 LSHR Measurement Window

0x10 F704 LSHR Measurement Window

0x10 F904 LSHR Measurement Window

0x10 FB04 LSHR Measurement Window

0x10 F320 Layer Solid Color — Layer 1 .

0x10 F520 Layer Solid Color — Layer 2 .

3 . . . . . . . . . . . . . . . . . . . . 360

4 . . . . . . . . . . . . . . . . . . . . 360

5 . . . . . . . . . . . . . . . . . . . . 360

1 . . . . . . . . . . . . . . . . . . . . 361

2 . . . . . . . . . . . . . . . . . . . . 361

3 . . . . . . . . . . . . . . . . . . . . 361

4 . . . . . . . . . . . . . . . . . . . . 361

5 . . . . . . . . . . . . . . . . . . . . 361

1 . . . . . . . . . . . . . . . . . . . . 361

2 . . . . . . . . . . . . . . . . . . . . 361

3 . . . . . . . . . . . . . . . . . . . . 361

4 . . . . . . . . . . . . . . . . . . . . 361

5 . . . . . . . . . . . . . . . . . . . . 361

Start — Layer 1 . . . . . . . . 364

Start — Layer 2 . . . . . . . . 364

Start — Layer 3 . . . . . . . . 364

Start — Layer 4 . . . . . . . . 364

Start — Layer 5 . . . . . . . . 364

End — Layer 1 . . . . . . . . . 364

End — Layer 2 . . . . . . . . . 364

End — Layer 3 . . . . . . . . . 364

End — Layer 4 . . . . . . . . . 364

End — Layer 5 . . . . . . . . . 364

364

0x10 F720 Layer Solid Color — Layer 3

0x10 F920 Layer Solid Color — Layer 4

0x10 FB20 Layer Solid Color — Layer 5

0x10 F324 Layer LUT-HIST Bins 00 to 03

0x10 F524 Layer LUT-HIST Bins 00 to 03

0x10 F724 Layer LUT-HIST Bins 00 to 03

0x10 F924 Layer LUT-HIST Bins 00 to 03

0x10 FB24 Layer LUT-HIST Bins 00 to 03

0x10 F328 Layer LUT-HIST Bins 04 to 07

0x10 F528 Layer LUT-HIST Bins 04 to 07

0x10 F728 Layer LUT-HIST Bins 04 to 07

0x10 F928 Layer LUT-HIST Bins 04 to 07

0x10 FB28 Layer LUT-HIST Bins 04 to 07

0x10 F32C Layer LUT-HIST Bins 08 to

0x10 F52C Layer LUT-HIST Bins 08 to

0x10 F72C Layer LUT-HIST Bins 08 to

0x10 F92C Layer LUT-HIST Bins 08 to

0x10 FB2C Layer LUT-HIST Bins 08 to

0x10 F330 Layer LUT-HIST Bins 12 to 15

0x10 F530 Layer LUT-HIST Bins 12 to 15

0x10 F730 Layer LUT-HIST Bins 12 to 15

0x10 F930 Layer LUT-HIST Bins 12 to 15

0x10 FB30 Layer LUT-HIST Bins 12 to 15

0x10 F334 Layer LUT-HIST Bins 16 to 19

0x10 F534 Layer LUT-HIST Bins 16 to 19

0x10 F734 Layer LUT-HIST Bins 16 to 19

0x10 F934 Layer LUT-HIST Bins 16 to 19

0x10 FB34 Layer LUT-HIST Bins 16 to 19

0x10 F338 Layer LUT-HIST Bins 20 to 23

0x10 F538 Layer LUT-HIST Bins 20 to 23

0x10 F738 Layer LUT-HIST Bins 20 to 23

0x10 F938 Layer LUT-HIST Bins 20 to 23

0x10 FB38 Layer LUT-HIST Bins 20 to 23

0x10 F33C Layer LUT-HIST Bins 24 to

0x10 F53C Layer LUT-HIST Bins 24 to

0x10 F73C Layer LUT-HIST Bins 24 to

0x10 F93C Layer LUT-HIST Bins 24 to

0x10 FB3C Layer LUT-HIST Bins 24 to

0x10 F340 Layer LUT-HIST Bins 28 to 31

0x10 F540 Layer LUT-HIST Bins 28 to 31

364

— Layer 1 . . . . . . . . . . . . 365

— Layer 2 . . . . . . . . . . . . 365

— Layer 3 . . . . . . . . . . . . 365

— Layer 4 . . . . . . . . . . . . 365

— Layer 5 . . . . . . . . . . . . 365

— Layer 1 . . . . . . . . . . . . 365

— Layer 2 . . . . . . . . . . . . 365

— Layer 3 . . . . . . . . . . . . 365

— Layer 4 . . . . . . . . . . . . 365

— Layer 5 . . . . . . . . . . . . 365

011 — Layer 1 . . . . . . . . 365

011 — Layer 2 . . . . . . . . 365

011 — Layer 3 . . . . . . . . 365

011 — Layer 4 . . . . . . . . 365

011 — Layer 5 . . . . . . . . 365

— Layer 1 . . . . . . . . . . . . 365

— Layer 2 . . . . . . . . . . . . 365

— Layer 3 . . . . . . . . . . . . 365

— Layer 4 . . . . . . . . . . . . 365

— Layer 5 . . . . . . . . . . . . 365

— Layer 1 . . . . . . . . . . . . 366

— Layer 2 . . . . . . . . . . . . 366

— Layer 3 . . . . . . . . . . . . 366

— Layer 4 . . . . . . . . . . . . 366

— Layer 5 . . . . . . . . . . . . 366

— Layer 1 . . . . . . . . . . . . 366

— Layer 2 . . . . . . . . . . . . 366

— Layer 3 . . . . . . . . . . . . 366

— Layer 4 . . . . . . . . . . . . 366

— Layer 5 . . . . . . . . . . . . 366

027 — Layer 1 . . . . . . . . 366

027 — Layer 2 . . . . . . . . 366

027 — Layer 3 . . . . . . . . 366

027 — Layer 4 . . . . . . . . 366

027 — Layer 5 . . . . . . . . 366

— Layer 1 . . . . . . . . . . . . 366

— Layer 2 . . . . . . . . . . . . 366

Preliminary Rev. 02 — July 22 2004 xxii

Page 24

Philips Semiconductors

PNX8550

0x10 F740 Layer LUT-HIST Bins 28 to 31

0x10 F940 Layer LUT-HIST Bins 28 to 31

0x10 FB40 Layer LUT-HIST Bins 28 to 31

0x10 F344 Layer Histogram Control —

0x10 F544 Layer Histogram Control —

0x10 F744 Layer Histogram Control —

0x10 F944 Layer Histogram Control —

0x10 FB44 Layer Histogram Control —

0x10 F348 Layer CFTR Blue — Layer 1 .

0x10 F548 Layer CFTR Blue — Layer 2 .

0x10 F748 Layer CFTR Blue — Layer 3 .

0x10 F948 Layer CFTR Blue — Layer 4 .

0x10 FB48 Layer CFTR Blue — Layer 5 .

— Layer 3 . . . . . . . . . . . . 366

— Layer 4 . . . . . . . . . . . . 366

— Layer 5 . . . . . . . . . . . . 366

Layer 1 . . . . . . . . . . . . . . . 367

Layer 2 . . . . . . . . . . . . . . . 367

Layer 3 . . . . . . . . . . . . . . . 367

Layer 4 . . . . . . . . . . . . . . . 367

Layer 5 . . . . . . . . . . . . . . . 367

367

Audio Output Port 1 Registers (Rev 0.5)

0x11 0000 AO_STATUS—DTL Clock

0x11 0004 AO_CTL—DTL Clock Domain

0x11 0008 AO_SERIAL—DTL Clock

0x11 000C AO_FRAMING—DMA Clock

0x11 0010 Reserved—DTL Clock Domain

0x11 0014 AO_BASE1—DTL Clock

0x11 0018 AO_BASE2—DTL Clock

Domain . . . . . . . . . . . . . . 370

371

Domain . . . . . . . . . . . . . . 372

373

Domain . . . . . . . . . . . . . . 373

0x10 F34C Layer CFTR Green — Layer 1

0x10 F54C Layer CFTR Green — Layer 2

0x10 F74C Layer CFTR Green — Layer 3

0x10 F94C Layer CFTR Green — Layer 4

0x10 FB4C Layer CFTR Green — Layer 5

0x10 F350 Layer DCTI Control — Layer 1

0x10 F550 Layer DCTI Control — Layer 2

0x10 F750 Layer DCTI Control — Layer 3

0x10 F950 Layer DCTI Control — Layer 4

0x10 FB50 Layer DCTI Control — Layer 5

0x10 FFE0 Interrupt Status QVCP . . 369 0x10 FFE4 Interrupt Enable QVCP . 370 0x10 FFE8 Interrupt Clear QVCP . . . 370

0x10 FFEC Interrupt Set QVCP . . . . 370

0x10 FFF4 Powerdown . . . . . . . . . . 370

0x10 FFFC Module ID . . . . . . . . . . . . 370

0x11 001C AO_SIZE—DMA Clock

0x11 0020 AO_CC—DMA Clock Domain

0x11 0024 AO_CFC—DMA Clock

0x11 0028—0FF0 Reserved—DTL Clock Domain

0x11 0FF4 AO_PWR_DWN—DTL Clock

0x11 0FFC AO_MODULE_ID—DTL Clock

368

Domain . . . . . . . . . . . . . . 373

373

Domain . . . . . . . . . . . . . . 373

374

Domain . . . . . . . . . . . . . . 374

Audio (I2S) Input Ports 1 Registers (Rev 0.6)

0x11 1000 AI_STATUS . . . . . . . . . . . 374

0x11 1004 AI_CTL . . . . . . . . . . . . . . 374

0x11 1008 AI_SERIAL . . . . . . . . . . . 375

0x11 100C AI_FRAMING . . . . . . . . . . 376

0x11 1010 Reserved . . . . . . . . . . . . . 376

0x11 1014 AI_BASE1 . . . . . . . . . . . . 377

0x11 1018 AI_BASE2 . . . . . . . . . . . . 377

0x11 101C AI_SIZE . . . . . . . . . . . . . 377

0x11 1020—1FEC Reserved . . . . . . . . . . . . 377

0x11 1FF0 SW_RESET . . . . . . . . . . 377

0x11 1FF4 AI_PWR_DWN . . . . . . . . 377

0x11 1FF8 MODULE_ID_EXT . . . . . 377

0x11 1FFC AI_MODULE_ID . . . . . . . 377

Audio Output Port 2 Registers (Rev 0.5)

0x11 2000 AO_STATUS—DTL Clock

0x11 2004 AO_CTL—DTL Clock Domain

0x11 2008 AO_SERIAL—DTL Clock

0x11 200C AO_FRAMING—DMA Clock

0x11 2010 Reserved—DTL Clock Domain

0x11 2014 AO_BASE1—DTL Clock

0x11 2018 AO_BASE2—DTL Clock

Domain . . . . . . . . . . . . . . 378

378

Domain . . . . . . . . . . . . . . 379

Domain . . . . . . . . . . . . . . 380

380

Domain . . . . . . . . . . . . . . 380

0x11 201C AO_SIZE—DMA Clock

0x11 2020 AO_CC—DMA Clock Domain

0x11 2024 AO_CFC—DMA Clock

0x11 2028—2FF0 Reserved—DTL Clock Domain

0x11 2FF4 AO_PWR_DWN—DTL Clock

0x11 2FFC AO_MODULE_ID—DTL Clock

Domain . . . . . . . . . . . . . . 380

Domain . . . . . . . . . . . . . . 381

381

Domain . . . . . . . . . . . . . . 381

381

Domain . . . . . . . . . . . . . . 381

Audio (I2S) Input Ports 2 Registers (Rev 0.6)

0x11 3000 AI_STATUS . . . . . . . . . . . 381

0x11 3004 AI_CTL . . . . . . . . . . . . . . 382

0x11 3008 AI_SERIAL . . . . . . . . . . . 383

0x11 300C AI_FRAMING . . . . . . . . . . 384

0x11 3010 Reserved . . . . . . . . . . . . . 384

0x11 3014 AI_BASE1 . . . . . . . . . . . . 384

0x11 3018 AI_BASE2 . . . . . . . . . . . . 384

Preliminary Rev. 02 — July 22 2004 xxiii

0x11 301C AI_SIZE . . . . . . . . . . . . . 384

0x11 3020—3FEC Reserved . . . . . . . . . . . . 384

0x11 3FF0 SW_RESET . . . . . . . . . . 385

0x11 3FF4 AI_PWR_DWN . . . . . . . . 385

0x11 3FF8 MODULE_ID_EXT . . . . . 385

0x11 3FFC AI_MODULE_ID . . . . . . . 385

Page 25

Philips Semiconductors

EDMA Controller Registers (Rev 2.4.1)

0x11 4000 DMA_CMD0 . . . . . . . . . . 385

0x11 4004 SRC_ADDR0 . . . . . . . . . . 386

0x11 4008 DST_ADDR0 . . . . . . . . . . 386

0x11 400C Reserved . . . . . . . . . . . . . 386

0x11 4010 Link List Pointer0 . . . . . . . 386

0x11 4014—401C Reserved . . . . . . . . . . . . . 386

0x11 4020 DMA_CMD1 . . . . . . . . . . 386

0x11 4024 SRC_ADDR1 . . . . . . . . . . 387

0x11 4028 DST_ADDR1 . . . . . . . . . . 387

0x11 402C Reserved . . . . . . . . . . . . . 387

0x11 4030 Channel Link List Pointer1 . . .

0x11 4034—403C Reserved . . . . . . . . . . . . . 387

0x11 4040 DMA_CMD2 . . . . . . . . . . 387

0x11 4044 SRC_ADDR2 . . . . . . . . . . 388

0x11 4048 DST_ADDR2 . . . . . . . . . . 388

0x11 404C Reserved . . . . . . . . . . . . . 388

0x11 4050 Channel Link List Pointer2 . . .

0x11 4054—405C Reserved . . . . . . . . . . . . . 388

0x11 4060 DMA_CMD3 . . . . . . . . . . 388

0x11 4064 SRC_ADDR3 . . . . . . . . . . 389

0x11 4068 DST_ADDR3 . . . . . . . . . . 389

0x11 406C Reserved . . . . . . . . . . . . . 389

0x11 4070 Channel Link List Pointer3 . . .

0x11 4074—40FC Reserved . . . . . . . . . . . . . 389

0x11 4100 CRC . . . . . . . . . . . . . . . . . 389

0x11 4104—411C Reserved . . . . . . . . . . . . . 389

0x11 4120 DMA_CHEN0 . . . . . . . . . 389

0x062124 DMA_CHENL1 . . . . . . . . 389

0x11 4128 DMA_CHEN2 . . . . . . . . . 389

0x11 412C DMA_CHEN3 . . . . . . . . . 389

387

388

389

PNX8550

0x11 4130—413C Reserved . . . . . . . . . . . . 389

0x11 4140 DMA Status Register0 . . 390 0x11 4144 DMA Status Register1 . . 390 0x11 4148 DMA Status Register2 . . 391 0x11 414C DMA Status Register3 . . 392

0x11 4150—41FC Reserved . . . . . . . . . . . . 393

0x11 4200 KMU Control Register . . 393 0x11 4204 KMU Status Register . . . 394

0x11 4208—420C Reserved . . . . . . . . . . . . 394

0x11 4210 Reference Key0 Register 394 0x11 4214 Reference Key1 Register 394 0x11 4218 Reference Key2 Register 395 0x11 421C Reference Key3 Register 395

0x11 4220—424C Reserved . . . . . . . . . . . . 395

0x11 4250 AES SRAM VALID Register .

0x11 4254 AES SRAM CLEAR Register

0x11 4258—42FC Reserved . . . . . . . . . . . . 395

0x11 4300 SCN Register0 . . . . . . . 395

0x11 4304 SCN Register1 . . . . . . . 395

0x11 4308—4BFC Reserved . . . . . . . . . . . . 395

0x11 4C00 DMA Soft Reset Register 395

0x11 4C04—4FDC Reserved . . . . . . . . . . . . 395

0x11 4FE0 Interrupt Status Register 395 0x11 4FE4 Interrupt Enable Register 396 0x11 4FE8 Interrupt Clear Register . 396 0x11 4FEC Interrupt Set Register . . . 396

0x11 4FF0 Reserved . . . . . . . . . . . . 396

0x11 4FF4 Power Down . . . . . . . . . . 396

0x11 4FF8—4FF8 Reserved . . . . . . . . . . . . 396

0x11 4FFC Module ID . . . . . . . . . . . . 396

395

TriMedia DCS Network Controller Security Registers (Rev 1.6)

0x11 5000 TMBC_CONFIG (Bus

0x11 5004 TMBC_SEC (Bus Controller

Controller Configuration Aperture Security Setting) 397

Security Aperture Security

TSDMA Registers (Rev 1.9.2)

0x11 6000 TSDMA_CTRL . . . . . . . . . 397

0x11 6004 TSDMA1_START_ADDRESS

0x11 6008 TSDMA1_PACKET_LENGTH

0x11 600C TSDMA1_SIZE . . . . . . . . 399

0x11 6010 TSDMA1_THRESHOLD . 399 0x11 6014 TSDMA1_DELIVERY

0x11 6018 TSDMA2_START_ADDRESS

0x11 601C TSDMA2_PACKET_LENGTH

0x11 6020 TSDMA2_SIZE . . . . . . . . 399

0x11 6024 TSDMA2_THRESHOLD . 399 0x11 6028

399

OFFSET . . . . . . . . . . . . . 399

399

DENC Registers (Rev 0.2.4)

0x11 7000 STATUS . . . . . . . . . . . . . 402

0x11 7068 MSMT . . . . . . . . . . . . . . . 402

0x11 706C MSMS . . . . . . . . . . . . . . . 402

0x11 7098 WSS1 . . . . . . . . . . . . . . . 403

0x11 709C WSS2 . . . . . . . . . . . . . . . 403

0x11 70A0 RTC1/BCTL1 . . . . . . . . . . 403

0x11 70A4 BCTL2 . . . . . . . . . . . . . . . 403

0x11 70A8 CGD1 . . . . . . . . . . . . . . . . 403

0x11 70AC CGD2 . . . . . . . . . . . . . . . . 403

0x11 7B0 CGD . . . . . . . . . . . . . . . . . 403

0x11 70B4 DACCTL Video Data Path 404

0x11 70E8 INPCTL . . . . . . . . . . . . . . 404

0x11 7150 VPS1 . . . . . . . . . . . . . . . . 404

0x11 5200—5280 Target Security Registers

0x11 5284—5FF8 Reserved . . . . . . . . . . . . 397

0x11 5FFC TMBCSEC_MODULE_ID 397

0x11 602C TSDMA_TIMEOUT_VALUE .

0x11 6030 TSDMA_TSTAMP_SEL . 400 0x11 6034 TSDMA_DMA_COUNT . 400

0x11 6038—6FDC Reserved . . . . . . . . . . . . 400

0x11 6FE0 TSDMA_INT_STATUS . . 400

0x11 6FE4 TSDMA_INT_EN . . . . . . 401

0x11 6FE8 TSDMA_INT_CLR . . . . . 401

0x11 6FEC TSDMA_INT_SET . . . . . 401

0x11 6FF0 Reserved . . . . . . . . . . . . 401

0x11 6FF4 Power Down . . . . . . . . . . 402

0x11 6FF8 Reserved . . . . . . . . . . . . 402

0x11 6FFC TSDMA_MOD_ID . . . . . . 402

0x11 7154 VPS2 . . . . . . . . . . . . . . . 404

0x11 7158 VPS3 . . . . . . . . . . . . . . . 404

0x11 715C VPS4 . . . . . . . . . . . . . . . 404

0x11 7160 VPS5 . . . . . . . . . . . . . . . 404

0x11 7164 VPS6 . . . . . . . . . . . . . . . 404

0x11 7168 CHPS . . . . . . . . . . . . . . . 405

0x11 716C—7174 (MSB) GAINU . . . . . . . . . 405

0x11 7170—7178 (MSB) GAINV . . . . . . . . . 405

0x11 7174 BLCKL . . . . . . . . . . . . . . 405

0x11 7178 BLNNL . . . . . . . . . . . . . . 406

0x11 717C BLNVB/CCR . . . . . . . . . . 406

0x11 7180 Must be initialized to zero. 406

0x11 7184 STDCTL . . . . . . . . . . . . . 406

Setting) . . . . . . . . . . . . . . 397

(One for each target) . . . 397

TSDMA2_DELIVERY_OFFSE

T . . . . . . . . . . . . . . . . . . . 400

400

Preliminary Rev. 02 — July 22 2004 xxiv

Page 26

Philips Semiconductors

PNX8550

0x11 7188 RTCCTL/BSTA . . . . . . . . 406

0x11 718C—7198 FSC0—FSC3 . . . . . . . . . . 407

0x11 719C L21O0 . . . . . . . . . . . . . . . 407

0x11 71A0 L21O1 . . . . . . . . . . . . . . . 407

0x11 71A4 L21E0 . . . . . . . . . . . . . . . 407

0x11 71A8 L21E1 . . . . . . . . . . . . . . . 407

0x11 71AC Must be initialized to zero. 407

0x11 71B0 TRGCTL1 . . . . . . . . . . . . 407

0x11 71B4 TRGCTL2 . . . . . . . . . . . . 407

0x11 71B8 MULTICTL . . . . . . . . . . . . 408

0x11 71BC TTXCTL . . . . . . . . . . . . . . 408

0x11 71C0 ADWHS . . . . . . . . . . . . . . 408

0x11 71C4 ADWHE . . . . . . . . . . . . . . 408

0x11 71C8 ADWHS/E . . . . . . . . . . . . 408

0x11 71CC TTXHS . . . . . . . . . . . . . . . 409

0x11 71D0 TTXHL/TTXHD . . . . . . . . 409

0x11 71D4 CSYNCA . . . . . . . . . . . . . 409

0x11 71D8 TTXOVS . . . . . . . . . . . . . 409

0x11 71DC TTXOVE . . . . . . . . . . . . . 409

0x11 71E0 TTXEVS . . . . . . . . . . . . . . 409

MSP 1 Registers (Rev 0.4)

0x11 8000—817C DQHDPTR . . . . . . . . . . . . 412

0x11 81A0 DQISTAT2 . . . . . . . . . . . . 412

0x11 81A4 DQISTAT1 . . . . . . . . . . . . 412

0x11 81A8 DQISTAT0 . . . . . . . . . . . . 412

0x11 81BC DQCTL . . . . . . . . . . . . . . 412

0x11 8200 FRMRCTL . . . . . . . . . . . . 413

0x11 8204 FRMRSYNC . . . . . . . . . . 413

0x11 8208 PIDMASK . . . . . . . . . . . . 414

0x11 820C PIDCTL . . . . . . . . . . . . . . 414

0x11 8210 PEAKVAL . . . . . . . . . . . . 415

0x0214 DACDATA . . . . . . . . . . . . 415

0x0218 DACCTL . . . . . . . . . . . . . 415

0x11 821C PCRREG0 . . . . . . . . . . . . 415

0x11 8220 PCRREG1 . . . . . . . . . . . . 415

0x11 8224 PCRREG2 . . . . . . . . . . . . 416

0x11 8228 STCREG0 . . . . . . . . . . . . 416

0x11 822C STCREG1 . . . . . . . . . . . . 416

0x11 8230 STCREG2 . . . . . . . . . . . . 416

0x11 8234 SCRREG0 . . . . . . . . . . . . 416

0x11 8238 SCRREG1 . . . . . . . . . . . . 416

0x11 823C SCRREG2 . . . . . . . . . . . . 416

0x11 8240 ACTSTCREG0 . . . . . . . . 417

0x11 8244 ACTSTCREG1 . . . . . . . . 417

0x11 8248 ACTSTCREG2 . . . . . . . . 417

0x11 824C TIMER1_LO . . . . . . . . . . . 417

0x11 8250 TIMER1_HI . . . . . . . . . . . 417

0x11 8254 TIMER2_LO . . . . . . . . . . . 417

0x11 8258 TIMER2_HI . . . . . . . . . . . 418

0x11 825C DSS_BITRATE . . . . . . . . 418

0x11 8260 FRMR_PACKSIZE . . . . . 418

0x11 8280 DMA_CMD0 . . . . . . . . . . 418

0x11 8284 SRC_ADDR0 . . . . . . . . . . 419

0x11 8288 DST_ADDR0 . . . . . . . . . . 419

0x11 828C LL_PTR0 . . . . . . . . . . . . . 419

0x11 8290 PACKET_SIZE0 . . . . . . . 419

0x11 8294 PDMA0_CTRL . . . . . . . . . 419

0x11 8298 PDMA0_STATUS . . . . . . 419

0x11 829C PDMA0_DELIVERY_DELAY .

0x11 82A0 TS_COUNTER0 . . . . . . . 420

0x11 82A4 DMA_CMD1 Same as

0x11 82A8 SRC_ADDR1 . . . . . . . . . . 420

0x11 82AC DST_ADDR1 . . . . . . . . . . 421

0x11 82B0 LL_PTR1 . . . . . . . . . . . . . 421

0x11 82B4 PACKET_SIZE1 . . . . . . . 421

0x11 82B8 PDMA1_CTRL . . . . . . . . . 421

0x11 82BC PDMA1_STATUS . . . . . . 421

0x11 82C0 PDMA1_DELIVERY_DELAY .

0x11 82C4 TS_COUNTER1 . . . . . . . 422

420

Channel0 . . . . . . . . . . . . . 420

422

0x11 71E4 TTXEVE . . . . . . . . . . . . . 409

0x11 71E8 FAL . . . . . . . . . . . . . . . . . 409

0x11 71EC LAL . . . . . . . . . . . . . . . . . 410

0x11 71F0 TTXCTRL . . . . . . . . . . . . 410

0x11 71F4 Must be initialized to zero. 410

0x11 71F8 DTTXL . . . . . . . . . . . . . . 410

0x11 71FC DTTXL2 . . . . . . . . . . . . . 410

0x11 7254 VMUXCTL . . . . . . . . . . . 410

0x11 7288 BORDER_Y . . . . . . . . . . 410

0x11 728C BORDER_U . . . . . . . . . . 410

0x11 7290 BORDER_V . . . . . . . . . . 410

0x11 7294 MISCCTRL . . . . . . . . . . . 411

0x11 7298 DACC_ADJ . . . . . . . . . . 411

0x11 729C DACY_ADJ . . . . . . . . . . 411

0x11 72A0 DACF_ADJ . . . . . . . . . . . 411

0x11 72E0 SIG3 . . . . . . . . . . . . . . . . 411

0x11 72E4 SIG4 . . . . . . . . . . . . . . . . 411

0x11 72E8 SIGCTRL . . . . . . . . . . . . 411

0x11 7FFC Module ID . . . . . . . . . . . . 411

0x11 82CC PDMA_TIMEOUT . . . . . . 422

0x11 82D4 TSC_ENA . . . . . . . . . . . . 422

0x11 82D8 TSC_ENB . . . . . . . . . . . . 422

0x11 8300—83FC PIDTABLE . . . . . . . . . . . 422

0x11 8400 RISCDBG0 . . . . . . . . . . . 422

0x11 8404 RISCDBG1 . . . . . . . . . . . 423

0x11 8408 RISCDBG2 . . . . . . . . . . . 423

0x11 840C RISCDBG3 . . . . . . . . . . . 423

0x11 8410 RISCDBG4 . . . . . . . . . . . 423

0x11 8414 RISCDBG5 . . . . . . . . . . . 423

0x11 8418 RISCDBG6 . . . . . . . . . . . 423

0x11 841C RISCDBG7 . . . . . . . . . . . 423

0x11 8420 RISCDBG8 . . . . . . . . . . . 423

0x11 8424 RISCDBG9 . . . . . . . . . . . 423

0x11 8428 RISCDBG10 . . . . . . . . . . 423

0x11 842C RISCDBG11 . . . . . . . . . . 424

0x11 8430 RISCCTL . . . . . . . . . . . . 424

0x11 8434 HSFCTL . . . . . . . . . . . . . 424

0x11 8600 + n*8 KEYnEVN0 (n = 0 to F) . 424 0x11 8604 + n*8 KEYnEVN1 (n = 0 to F) . 424 0x11 8680 + n*8 KEYnODD0 (n = 0 to F) . 424 0x11 8684 + n*8 KEYnODD1 (n = 0 to F) . 424

0x11 8700 M2SYSKEY0 . . . . . . . . . 424

0x11 8704 M2SYSKEY1 . . . . . . . . . 424

0x11 8708 M2SYSKEY2 . . . . . . . . . 425

0x11 870C M2SYSKEY3 . . . . . . . . . 425

0x11 8710 M2SYSKEY4 . . . . . . . . . 425

0x11 8714 M2SYSKEY5 . . . . . . . . . 425

0x11 8718 M2SYSKEY6 . . . . . . . . . 425

0x11 871C M2SYSKEY7 . . . . . . . . . 425

0x11 8720 CPKEYEVEN0 . . . . . . . . 425

0x11 8724 CPKEYEVEN1 . . . . . . . . 425

0x11 8728 CPKEYODD0 . . . . . . . . . 425

0x11 872C CPKEYODD1 . . . . . . . . . 425

0x11 8730 DSCIVCBC0 . . . . . . . . . . 425

0x11 8734 DSCIVCBC1 . . . . . . . . . . 425

0x11 8738 DSCIVOFB0 . . . . . . . . . . 425

0x11 873C DSCIVOFB1 . . . . . . . . . . 425

0x11 8740 CPIVCBC0 . . . . . . . . . . . 425

0x11 8744 CPIVCBC1 . . . . . . . . . . . 425

0x11 8748 CPIVOFB0 . . . . . . . . . . . 425

0x11 874C CPIVOFB1 . . . . . . . . . . . 425

0x11 8750 MODEPAD . . . . . . . . . . . 426

0x11 8C00 MSPRST . . . . . . . . . . . . 427

0x11 8E00—8F7C DQATTR . . . . . . . . . . . . 427

0x11 8FE0 STB_MSPINTST . . . . . . 428

0x11 8FE4 STB_MSPINTENA . . . . . 428

0x11 8FE8 STB_MSPINTCLR . . . . . 429

0x11 8FEC STB_MSPINTSET . . . . . 429

0x11 8FFC MODULEID . . . . . . . . . . 429

MSP 2 Registers (Rev 0.4)

0x12 0000—017C DQHDPTR . . . . . . . . . . . . 429

0x12 01A0 DQISTAT2 . . . . . . . . . . . . 430

Preliminary Rev. 02 — July 22 2004 xxv

0x12 01A4 DQISTAT1 . . . . . . . . . . . 430

0x12 01A8 DQISTAT0 . . . . . . . . . . . 430

Page 27

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PNX8550

0x12 01BC DQCTL . . . . . . . . . . . . . . 430

0x12 0200 FRMRCTL . . . . . . . . . . . . 430

0x12 0204 FRMRSYNC . . . . . . . . . . 431

0x12 0208 PIDMASK . . . . . . . . . . . . 432

0x12 020C PIDCTL . . . . . . . . . . . . . . 432

0x12 0210 PEAKVAL . . . . . . . . . . . . 433

0x0214 DACDATA . . . . . . . . . . . . 433

0x0218 DACCTL . . . . . . . . . . . . . 433

0x12 021C PCRREG0 . . . . . . . . . . . . 433

0x12 0220 PCRREG1 . . . . . . . . . . . . 433

0x12 0224 PCRREG2 . . . . . . . . . . . . 433

0x12 0228 STCREG0 . . . . . . . . . . . . 434

0x12 022C STCREG1 . . . . . . . . . . . . 434

0x12 0230 STCREG2 . . . . . . . . . . . . 434

0x12 0234 SCRREG0 . . . . . . . . . . . . 434

0x12 0238 SCRREG1 . . . . . . . . . . . . 434

0x12 023C SCRREG2 . . . . . . . . . . . . 434

0x12 0240 ACTSTCREG0 . . . . . . . . 434

0x12 0244 ACTSTCREG1 . . . . . . . . 435

0x12 0248 ACTSTCREG2 . . . . . . . . 435

0x12 024C TIMER1_LO . . . . . . . . . . . 435

0x12 0250 TIMER1_HI . . . . . . . . . . . 435

0x12 0254 TIMER2_LO . . . . . . . . . . . 435

0x12 0258 TIMER2_HI . . . . . . . . . . . 436

0x12 025C DSS_BITRATE . . . . . . . . 436

0x12 0260 FRMR_PACKSIZE . . . . . 436

0x12 0280 DMA_CMD0 . . . . . . . . . . 436

0x12 0284 SRC_ADDR0 . . . . . . . . . . 436

0x12 0288 DST_ADDR0 . . . . . . . . . . 437

0x12 028C LL_PTR0 . . . . . . . . . . . . . 437

0x12 0290 PACKET_SIZE0 . . . . . . . 437

0x12 0294 PDMA0_CTRL . . . . . . . . . 437

0x12 0298 PDMA0_STATUS . . . . . . 437

0x12 029C PDMA0_DELIVERY_DELAY .

0x12 02A0 TS_COUNTER0 . . . . . . . 438

0x12 02A4 DMA_CMD1 Same as

0x12 02A8 SRC_ADDR1 . . . . . . . . . . 438

0x12 02AC DST_ADDR1 . . . . . . . . . . 439

0x12 02B0 LL_PTR1 . . . . . . . . . . . . . 439

0x12 02B4 PACKET_SIZE1 . . . . . . . 439

0x12 02B8 PDMA1_CTRL . . . . . . . . . 439

0x12 02BC PDMA1_STATUS . . . . . . 439

0x12 02C0 PDMA1_DELIVERY_DELAY .

0x12 02C4 TS_COUNTER1 . . . . . . . 440

0x12 02CC PDMA_TIMEOUT . . . . . . 440

0x12 02D4 TSC_ENA . . . . . . . . . . . . 440

438

Channel0 . . . . . . . . . . . . . 438

440

0x12 02D8 TSC_ENB . . . . . . . . . . . . 440

0x12 0300—03FC PIDTABLE . . . . . . . . . . . 440

0x12 0400 RISCDBG0 . . . . . . . . . . . 440

0x12 0404 RISCDBG1 . . . . . . . . . . . 441

0x12 0408 RISCDBG2 . . . . . . . . . . . 441

0x12 040C RISCDBG3 . . . . . . . . . . . 441

0x12 0410 RISCDBG4 . . . . . . . . . . . 441

0x12 0414 RISCDBG5 . . . . . . . . . . . 441

0x12 0418 RISCDBG6 . . . . . . . . . . . 441

0x12 041C RISCDBG7 . . . . . . . . . . . 441

0x12 0420 RISCDBG8 . . . . . . . . . . . 441

0x12 0424 RISCDBG9 . . . . . . . . . . . 441

0x12 0428 RISCDBG10 . . . . . . . . . . 441

0x12 042C RISCDBG11 . . . . . . . . . . 442

0x12 0430 RISCCTL . . . . . . . . . . . . 442

0x12 0434 HSFCTL . . . . . . . . . . . . . 442

0x12 0600 + n*8 KEYnEVN0 (n = 0 to F) . 442 0x12 0604 + n*8 KEYnEVN1 (n = 0 to F) . 442 0x12 0680 + n*8 KEYnODD0 (n = 0 to F) . 442 0x12 0684 + n*8 KEYnODD1 (n = 0 to F) . 442

0x12 0700 M2SYSKEY0 . . . . . . . . . 442

0x12 0704 M2SYSKEY1 . . . . . . . . . 442

0x12 0708 M2SYSKEY2 . . . . . . . . . 443

0x12 070C M2SYSKEY3 . . . . . . . . . 443

0x12 0710 M2SYSKEY4 . . . . . . . . . 443

0x12 0714 M2SYSKEY5 . . . . . . . . . 443

0x12 0718 M2SYSKEY6 . . . . . . . . . 443

0x12 071C M2SYSKEY7 . . . . . . . . . 443

0x12 0720 CPKEYEVEN0 . . . . . . . . 443

0x12 0724 CPKEYEVEN1 . . . . . . . . 443

0x12 0728 CPKEYODD0 . . . . . . . . . 443

0x12 072C CPKEYODD1 . . . . . . . . . 443

0x12 0730 DSCIVCBC0 . . . . . . . . . . 443

0x12 0734 DSCIVCBC1 . . . . . . . . . . 443

0x12 0738 DSCIVOFB0 . . . . . . . . . . 443

0x12 073C DSCIVOFB1 . . . . . . . . . . 443

0x12 0740 CPIVCBC0 . . . . . . . . . . . 443

0x12 0744 CPIVCBC1 . . . . . . . . . . . 443

0x12 0748 CPIVOFB0 . . . . . . . . . . . 443

0x12 074C CPIVOFB1 . . . . . . . . . . . 443

0x12 0750 MODEPAD . . . . . . . . . . . 444

0x12 0C00 MSPRST . . . . . . . . . . . . 445

0x12 0E00—8F7C DQATTR . . . . . . . . . . . . 445

0x12 0FE0 STB_MSPINTST . . . . . . 446

0x12 0FE4 STB_MSPINTENA . . . . . 446

0x12 0FE8 STB_MSPINTCLR . . . . . 447

0x12 0FEC STB_MSPINTSET . . . . . 447

0x12 0FFC MODULEID . . . . . . . . . . 447

T-Default Slv

0x12 8FFC . . . . . . . . . . . . . . . . . . . . . 447

TM3260 MMIO Registers (Rev 1.01)

0x10_000C . . . . . . . . . . . . . . . . . . . . .447

0x10_0010 . . . . . . . . . . . . . . . . . . . . . 448

0x10_0014 . . . . . . . . . . . . . . . . . . . . . 449

0x10_0018 . . . . . . . . . . . . . . . . . . . . . 449

0x10_001C . . . . . . . . . . . . . . . . . . . . .449

0x10_0020 . . . . . . . . . . . . . . . . . . . . . 449

0x10_0030 . . . . . . . . . . . . . . . . . . . . . 450

0x10_0034 . . . . . . . . . . . . . . . . . . . . . 450

0x10_0038 . . . . . . . . . . . . . . . . . . . . . 450

0x10_003C . . . . . . . . . . . . . . . . . . . . .450

0x10_0040 . . . . . . . . . . . . . . . . . . . . . 451

0x10_0044 . . . . . . . . . . . . . . . . . . . . . 451

0x10_0048 . . . . . . . . . . . . . . . . . . . . . 451

0x10_004C . . . . . . . . . . . . . . . . . . . . .451

0x10_0050 . . . . . . . . . . . . . . . . . . . . . 451

0x10_0054 . . . . . . . . . . . . . . . . . . . . . 452

0x10_0108 . . . . . . . . . . . . . . . . . . . . . 452

0x10_0210 . . . . . . . . . . . . . . . . . . . . . 452

0x10_0214 . . . . . . . . . . . . . . . . . . . . . 452

0x10_0218 . . . . . . . . . . . . . . . . . . . . . 453

0x10_0500 . . . . . . . . . . . . . . . . . . . . . 453

0x10_0800 . . . . . . . . . . . . . . . . . . . . . 453

0x10_0810 . . . . . . . . . . . . . . . . . . . . . 453

Preliminary Rev. 02 — July 22 2004 xxvi

0x10_0814 . . . . . . . . . . . . . . . . . . . . 454

0x10_0818 . . . . . . . . . . . . . . . . . . . . 454

0x10_081C . . . . . . . . . . . . . . . . . . . . 454

0x10_0820 . . . . . . . . . . . . . . . . . . . . 454

0x10_0824 . . . . . . . . . . . . . . . . . . . . 454

0x10_0828 . . . . . . . . . . . . . . . . . . . . 455

0x10_0830 . . . . . . . . . . . . . . . . . . . . 455

0x10_083 . . . . . . . . . . . . . . . . . . . . 455

0x10_0838 . . . . . . . . . . . . . . . . . . . . 455

0x10_083C . . . . . . . . . . . . . . . . . . . . 456

0x10_0840 . . . . . . . . . . . . . . . . . . . . 456

0x10_0844 . . . . . . . . . . . . . . . . . . . . 456

0x10_0848 . . . . . . . . . . . . . . . . . . . . 456

0x10_0880+4n . . . . . . . . . . . . . . . . . . . . 456

0x10_0C00 . . . . . . . . . . . . . . . . . . . . 456

0x10_0C04 . . . . . . . . . . . . . . . . . . . . 456

0x10_0C08 . . . . . . . . . . . . . . . . . . . . 456

0x10_0C20 . . . . . . . . . . . . . . . . . . . . 457

0x10_0C24 . . . . . . . . . . . . . . . . . . . . 457

0x10_0C28 . . . . . . . . . . . . . . . . . . . . 457

0x10_0C40 . . . . . . . . . . . . . . . . . . . . 458

0x10_0C44 . . . . . . . . . . . . . . . . . . . . 458

0x10_0C48 . . . . . . . . . . . . . . . . . . . . 458

Page 28

Philips Semiconductors

PNX8550

0x10_0C60 . . . . . . . . . . . . . . . . . . . . .459

0x10_0C64 . . . . . . . . . . . . . . . . . . . . .459

0x10_0C68 . . . . . . . . . . . . . . . . . . . . .459

0x10_0FF8 . . . . . . . . . . . . . . . . . . . . . 460

0x10_0FFC . . . . . . . . . . . . . . . . . . . . . 460

0x10_1000 . . . . . . . . . . . . . . . . . . . . . 460

T-Default Slv

0x14 2FFC . . . . . . . . . . . . . . . . . . . . . 462

T-Default Slv

0x16 2FFC . . . . . . . . . . . . . . . . . . . . . 462

GIC_TM32_2 Registers (Rev 1.6.1)

0x17 0000 int_priority_0 . . . . . . . . . . 462

0x17 0004 int_priority_1 . . . . . . . . . . 463

0x17 0100 int_vector_0 . . . . . . . . . . . 463

0x17 0104 int_vector_1 . . . . . . . . . . . 464

0x17 0200 int_pending_1_31 . . . . . . 464

0x17 0204 int_pending_32_63 . . . . . 464

0x17 0208 int_pending_64_70 . . . . . 465

0x17 0300 int_features . . . . . . . . . . . 465

0x17 0404 int_request_reg_1 . . . . . . 465

0x17 0408 int_request_reg_2 . . . . . . 467

0x17 040C int_request_reg_3 . . . . . . 467

0x17 0410 int_request_reg_4 . . . . . . 467

0x17 0414 int_request_reg_5 . . . . . . 467

0x17 0418 int_request_reg_6 . . . . . . 467

0x17 041C int_request_reg_7 . . . . . . 467

0x17 0420 int_request_reg_8 . . . . . . 467

0x17 0424 int_request_reg_9 . . . . . . 467

0x17 0428 int_request_reg_10 . . . . . 467

0x17 042C int_request_reg_11 . . . . . 467

0x17 0430 int_request_reg_12 . . . . . 467

0x17 0434 int_request_reg_13 . . . . . 467

0x17 0438 int_request_reg_14 . . . . . 467

0x17 043C int_request_reg_15 . . . . . 467

0x17 0440 int_request_reg_16 . . . . . 468

0x17 0444 int_request_reg_17 . . . . . 468

0x17 0448 int_request_reg_18 . . . . . 468

0x17 044C int_request_reg_19 . . . . . 468

0x17 0450 int_request_reg_20 . . . . . 468

0x17 0454 int_request_reg_21 . . . . . 468

0x17 0458 int_request_reg_22 . . . . . 468

0x17 045C int_request_reg_23 . . . . . 468

0x17 0460 int_request_reg_24 . . . . . 468

0x17 0464 int_request_reg_25 . . . . . 468

0x17 0468 int_request_reg_26 . . . . . 468

0x17 046C int_request_reg_27 . . . . . 468

0x17 0470 int_request_reg_28 . . . . . 468

0x17 0474 int_request_reg_29 . . . . . 468

0x17 0478 int_request_reg_30 . . . . . 468

0x17 047C int_request_reg_31 . . . . . 468

0x17 0480 int_request_reg_32 . . . . . 468

0x10_1004 . . . . . . . . . . . . . . . . . . . . 461

0x10_1020 . . . . . . . . . . . . . . . . . . . . 461

0x10_1030 . . . . . . . . . . . . . . . . . . . . 461

0x10_1034 . . . . . . . . . . . . . . . . . . . . 461

0x10_1038 . . . . . . . . . . . . . . . . . . . . 461

0x10_103C . . . . . . . . . . . . . . . . . . . . 462

0x17 0484 int_request_reg_33 . . . . 468

0x17 0488 int_request_reg_34 . . . . 468

0x17 048C int_request_reg_35 . . . . 469

0x17 0490 int_request_reg_36 . . . . 469

0x17 0494 int_request_reg_37 . . . . 469

0x17 0498 int_request_reg_38 . . . . 469

0x17 049C int_request_reg_39 . . . . 469

0x17 04A0 int_request_reg_40 . . . . 469

0x17 04A4 int_request_reg_41 . . . . 469

0x17 04A8 int_request_reg_42 . . . . 469

0x17 04AC int_request_reg_43 . . . . 469

0x17 04B0 int_request_reg_44 . . . . 469

0x17 04B4 int_request_reg_45 . . . . 469

0x17 04B8 int_request_reg_46 . . . . 469

0x17 04BC int_request_reg_47 . . . . 469

0x17 04C0 int_request_reg_48 . . . . 469

0x17 04C4 int_request_reg_49 . . . . 469

0x17 04C8 int_request_reg_50 . . . . 469

0x17 04CC int_request_reg_51 . . . . 469

0x17 04D0 int_request_reg_52 . . . . 469

0x17 04D4 int_request_reg_53 . . . . 470

0x17 04D8 int_request_reg_54 . . . . 470

0x17 04DC int_request_reg_55 . . . . 470

0x17 04E0 int_request_reg_56 . . . . 470

0x17 04E4 int_request_reg_57 . . . . 470

0x17 04E8 int_request_reg_58 . . . . 470

0x17 04EC int_request_reg_59 . . . . 470

0x17 04F0 int_request_reg_60 . . . . 470

0x17 04F4 int_request_reg_61 . . . . 470

0x17 04F8 int_request_reg_62 . . . . 470

0x17 04FC int_request_reg_63 . . . . 470

0x17 0500 int_request_reg_64 . . . . 470

0x17 0504 int_request_reg_65 . . . . 470

0x17 0508 int_request_reg_66 . . . . 470

0x17 050C int_request_reg_67 . . . . 470

0x17 0510 int_request_reg_68 . . . . 470

0x17 0514 int_request_reg_69 . . . . 470

0x17 0518 int_request_reg_70 . . . . 470

0x17 0FFC MOD_ID . . . . . . . . . . . . . 471

IPC_TM32_1 Registers (Rev 1.6.1)

0x17 1000 int_priority_0 . . . . . . . . . . 471

0x17 1004 int_priority_1 . . . . . . . . . . 471

0x17 1100 int_vector_0 . . . . . . . . . . . 472

0x17 1104 int_vector_1 . . . . . . . . . . . 472

0x17 1200 int_pending_1_8 . . . . . . . 472

0x17 1300 int_features . . . . . . . . . . . 473

0x17 1404 Message Register_1 . . . . 473

0x17 1408 Message Register_2 . . . 474 0x17 140C Message Register_3 . . . 474 0x17 1410 Message Register_4 . . . 475 0x17 1414 Message Register_5 . . . 475 0x17 1418 Message Register_6 . . . 475 0x17 141C Message Register_7 . . . 475 0x17 1420 Message Register_8 . . . 475

IPC_TM32_2 Registers (Rev 1.6.1)

0x17 2000 int_priority_0 . . . . . . . . . . 475

0x17 2004 int_priority_1 . . . . . . . . . . 475

0x17 2100 int_vector_0 . . . . . . . . . . . 476

0x17 2104 int_vector_1 . . . . . . . . . . . 476

0x17 2200 int_pending_1_8 . . . . . . . 476

0x17 2300 int_features . . . . . . . . . . . 477

0x17 2404 Message Register_1 . . . . 477

Preliminary Rev. 02 — July 22 2004 xxvii

0x17 2408 Message Register_2 . . . 478 0x17 240C Message Register_3 . . . 478 0x17 2410 Message Register_4 . . . 479 0x17 2414 Message Register_5 . . . 479 0x17 2418 Message Register_6 . . . 479 0x17 241C Message Register_7 . . . 479 0x17 2420 Message Register_8 . . . 479

Page 29

Philips Semiconductors

Vertical Peaking (VPK) Registers (Rev 0.15)

0x17 3000 FIL_PAR0 . . . . . . . . . . . . 479

0x17 3004 FIL_PAR1 . . . . . . . . . . . . 479

0x17 3008 VPK_PAR . . . . . . . . . . . . 479

0x17 300C VOUT_FORMAT . . . . . . .479

0x17 3010 VPK_CTRL . . . . . . . . . . . 480

0x17 3014 DATA_SIZE

0x17 3018 FRM_SIZE . . . . . . . . . . . . 480

0x17 301C DEMO_WIN_STRT . . . . . 480

0x17 3020 DEMO_WIN_END . . . . . . 481

0x17 3024 CROP_WIN_STRT . . . . . 481

0x17 3028 CROP_WIN_STRT . . . . . 481

0x17 302C PFU_BLK_SIZE . . . . . . . . 481

0x17 3030 PFU_BASE . . . . . . . . . . . 481

Memory Based Scaler2 (MBS2) Registers (Rev 0.3)

0x17 4000 MBS Mode Control . . . . . 482

0x17 4040 Task FIFO . . . . . . . . . . . . 484

0x17 4044 Task Status 1 . . . . . . . . . . 484

0x17 4048 Task Status 2 . . . . . . . . . . 484

0x17 4100 Input Format . . . . . . . . . . 484

0x17 4104 Source Window Size . . . . 485

0x17 4108 Variable Format Register . 485 0x17 4140 Source Base Address #1 . 486

0x17 4144 Source Line Pitch #1 . . . . 486

0x17 4148 Source Base Address #2 . 486

0x17 414C Source Line Pitch #2 . . . . 486

0x17 4150 Source Base Address #3 . 486 0x17 4154 Source Base Address #4 . 486 0x17 4158 Source Base Address #5 . 486 0x17 415C Source Base Address #6 . 486

0x17 4200 Initial Zoom . . . . . . . . . . . 487

0x17 4204 Phase Control . . . . . . . . . 487

0x17 4208 Initial Zoom delta . . . . . . . 488

0x17 420C Zoom delta change . . . . . 488

0x17 4220 Color space matrix coefficients

0x17 4224 Color space matrix coefficients

0x17 4228 Color space matrix coefficients

0x17 422C Color space matrix offset

0x17 4230 Color space matrix offset

C00 - C02 . . . . . . . . . . . . 488

C10 - C12 . . . . . . . . . . . . 488

C20 - C22 . . . . . . . . . . . . 488

coefficients D0 - D2 . . . . . 489

coefficients E0 - E2 . . . . . 489

1 . . . . . . . . . . . . . 480

PNX8550

0x17 3034 PFU_PITCH . . . . . . . . . . 481

0x17 3038 PSU_BASE_Y . . . . . . . . 481

0x17 303C PSU_PITCH_Y . . . . . . . . 481

0x17 3040 PSU_BASE_UV . . . . . . . 481

0x17 3044 PSU_PITCH_UV . . . . . . 481

0x17 3048 OP_LINE_CTR . . . . . . . . 481

0x17 3FE0 INT_STATUS . . . . . . . . . 482

0x17 3FE4 INT_ENABLE . . . . . . . . . 482

0x17 3FE8 INT_CLEAR 0x17 3FEC INT_SET

0x17 3FF4 POWERDOWN . . . . . . . 482

0x17 3FFC MODULE_ID . . . . . . . . . 482

0x17 4240 Initial Zoom . . . . . . . . . . . 489

0x17 4244 Phase Control . . . . . . . . 490

0x17 4248 Initial Zoom delta . . . . . . 490

0x17 424C Zoom delta change . . . . 490

0x17 4280 Color Key Control . . . . . . 490

0x17 4284 Color Key Components . 491 0x17 4300 Video Output Format . . . 491

0x17 4304 Target Window Size . . . . 492

0x17 4340 Target Base Address #1 492

0x17 4344 Target Line Pitch #1 . . . . 492

0x17 4348 Target Base Address #2 493

0x17 434C Target Line Pitch #2 . . . . 493

0x17 4350 Target Base Address #3 493 0x17 4354 Target Base Address #4 493 0x17 4358 Target Base Address #5 493 0x17 435C Target Base Address #6 493 0x17 4400—47FC Color Look Up Table . . . 493 0x17 4800—49FC Coefficient Table #1 Taps 0-5

0x17 4A00—4BFC Coefficient Table #2 Taps 0-5

0x17 4C00—4DFC Coefficient Table #3 Taps 0-5

0x17 4FE0 Interrupt Status . . . . . . . . 494

0x17 4FE4 Interrupt Enable . . . . . . . 495

0x17 4FE8 Interrupt Clear . . . . . . . . 495

0x17 4FEC Interrupt Set . . . . . . . . . . 495

0x17 4FFC Module ID . . . . . . . . . . . . 495

(Horizontal) . . . . . . . . . . . 493

(Vertical - Luma) . . . . . . . 494

(Vertical - Chroma) . . . . . 494

2 . . . . . . . . . . . . . 482

3 . . . . . . . . . . . . . . . . 482

SPDIF IN 2 Registers (Rev 2.1.5)

0x17 5000 SPDI_CTL . . . . . . . . . . . . 496

0x17 5004 SPDI_BASE1 . . . . . . . . . . 497

0x17 5008 SPDI_BASE2 . . . . . . . . . . 497

0x17 500C SPDI_SIZE . . . . . . . . . . . 497

0x17 5010 SPDI_BPTR . . . . . . . . . . . 497

0x17 5014 SPDI_SMPMASK . . . . . . 497

0x17 5018 SPDI_CBITS1 . . . . . . . . . 498

0x17 501C SPDI_CBITS2 . . . . . . . . . 498

0x17 5020 SPDI_CBITS3 . . . . . . . . . 498

0x17 5024 SPDI_CBITS4 . . . . . . . . . 498

0x17 5028 SPDI_CBITS5 . . . . . . . . . 498

0x17 502C SPDI_CBITS6 . . . . . . . . . 498

0x17 5030 SPDI_UBITS1 . . . . . . . . . 498

0x17 5034 SPDI_UBITS2 . . . . . . . . 498

0x17 5038 SPDI_UBITS3 . . . . . . . . 498

0x17 503C SPDI_UBITS4 . . . . . . . . 499

0x17 5040 SPDI_UBITS5 . . . . . . . . 499

0x17 5044 SPDI_UBITS6 . . . . . . . . 499

0x17 5048—5FDC Reserved . . . . . . . . . . . . 499

0x17 5FE0 SPDI_STATUS . . . . . . . . 499

0x17 5FE4 SPDI_INTEN . . . . . . . . . 500

0x17 5FE8 SPDI_INTCLR . . . . . . . . 501

0x17 5FEC SPDI_INTSET . . . . . . . . 501

0x17 5FF4 SPDI_PWR_DWN . . . . . 502

0x17 5FFC SPDI_MODULE_ID . . . . 502

T-Default Slv

0x17 6FFC . . . . . . . . . . . . . . . . . . . . . 502

Tunnel Registers (Rev 0.33)

0x17 F000 CTL12 IN Receive Status

0x17 F004 CTL12 IN Packet Status

0x17 F008 CTL12 IN Packet Register 503 0x17 F00C CTL12 IN Configuration

0x17 F010 CTL12 IN Idle Packet Status

Preliminary Rev. 02 — July 22 2004 xxviii

0x17 F014 CTL12 IN TUN_TX_DATA

0x17 F018 CTL12 IN TUN_RX_DATA

0x17 FFF4 CTL12 IN Power Down

0x17 FFFC CTL12 IN Module ID Reg. 504

Page 30

PNX8550

Rev. 02 — July 22 2004 Preliminary

Aperture Map

Table 1: Aperture Map

Aperture

Status

MDCS Bus

M-Default Slv 0x00 0000 248K 4

GIC_MIPS 0x03 E000 4K 4

IPC_MIPS 0x03 F000 4K 12

PCI/XIO 0x04 0000 4K 16

EJTAG DMA 0x04 1000 4K 36

M-Default Slv 0x04 2000 4K 37

ISO UART1 0x04 3000 4K 37

ISO UART2 0x04 4000 4K 49

IIC1 0x04 5000 4K 61

IIC2 0x04 6000 4K 66

Clocks 0x04 7000 4K 70

USB 0x04 8000 4K 91

M-Default Slv 0x04 9000 4K 98

UART1 0x04 A000 4K 98

UART2 0x04 B000 4K 102

UART3 0x04 C000 4K 107

Global Regs 2 0x04 D000 4K 110

MDCSC 0x04 E000 4K 120

D2D 0x04 F000 68K 122

Reset 0x06 0000 4K 130

TMDBG1 0x06 1000 4K 131

TMDBG2 0x06 2000 4K 132

Global Regs 1 0x06 3000 4K 133

PMAN Arbiter 0x06 4000 4K 137

DDR SDRAM Controller 0x06 5000 4K 139

PMAN Security 0x06 6000 4K 147

Memory Bandwidth Monitor 0x06 7000 4K 156

MDCS Security 0x06 8000 4K 159

Start

Aperture Size Module Name

Page Reference

Page 31

Philips Semiconductors

PNX8550

Table 1: Aperture Map …Continued

Aperture

Status

IIC 3 0x06 9000 4K 160

M-Default Slv 0x06 9000 604K 163

Aperture End 0x0F FFFF total size = 1MB 163

TDCS Bus

T-Default Slv 0x10 0000 8K 163

GIC-TM32_1 0x10 2000 4K 163

TDCSC 0x10 3000 4K 172

GPIO 0x10 4000 4K 175

VMPG 0x10 5000 4K 199

VIP1 0x10 6000 4K 210

VIP2 0x10 7000 4K 223

VLD 0x10 8000 4K 236

SPDO 0x10 9000 4K 239

SPDI 0x10 A000 4K 241

DVDD 0x10 B000 4K 247

MBS1 0x10 C000 4K 248

QTNR 0x10 D000 4K 269

QVCP1 0x10 E000 4K 282

QVCP2 0x10 F000 4K 327

AO1 0x11 0000 4K 370

AI1 0x11 1000 4K 374

AO2 0x11 2000 4K 378

AI2 0x11 3000 4K 381

EDMA 0x11 4000 4K 385

TDCS Security 0x11 5000 4K 397

TSDMA 0x11 6000 4K 397

DENC 0x11 7000 4K 402

MSP1 0x11 8000 32K 412

MSP2 0x12 0000 32K 429

T-Default Slv 0x12 8000 32K 447

TM3260 MMIO Registers 0x13 0000 64K 447

T Default Slv 0x14 2000 56K 462

T Default Slv 0x16 2000 56K 462

GIC_TM32_2 0x17 0000 4K 462

IPC_TM32_1 0x17 1000 4K 471

IPC_TM32_2 0x17 2000 4K 475

VPK 0x17 3000 4k 479

MBS2 0x17 4000 4k 482

Start

Aperture Size Module Name

Page Reference

Preliminary Rev. 02 — July 22 2004 1 - 2

Page 32

Philips Semiconductors

PNX8550

Table 1: Aperture Map …Continued

Aperture

Status

SPDI2 0x17 5000 4k 496

T-Default Slv 0x17 6000 36K 502

Tunnel Configuration*** 0x17 F000 4K 502

Start

Aperture Size Module Name

Page Reference

* This aperture is the TM3260 internal view of the TM3260 registers. Each TM only sees its own registers here i.e., Viper2 aperture 14 0000 maps to TM1 10 0000. Viper2 aperture 16 0000 maps to TM2 10 0000.

** Each TriMedia sees the lower 64 K of the MMIO aperture as cache i.e., Viper2 aperture of 13 0000 maps for TM1 00 0000. Viper2 aperture of 15 0000 maps to TM2 00 0000

*** The tunnel configuration sets its aperture size from 4 K to 514 K if the tunnel is not in use.

Preliminary Rev. 02 — July 22 2004 1 - 3

Page 33

Philips Semiconductors

Table 2: M-Default Slv

Bit Symbol Access Val ue Description

Offset 0x00 0FFC

31:16 MOD_ID R 0x0124 Module ID Number

15:12 REV_MAJOR R 0 Major revision

11:8 REV_MINOR R 0 Minor revision

7:0 APP_SIZE R 3D Aperture size is 0 = 248 kB.

Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

INT_PRIORITYMASK_{0,1} Registers

Offset 0x03 E000 int_priority_0

31:4 Reserved R 0

3:0 priority_limiter_0 R/W 0 Priority Limiter:

This variable determines a priority threshold that incoming interrupt requests must exceed to trigger interrupt requests towards processor and power management controller.

Legal PRIORITY_LIMITER values are 0... F; other values are reserved and lead to undefined behavior.

PRIORITY_LIMITER = 0: Incoming interrupt requests with priority >0 can trigger interrupt requests towards processor.

PRIORITY_LIMITER = n: Only interrupt requests at a priority level above n can trigger interrupt requests towards processor.

...

PRIORITY_LIMITER = F: No incoming interrupt requests can trigger interrupt requests towards processor.

High order bits not required for PRIORITY_LIMITER encoding are read-only 0.

Offset 0x03 E004 int_priority_1

31:4 Reserved R 0

PNX8550

Preliminary Rev. 02 — July 22 2004 1 - 4

Page 34

Philips Semiconductors

PNX8550

Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

3:0 priority_limiter_1 R/W 0 Priority Limiter:

INT_VECTOR_{0,1} Registers

Offset 0x03 E100 int_vector_0

31:11 table_addr R/W 0 Table start address: indicates the lower address boundary of a

10:3 Index R 0 Index: indicates the intreq line number of the interrupt request to be

2:0 Reserved R 0

Offset 0x03 E104 int_vector_1

31:11 table_addr R/W 0 Table start address: indicates the lower address boundary of a 2048

10:3 Index R 0 Index: indicates the intreq line number of the interrupt request to be

…Continued

This variable determines a priority threshold that incoming interrupt requests must exceed to trigger interrupt requests towards processor.

Legal PRIORITY_LIMITER values are 0... F; other values are reserved and lead to undefined behavior.

PRIORITY_LIMITER = 0: Incoming interrupt requests with priority >0 can trigger interrupt requests towards processor.

PRIORITY_LIMITER = n: Only interrupt requests at a priority level above n can trigger interrupt requests towards processor.

...

PRIORITY_LIMITER = F: No incoming interrupt requests can trigger interrupt requests towards processor.

High order bits not required for PRIORITY_LIMITER encoding are read-only 0.

2048-byte aligned interrupt vector table in memory.

served by the processor:

INDEX = 0: No interrupt request to be served

INDEX = 1: Serve interrupt request at input intreq1

INDEX = 2: Serve interrupt request at input intreq2

...

INDEX = 69: Serve interrupt request at input intreq69

byte aligned interrupt vector table in memory.

served by the processor:

INDEX = 0: No interrupt request to be served

INDEX = 1: Serve interrupt request at input intreq1

INDEX = 2: Serve interrupt request at input intreq2

...

INDEX = 69: Serve interrupt request at input intreq69

Preliminary Rev. 02 — July 22 2004 1 - 5

Page 35

Philips Semiconductors

PNX8550

Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

2:0 Reserved R 0

INT_PENDING Registers

Offset 0x03 E200 int_pending_1_31

31:1 pending[i] R 0 Pending interrupt request:

0 Reserved

Offset 0x03 E204 int_pending_32_63

31:0 pending[i] R 0 Pending interrupt request:

Offset 0x03 E208 int_pending_64_70

31:7 Reserved

6:0 pending[i] R 0 Pending interrupt request:

INT_FEATURES Register

Offset 0x03 E300 int_features

31:22 0 R -

21:16 Targets R 1 Number of interrupt targets supported (minus one)

15:8 Priority Limit R F Number of priority levels supported (minus one)

7:0 Request Input number R 50 Number of interrupt request inputs (hex)

…Continued

This variable reflects the state of the intreq[i] line (if needed, converted to active high) OR’ed by the state of the local soft-ware interrupt request variable at the time the register is read. Note that the pending variables are also reflected by the INT_REQUEST_* registers individually present for each interrupt request input.

PENDING = 0: no interrupt request PENDING = 1: interrupt request is pending

PENDING = 0:no interrupt request PENDING = 1: interrupt request is pending

Preliminary Rev. 02 — July 22 2004 1 - 6

Page 36

Philips Semiconductors

PNX8550

Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

INT_REQUEST_{1...N} Registers

Offset 0x03 E404 int_request_reg_1

Inter-Processor Communication (IPC) MIPS Register, Target 0

31 pending R 0 Pending interrupt request:

30 SET_SWINT W 0 Set software interrupt request

29 CLR_SWINT W 0 Clear software interrupt request:

28 WE_PRIORITY_LEVEL W x Write Enable PRIORITY_LEVEL

27 WE_TARGET W x Write Enable TARGET

26 WE_ENABLE W x Write Enable ENABLE

25 WE_ACTIVE_LOW W x Write Enable ACTIVE_LOW

24:18 Reserved R 0

…Continued

This variable reflects the state of the intreq line (if needed, converted to active high) OR’ed by the state of the local soft-ware interrupt request variable at the time the register is read. Note that the PENDING variable is also visible from the INT_PENDING_* registers.

PENDING = 0:no interrupt request PENDING = 1: interrupt request pending

SET_SW_INT = 0 (write): no effect on the state of the local software interrupt request variable SET_SWINT = 1 (write): set the state of the local software interrupt request variable to ‘1’ SET_SWINT is always reads as 0

CLR_SWINT = 0 (write): no effect on the state of the local software interrupt request variable CLR_SWINT = 1 (write): clear the state of the local software interrupt request variable to ‘0’ CLR_SWINT is always read as 0

WE_PRIORITY_LEVEL = 0 (write): no change of PRIORITY_LEVEL variable state WE_PRIORITY_LEVEL = 1 (write): PRIORITY_LEVEL variable state may be changed. WE_PRIORITY_LEVEL is always read as 0. This bit is self-clearing.

WE_TARGET = 0 (write): no change of TARGET variable state WE_TARGET = 1 (write): TARGET variable state may be changed. WE_TARGET is always read as 0. This bit is self-clearing.

WE_ENABLE = 0 (write): no change of ENABLE variable state WE_ENABLE = 1 (write): ENABLE variable state may be changed. WE_ENABLE is always read as 0. This bit is self-clearing.

WE_ACTIVE_LOW = 0 (write): no change of ACTIVE_LOW variable state WE_ACTIVE_LOW = 1 (write): ACTIVE_LOW variable state may be changed. WE_ACTIVE_LOW is always read as 0. This bit is self-clearing.

Preliminary Rev. 02 — July 22 2004 1 - 7

Page 37

Philips Semiconductors

PNX8550

Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

17 active_type R/W 0 Active Low:

16 enable_type R/W 0 Enable interrupt request:

15:9 Reserved R

8 target_type R/W 0 Interrupt target:

7:4 Reserved

3:0 priority_level R/W 0 Priority level:

Offset 0x03 E408 int_request_reg_2

IPC TM32-1register, Target 1. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E40C int_request_reg_3

IPC TM32-2 register, Target 1. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E410 int_request_reg_4

Reserved

Offset 0x03 E414 int_request_reg_5

Universal Serial Bus Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

…Continued

This variable selects the polarity of the interrupt request input signal. See also WE_ACTIVE_LOW. ACTIVE_LOW = 1: the intreq signal is interpreted as active low. ACTIVE_LOW = 0: the intreq signal is interpreted as active high.

This variable controls whether an interrupt request is enabled for further processing by the interrupt controller. See also WE_ENABLE. ENABLE = 0: the interrupt request is discarded. It cannot cause a processor or power management interrupt request. ENABLE = 1: the interrupt request may cause a processor or power management interrupt request when further conditions for this become true.

This variable defines the interrupt target of an interrupt request. Legal values are 0... 1; other values are reserved and lead to undefined behavior. See also WE_TARGET. TARGET = 0: the interrupt request will lead to a processor interrupt request 0 (cpuint0). TARGET = 1: the interrupt request will lead to a processor interrupt request 1 (cpuint1). High order bits are not required for TARGET encoding as they are read-only 0.

This variable determines the priority level of the interrupt request. Legal values are 0... F; other values are reserved and lead to undefined behavior. See also WE_PRIORITY_LEVEL. PRIORITY_LEVEL = 0: the interrupt request has priority level 0 (masked); it is ignored. PRIORITY_LEVEL = 1: the interrupt request has priority level 1 (lowest).

...

PRIORITY_LEVEL = F: the interrupt request has priority level F (highest). High order bits not required for PRIORITY_LEVEL encoding; are read-only 0.

Preliminary Rev. 02 — July 22 2004 1 - 8

Page 38

Philips Semiconductors

PNX8550

Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

Offset 0x03 E418 int_request_reg_6

GPIO Interrupt Event Queue 0 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E41C int_request_reg_7

GPIO Interrupt Event Queue 1 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E420 int_request_reg_8

GPIO Interrupt Event Queue 2 register. This register is identical to the int_request_1 register (Offset 0x03 E404.)

Offset 0x03 E424 int_request_reg_9

GPIO Interrupt Event Queue 3 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E428 int_request_reg_10

GPIO Interrupt Event Queue 4 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E42C int_request_reg_11

GPIO Interrupt Event Queue 5 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E430 int_request_reg_12

Reserved

Offset 0x03 E434 int_request_reg_13

Quality Video Composition Processor Interrupt 1 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E438 int_request_reg_14

Quality Video Composition Processor Interrupt 2 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E43C int_request_reg_15

I2C 1 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E440 int_request_reg_16

I2C 2 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E444 int_request_reg_17

ISO UART 1 (Smartcard) Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E448 int_request_reg_18

ISO UART 2 (Smartcard) Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E44C int_request_reg_19

UART 1 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E450 int_request_reg_20

UART 2 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E454 int_request_reg_21

QTNR register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E458 int_request_reg_22

Reserved

Offset 0x03 E45C int_request_reg_23

TDCS bus controller interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E460 int_request_reg_24

MDCS bus controller interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

…Continued

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Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

Offset 0x03 E464 int_request_reg_25

Reserved

Offset 0x03 E468 int_request_reg_26

2D Drawing Engine Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E46C int_request_reg_27

Memory Based Scaler 1 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E470 int_request_reg_28

Video MPEG interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E474 int_request_reg_29

Video Input Processor 1 interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E478 int_request_reg_30

Video Input Processor 2 interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E47C int_request_reg_31

Sony Philips Digital Input Interrupt (SPDI) register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E480 int_request_reg_32

Sony Philips Digital Output Interrupt (SPDO) register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E484 int_request_reg_33

Audio Input 1 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E488 int_request_reg_34

Audio Output 1 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E48C int_request_reg_35

Audio Input 2 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E490 int_request_reg_36

Audio Output 2 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E494 int_request_reg_37

Memory Based Scaler 2 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E498 int_request_reg_38

VPK Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E49C int_request_reg_39

MPEG System Processor 1 MIPS Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4A0 int_request_reg_40

MPEG System Processor 1 TriMedia Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4A4 int_request_reg_41

MPEG System Processor 2 MIPS Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4A8 int_request_reg_42

MPEG System Processor 2 TriMedia Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

…Continued

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Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

Offset 0x03 E4AC int_request_reg_43

Transport Stream DMA Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4B0 int_request_reg_44

EDMA Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4B4 int_request_reg_45

TriMedia Debug 1 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4B8 int_request_reg_46

TriMedia Debug 2 Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4BC int_request_reg_47

PCI INTA interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4C0 int_request_reg_48

Clock module Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4C4 int_request_reg_49

PCI-XIO module interrupt PCI register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4C8 int_request_reg_50

PCI-XIO module interrupt DMA register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4CC int_request_reg_51

PCI-XIO module interrupt GPPM register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4D0 int_request_reg_52

PCI-XIO module interrupt GPXIO register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4D4 int_request_reg_53

DVD/CSS Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4D8 int_request_reg_54

VLD Interrupt register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4DC int_request_reg_55

GPIO TSU 7:0 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4E0 int_request_reg_56

GPIO TSU 15:8 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4E4 int_request_reg_57

GPIO CTU + IR. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4E8 int_request_reg_58

GPIO Signal Mux 0 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4EC int_request_reg_59

GPIO Signal Mux 1 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4F0 int_request_reg_60

GPIO Signal Mux 2 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4F4 int_request_reg_61

GPIO Signal Mux 3 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

…Continued

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Table 3: MGIC Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

Offset 0x03 E4F8 int_request_reg_62

GPIO Signal Mux 4 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E4FC int_request_reg_63

GPIO Signal Mux 5 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E500 int_request_reg_64

GPIO Signal Mux 6 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E504 int_request_reg_65

GPIO Signal Mux 7 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E508 int_request_reg_66

PMAN Security register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E50C int_request_reg_67

I2C 3 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E510 int_request_reg_68

Reserved

Offset 0x03 E514 int_request_reg_69

SPDI 2 register. This register is identical to the int_request_1 register (Offset 0x03 E404).

Offset 0x03 E518 int_request_reg_70

I2C 4. This register is identical to the int_request_1 register (Offset 0x03 E404).

INT_MOD_ID Register

Offset 0x03 EFFC MOD_ID

31:16 ID R 1106h Identification number:

15:12 MAJOR_REV R 0h Major revision of module implementation Note that there is no

11:8 MINOR_REV R 0 Minor revision of module implementation, starting at 0. There is

7:0 APERTURE_SIZE R 00h 4 kB address aperture

…Continued

Unique module identifier (assigned by the Philips Semiconductors ReUse Technology Group) indicating the type of interrupt controller.

guaranteed software compatibility between different major revisions of the same module.

software compatibility between minor revisions.

Table 4: IPC_MIPS Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

Interrupt Priority Mask Registers

Offset 0x03 F000 int_priority_0

31:3 Reserved R 0 Reserved for future extensions; should be written as 0.

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Table 4: IPC_MIPS Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

2:0 priority_limiter_0 R/W 0 Priority Limiter:

Offset 0x03 F004 int_priority_1

31:3 Reserved R 0

2:0 priority_limiter_1 R/W 0 Priority Limiter:

Interrupt Vector Registers

Offset 0x03 F100 int_vector_0

31:11 table_addr R/W 0 Table start address: indicates the lower address boundary of a 2048

10:3 Index R 0 Index: indicates the intreq line number of the interrupt request to be

2:0 Reserved R 0

…Continued

This variable determines a priority threshold that incoming interrupt requests must exceed to trigger interrupt requests towards processor. Legal PRIORITY_LIMITER values are 0... 7; other values are reserved and lead to undefined behavior.

PRIORITY_LIMITER = 0: Incoming interrupt requests with priority >0 can trigger interrupt requests towards processor.

PRIORITY_LIMITER = n: Only interrupt requests at a priority level above n can trigger interrupt requests towards processor.

PRIORITY_LIMITER = 7: No incoming interrupt requests can trigger interrupt requests towards processor.

High order bits not required for PRIORITY_LIMITER encoding are read-only 0.

This variable determines a priority threshold that incoming interrupt requests must exceed to trigger interrupt requests towards processor.

Legal PRIORITY_LIMITER values are 0... 7; other values are reserved and lead to undefined behavior. PRIORITY_LIMITER = 0: Incoming interrupt requests with priority >0 can trigger interrupt requests towards processor.

PRIORITY_LIMITER = n: Only interrupt requests at a priority level above n can trigger interrupt requests towards processor.

PRIORITY_LIMITER = 7: No incoming interrupt requests can trigger interrupt requests towards processor.

High order bits not required for PRIORITY_LIMITER encoding are read-only 0.

byte aligned interrupt vector table in memory.

served by the processor:

INDEX = 0: No interrupt request to be served INDEX = 1: Serve interrupt request at input intreq1 INDEX = 2: Serve interrupt request at input intreq2 ...

INDEX = 8: Serve interrupt request at input intreq8

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Table 4: IPC_MIPS Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

Offset 0x03 F104 int_vector_1

31:11 table_addr R/W 0 Table start address: indicates the lower address boundary of a 2048

10:3 Index R 0 Index: indicates the intreq line number of the interrupt request to be

2:0 Reserved R 0

Interrupt Pending Registers

Offset 0x03 F200 int_pending_1_8

31:9 Reserved R 0

8:1 pending[i] R 0 Pending interrupt request:

0 Reserved R 0

Interrupt Features Register

Offset 0x03 F300 int_features

31:22 0 R -

21:16 Targets R 1 Number of interrupt targets supported (minus one)

15:8 Priority Limit R 7 Number of priority levels supported (minus one)

7:0 Number of request

inputs

Interrupt Message Registers

Offset 0x03 F404 Message Register_1

31 pending R 0 Pending interrupt request:

30 SET_SWINT W 0 Set software interrupt request

R 8 Number of interrupt request inputs

…Continued

byte aligned interrupt vector table in memory.

served by the processor:

INDEX = 0: No interrupt request to be served INDEX = 1: Serve interrupt request at input intreq1 INDEX = 2: Serve interrupt request at input intreq2 ...

INDEX = 8: Serve interrupt request at input intreq8

PENDING = 0:no interrupt request PENDING = 1: interrupt request is pending

PENDING = 0:no interrupt request PENDING = 1: interrupt request pending

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Table 4: IPC_MIPS Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

29 CLR_SWINT W 0 Clear software interrupt request:

28 WE_PRIORITY_LEVEL W x Write Enable PRIORITY_LEVEL

27 WE_TARGET W x Write Enable TARGET

26 WE_ENABLE W x Write Enable ENABLE

25:17 Reserved R 0

16 enable_type R/W 0 Enable interrupt request:

15:9 Reserved R

8 target_type R/W 0 Interrupt target:

7:4 Reserved

…Continued

WE_PRIORITY_LEVEL = 0 (write): no change of PRIORITY_LEVEL variable state WE_PRIORITY_LEVEL = 1 (write): PRIORITY_LEVEL variable state may be changed WE_PRIORITY_LEVEL is always read as 0. This bit is self-clearing.

WE_TARGET = 0 (write): no change of TARGET variable state WE_TARGET = 1 (write): TARGET variable state may be changed WE_TARGET is always read as 0. This bit is self-clearing.

WE_ENABLE = 0 (write): no change of ENABLE variable state WE_ENABLE = 1 (write): ENABLE variable state may be changed. WE_ENABLE is always read as 0. This bit is self-clearing.

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Table 4: IPC_MIPS Registers (Rev 1.6.1)

Bit Symbol Access Val ue Description

3:0 priority_level R/W 0 Priority level:

Offset 0x03 F408 Message Register_2

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

Offset 0x03 F40C Message Register_3

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

Offset 0x03 F410 Message Register_4

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

Offset 0x03 F414 Message Register_5

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

Offset 0x03 F418 Message Register_6

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

Offset 0x03 F41C Message Register_7

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

Offset 0x03 F420 Message Register_8

This register signals an IPC message. This register is identical to Message Register_1 (Offset 0x03 F404).

…Continued

This variable determines the priority level of the interrupt request. Legal values are 0... 7; other values are reserved and lead to undefined behavior. See also WE_PRIORITY_LEVEL. PRIORITY_LEVEL = 0: the interrupt request has priority level 0 (masked); it is ignored. PRIORITY_LEVEL = 1: the interrupt request has priority level 1 (lowest). ...

PRIORITY_LEVEL = 7: the interrupt request has priority level 7 (highest). High order bits not required for PRIORITY_LEVEL encoding are read-only 0.

Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

PCI Control Registers

This register must be initialized before any PCI cycles will be entertained. The boot loader is expected to load the values at boot time. Write once by boot loader, otherwise read only. Because this register is “written once” the bit fields are designated “R/W1.” An unlock is available to update this register if necessary. A write of “CA” to bits [7:0] of the unlock_setup register will allow one additional write to the setup register before locking again

Offset 0x04 0010 PCI Setup

31 Reserved R 0

30 dis_reqgnt R/W1 0 Disable use of REQ/GNT when using internal arbiter. These pins

may be released for other uses when using an internal arbiter and no external PCI masters are used in the system.

29 dis_reqgnt_a R/W1 0 Disable use of REQ_A/GNT_A when using internal arbiter. These

pins are not used when using an external harborer.

28 dis_reqgnt_b R/W1 0 Disable use of REQ_B/GNT_B when using internal arbiter. These

pins are not used when using an external arbiter.

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Table 5: PCI-XIO Registers (Rev 0.9.6) …Continued

Bit Symbol Access Val ue Description

27 d2_support R/W1 1 Support for D2 power state

26 d1_support R/W1 1 Support for D1 power state

25 Reserved R/W1 0

24 en_ta R/W1 0 Terminate restricted access attempt with target abort (otherwise,

ignore writes, return 0 on read).

23 en_pci2mmi R/W1 1 Enable memory hwy interface.

22 en_xio R/W1 1 Enable XIO functionality.

21 base18_prefetchable R/W1 0 PCI base address 18 is a prefetchable memory aperture.

20:18 base18_siz R/W1 011 The size of aperture located by PCI cfg base18 is:

011 = 16 MB 100 = 32 MB 101 = 64 MB 110 = 128 MB This aperture is used as the XIO aperture in the PNX8550. Note: If expanding to 128 MB, the default setting of base18 address will overlap with the default base14 address. To avoid an address conflict, the base18 address or the base14 address should be relocated before setting the base18_siz.

17 en_base18 R/W1 1 Enable 3rd aperture, PCI base address 18. The PNX8550 will

always use this aperture.

16 base14_prefetchable R/W1 0 PCI Base address 14 is a non-prefetchable memory aperture.

15 Reserved R 0

14:12 base14_siz R/W1 000 The size of aperture located by PCI cfg base 14 is 000 = 2 MB.

This aperture is used as the MMIO aperture in the PNX8550.

11 en_base14 R/W1 1 Enable 2nd aperture, PCI base address 14. The PNX8550 will

always use this aperture.

10 base10_prefetchable R/W1 1 PCI Base address 10 is a prefetchable memory aperture.

9:7 base10_siz R/W1 100 The size of aperture located by PCI cfg base 10 is:

011 = 16 MB 100 = 32 MB 101 = 64 MB 110 = 128 MB

This aperture is used as the DRAM aperture in the PNX8550.

6:2 Reserved

1 en_config_manag R/W1 1 Enable configuration management.

0 en_pci_arb R/W1 0 Enable internal PCI system arbitration.

Offset 0x04 0014 PCI Control

31:17 Reserved R 0

16 dis_swapper2targ R/W 0 0 = Enable byte swapping in big endian mode from DCS to PCI

path. 1 = Disable byte swapping in big endian mode from DCS to PCI path.

15 dis_swapper2intreg R/W 0 0 = Enable byte swapping in big endian mode from PCI to PCI mmio

registers. 1 = Disable byte swapping in big endian mode from PCI to PCI mmio registers.

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

14 dis_swapper2dtlinit R/W 0 0 = Enable byte swapping in big endian mode from PCI to DCS.

13 regs_wr_post_en R/W 0 Enable write posting to internal PCI registers.

12 xio_wr_post_en R/W 0 Enable write posting to XIO address range.

11 pci2_wr_post_en R/W 0 Enable write posting to pci_base2 address range.

10 pci1_wr_post_en R/W 0 Enable write posting to pci_base1 address range.

9 en_serr_seen R/W 0 Enable monitoring of the SERR pin.

8:7 Reserved R 0

6 en_base10_spec_rd R/W 1 Read ahead to optimize PCI read latency to base 10.

5 en_base14_spec_rd R/W 0 Read ahead to optimize PCI read latency to base 14.

4 en_base18_spec_rd R/W 0 Read ahead to optimize PCI read latency to base 18.

3 disable_subword2_10 R/W 0 Disable subword access to/from Base10 aperture.

2 disable_subword2_14 R/W 1 Disable subword access to/from Base14 aperture.

1 disable_subword2_18 R/W 1 Disable subword access to/from Base18 aperture.

0 en_retry_timer R/W 1 Enables timer for 16 tic rule enforcer. This bit does not affect access

Offset 0x04 0018 PCI_Base1_lo

31:21 pci_base1_lo R/W 0 For internal address decoding: low bar of first aperture for external

20:0 Reserved R 0

Offset 0x04 001C PCI_Base1_hi

31:21 pci_base1_hi R/W 0 For internal address decoding: high bar of first aperture for external

20:0 Reserved R 0

Offset 0x04 0020 PCI_Base2_lo

31:21 pci_base2_lo R/W 0 For internal address decoding: low bar of second aperture for

20:0 Reserved R 0

…Continued

1 = Disable byte swapping in big endian mode from PCI to DCS.

to the XIO aperture.

PCI access. This register affects the decode and routing of the bus controllers. It should not be relied on as stable for 10 clocks after writing. It is recommended that the PCI_Base1_lo be initialized before the PCI_Base1_hi to avoid a potentially large segment of address space being temporarily allocated to PCI space.

PCI access (up to but not including). This register affects the decode and routing of the bus controllers. It should not be relied on as stable for 10 clocks after writing. It is recommended the PCI_Base1_lo be initialized before the PCI_Base1_hi to avoid a potentially large segment of address space being temporarily allocated to PCI space.

external PCI access. This register affects the decode and routing of the bus controllers. It should not be relied on as stable for 10 clocks after writing. It is recommended the PCI_Base2_lo be initialized before the PCI_Base2_hi to avoid a potentially large segment of address space being temporarily allocated to PCI space. The PCI_Base2 aperture may be declared as a internal view of PCI IO space or as PCI memory space. See pci_io register for more information.

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

Offset 0x04 0024 PCI_Base2_hi

31:21 pci_base2_hi R/W 0 For internal address decoding: high bar of second aperture for

20:0 Reserved R 0

Offset 0x04 0028 Read Data Lifetime Timer

31:16 Unused -

15:0 read_lifetime R/W 8000 This register is the amount of time (in PCI clocks) the PCI will hold a

Offset 0x04 002C General Purpose PCI Master (GPPM) Address

31:0 gppm_addr R/W 0 This register will be written with the address for the single data

Offset 0x04 0030 General Purpose PCI Master (GPPM) Write Data

31:0 gppm_wdata R/W 0 This register will be written with the data for the single data phase

Offset 0x04 0034 General Purpose PCI Master (GPPM) Read Data

31:0 gppm_rdata R 0 This register will hold data from the selected target after completion

Offset 0x04 0038 General Purpose PCI Master (GPPM) Control

31:11 Reserved R 0

10 gppm_done R 0 1 = cycle has completed. This bit can also be viewed in the

9 init_pci_cycle R/W 0 1 = initiate a PCI single data phase transaction on the PCI bus with

8 Reserved R 0

7:4 gppm_cmd R/W 0 Command to be used with PCI cycle. Acceptable commands to use

3:0 gppm_ben R/W 0 Byte enables to be used with PCI cycle

Offset 0x04 003C Unlock Register

31:16 Reserved R 0

…Continued

external PCI access (up to but not including). This register affects the decode and routing of the bus controllers. It should not be relied on as stable for 10 clocks after writing. It is recommended the PCI_Base2_lo be initialized before the PCI_Base2_hi to avoid a potentially large segment of address space being temporarily allocated to PCI space. The PCI_Base2 aperture may be declared as a internal view of PCI IO space or as PCI memory space. See pci_io register for more information.

piece of data exclusively for an external PCI master. The timer is initiated when the PCI can not complete the requested read in 16 clock cycles and issues a retry.

phase cycle to be issued on the PCI bus. It will accept only 32-bit writes. When issuing type 0 configuration transactions, the device number (bits [15:11]) is expanded to bits [31:11] on the PCI bus as defined in the PCI 2.2 spec.

cycle to be issued on the PCI bus. This register will accept any size write.

of the read.

gppm_status register. Write to register 0x40FC8 to clear.

address “gppm_addr” and data “gppm_data.”

in the command field include IO read, IO write, memory Read, memory Write, configuration read and interrupt acknowledge. If configuration management is enabled, configuration write may be used.

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

15:8 unlock_ssid W 0 Writing a “0xCA” to this field will unlock the “subsystem_id” and

7:0 unlock_setup W 0 Writing a “0xCA” to this field will unlock the “classcode”,

Offset 0x04 0040 Image of Device ID and Vendor ID

31:16 device_id R 0x8550 PCI configuration device ID

15:0 vendor_id R 0x1131 PCI configuration vendor ID

Offset 0x04 0044 Image of Command/Status

31:16 status R 0x0290 PCI configuration status register

15:0 command R/W* 0x0000 PCI configuration command register.

Offset 0x04 0048 Image of Class Code/Revision ID

31:8 class code R/W* 048000 PCI configuration class code.

7:0 revision id R 00h 10h PCI configuration revision ID

Offset 0x04 004C Image of Latency Timer/Cache Line Size

31:24 BIST R 0 PCI configuration BIST

23:16 Header Type R 0 PCI configuration Header Type

15:8 latency timer R/W* 0 PCI configuration latency timer.

7:0 cache line size R/W* 0 PCI configuration cache line size.

Offset 0x04 0050 Base Address 10 Image

31:21 Base Address 10 R/W* 0 PCI configuration Base address for DRAM.

20:4 Reserved R 0

3 Prefetchable R cfg* *Value is determined at boot time by pci_setup register.

2:0 Type R 0 Indicates type 0 memory space (locatable anywhere in 32-bit

Offset 0x04 0054 Base Address 14 Image

31:4 Base Address 14 R/W* 1BE0000 PCI configuration Base address for MMIO.

…Continued

“subsystem_vendor” registers. A writer to the subsystem_id/ subsystemvendor” register will lock the register again.

“max_latency”, “min_gnt” and “pci_setup” registers. A write to the “pci_setup” register to lock registers again.

*This register is read/write if configuration management is enabled (pci_setup[1]). If not enabled, it is read only. Refer to configuration register 4 for details on which bits are implemented and controllable.

*Write-once/Read-only

*This register is read/write if configuration management is enabled (pci_setup[1]). If not enabled, it is read only.

This register affects the decode and routing of the bus controllers. It should not be relied on as stable for 10 clocks after writing. *This register is read/write if configuration management is enabled (pci_setup[1]). If not enabled, it is read only.

address space).

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Table 5: PCI-XIO Registers (Rev 0.9.6) …Continued

Bit Symbol Access Val ue Description

3 Prefetchable R cfg* *Value is determined at boot time by pci_setup register.

2:0 Type R 0 Indicates type 0 memory space (locatable anywhere in 32-bit

address space).

Offset 0x04 0058 Base Address 18 Image

31:4 Base Address 18 R/W* 1C00000 PCI configuration Base address for XIO.

3 Prefetchable R cfg* *Value is determined at boot time by pci_setup register.

2:0 Type R 0 Indicates PCI “type 0” memory space (locatable anywhere in 32-bit

address space).

Offset 0x04 006C Subsystem ID/Subsystem Vendor ID Write Port

This register must be initialized before any PCI cycles will be entertained. The boot loader is expected to load the values at boot time. This register is a Write-once/Read-only register (R/W1).

31:16 subsystem ID R/W1 0 This is the write port for the Subsystem ID (PCI config 2C).

15:0 subsystem vendor ID R/W1 0 This is the write port for the Subsystem Vendor ID (PCI config 2C).

Offset 0x04 0074 Image of Configuration Reg 34

31:8 Reserved R 0

7:0 CAP_PTR R 40 Capabilities Pointer

Offset 0x04 007C Image of Configuration Reg 3C

31:24 max_lat R/W1 0x18 Max Latency

23:16 min_gnt R/W1 0x09 Minimum Grant

15:8 interrupt pin R 0x01 Interrupt pin information

7:0 Interrupt Line R/W* 0x00 This register conveys interrupt line routing information.

*This register is read/write if configuration management is enabled (pci_setup[1]). If not enabled, it is read only.

Offset 0x04 0080 Image of Configuration Reg 40

31:27 Reserved R 00000

26 d2_support R cfg* 1 = Device supports D2 power management state.

*Value is determined by pci_setup register.

25 d1_support R cfg* 1 = Device supports D1 power management state.

*Value is determined by pci_setup register.

24:19 Reserved R 0

18:16 version R 010 Indicates compliance with version 1.1 of PM.

15:8 Next Item Pointer R 00 There are no other extended capabilities.

7:0 Cap_ID R 01 Indicates this is power management data structure.

Offset 0x04 0084 Image of Configuration Reg 44

31:1 Reserved R 0

1:0 pwr_state R/W* 0 Power State

*This register is read/write if configuration management is enabled (pci_setup[1]). If not enabled, it is read only.

Preliminary Rev. 02 — July 22 2004 1 - 21

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

Offset 0x04 0088 PCI_IO

31:24 upper_io3_addr R/W 0 Bits [31:24] of IO address during PCI IO transactions.

23:16 upper_io2_addr R/W 0 Bits [23:16] of IO address during PCI IO transactions.

15:3 Reserved R 0

2 use_io3_addr R/W 0 Use “upper_io3_addr” as the upper address for PCI IO transactions.

1 use_io2_addr R/W 0 Use “upper_io3_addr” and “upper_io2_addr” as the upper address

0 use_pcibase2_as_io R/W 0 1: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as IO

Offset 0x04 008C Slave DTL tuning

31:24 Reserved R 0

20:16 slv_memrd_fetch R/W 111 PCI slave DTL read block size for memory read command

11:8 slv_threshold R/W 10 Threshold (amount of data not consumed from previous read

7:3 Reserved R 0

2:0 slv_mrmul_fetch R/W 001 Encoded PCI slave DTL read block size for memory read multiple

Offset 0x04 0090 DMA DTL tuning

31:16 Reserved R 0

15:8 dma_threshold R/W 0x1B Threshold for when DMA DTL requests more read data when initial

7:3 Reserved R 0

2:0 dma_fetch R/W 010 Encoded DMA DTL read block size

…Continued

for PCI IO transactions.

transactions. The address will be unchanged or modified with an alternate upper addresses selected above. 0: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as memory transactions with unchanged address.

request) for when PCI slave DTL requests more read data when responding to memory read command. This must be set to a value less than the smallest of slv_memrd_fetch, Cache Line Size or read_block_siz.

command

siz read_block_siz

000 0000000111 001 0000001111 010 0000011111 011 0000 111111 100 0001111111 101 0 011111111 110 0111111111 111 1111111111

fetch is less than total dma length.

siz read_block_siz

000 0000000111 001 0000001111 010 0000011111 011 0000 111111 100 0001111111 101 0 011111111 110 0111111111 111 1111111111

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Table 5: PCI-XIO Registers (Rev 0.9.6) …Continued

Bit Symbol Access Val ue Description

Offset 0x04 0094—07FC Reserved

Offset 0x04 0800 DMA PCI Address

This register will accept only word writes.

31:0 dma_eaddr R/W 1C00_0000This is the external starting address for the DMA engine. It is used

for DMA transfers over PCI and XIO. Bit 0 and 1 are not used because all DMA transfers are word aligned.

Offset 0x04 0804 DMA Internal Address

This register will accept only word writes.

31:0 dma_iaddr R/W 0010_0000This is the internal read source/ write destination address in

SDRAM.

Offset 0x04 0808 DMA Transfer Size

This register will accept any size writes.

31:16 Reserved R/W 0

15:0 dma_length R/W 800 This is the length of the DMA transfer (number of 4-byte words).

Offset 0x04 080C DMA Controls

This register will accept any size writes.

31:11 Reserved R 0

10 single_data_phase R/W 0 1 = Limit DMA to single data phase transactions.

This overrides “max_burst_size.” 0 = Use max_burst_size to determine burst size.

9 snd2xio R/W 0 0 = DMA will target PCI.

1 = DMA will target XIO.

8 fix_addr R/W 0 0 = DMA will use linear address.

1 = DMA will use a fixed address.

7:5 max_burst_size R/W 0 PCI transaction will be split into multiple transactions. Max size:

000 = 8 data phase 001 = 16 data phase 010 = 32 data phase 011 = 64 data phase 100 = 128 data phase 101 = 256 data phase 110 = 512 data phase 111 = No restriction in transfer length

4 init_dma R/W 0 Initiate DMA transaction. This bit is cleared by the DMA engine

when it begins its operation.

3:0 cmd_type R/W 0 Command to be used for DMA. This field is restricted to memory

type or IO type commands as defined in the PCI 2.2 spec. A command filter checks compliance with alignment and length when using memory write and invalidate and memory read multiple. Any non-compliant request will result in a memory read line or memory write command being substituted for the requested operation. This filter ensures proper command usage when restarting after being retried by an external target.

Offset 0x04 0810 XIO Control Register

31:2 Reserved R 0

1 xio_ack R Live XIO_ACK status bit.

Preliminary Rev. 02 — July 22 2004 1 - 23

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

0 Reserved R 0

Offset 0x04 0814 XIO Sel0 Profile

This register sets up the profile of the XIO select 0 line. All times are in reference to PCI clocks.

31:25 Reserved R 0

24 misc_ctrl R/W 0 68360: 1 synchronous DSACK; 0 asynchronous DSACK.

23 en_16bit_xio R/W 0 0 = 8 bit XIO device

22 sel0_use_ack R/W 0 0 = Fixed wait state

21:18 sel0_we_hi R/W 0 68360: DS time high.

17:14 sel0_we_lo R/W 0 68360: Not used.

13:9 sel0_wait R/W 0 68360: DS time low if using fixed timing.

8:5 sel0_offset R/W 0 Starting address offset from start address of XIO aperture, in 8M

4:3 sel0_type R/W 0 Device type selected:

2:1 sel0_siz R/W 0 Amount of address space allocated to Sel0:

0 en_sel0 R/W 0 1 = Enable sel0 profile.

Offset 0x04 0818 XIO Sel1 Profile

This register sets up the profile of the XIO select 1 line. All times are in reference to PCI clocks.

31:25 Reserved R 0

24 misc_ctrl R/W 0 68360: 1 synchronous DSACK; 0 asynchronous DSACK.

…Continued

NOR: 1 = use REQ_B (untested feature); 0 = use XIO_ACK NAND: Not used IDE: Not used

1 = 16 bit XIO device

1 = Wait for ACK Not used for IDE.

NOR: WN time high NAND: REN profile, [19:18] low time; [21:20] high time IDE: DIOR and DIOW high time

NOR: WN time low NAND: WEN profile, [15:14] low time; [17:16] high time IDE: DIOR and DIOW low time

NOR: OEN time low if not using ACK. NAND: Delay between address and data phase if not using ACK, delay until monitoring ACK. IDE: Not used.

increments. This field must be naturally aligned with the size of the profile.

00 = 68360 type device 01 = NOR Flash 10 = NAND-Flash 11 = IDE

00 = 8M 01 = 16M 10 = 32M 11 = 64M

NOR: 1 = use REQ_B (untested feature); 0 = use XIO_ACK NAND: Not used IDE: Not used

Preliminary Rev. 02 — July 22 2004 1 - 24

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Table 5: PCI-XIO Registers (Rev 0.9.6) …Continued

Bit Symbol Access Val ue Description

23 en_16bit_xio R/W 0 0 = 8 bit XIO device

1 = 16 bit XIO device

22 sel1_use_ack R/W 0 1 = Wait for ACK

0 = fixed wait state. Not used for IDE.

21:18 sel1_we_hi R/W 0 63860: time high.

NOR: WN time high NAND: REN profile, [19:18] low time; [21:20] high time IDE: DIOR and DIOW high time

17:14 sel1_we_lo R/W 0 63860: Not used.

NOR: WN time low NAND: WEN profile, [15:14] low time; [17:16] high time IDE: DIOR and DIOW low time

13:9 sel1_wait R/W 0 63860: DS time low if using fixed timing.

NOR: OEN time low if not using ACK. NAND: Delay between address and data phase if not using ACK, delay until monitoring ACK. IDE: Not used.

8:5 sel1_offset R/W 0 Address offset form start address of XIO aperture, in 8M

increments. This field must be naturally aligned with the size of the profile.

4:3 sel1_type R/W 0 Sel1 is configured as:

00 = 68360 type device 01 = NOR Flash 10 = NAND-Flash 11 = IDE

2:1 sel1_siz R/W 0 Amount of address space allocated to Sel1:

00 = 8M 01 = 16M 10 = 32M 11 = 64M

0 en_sel1 R/W 0 Enable sel1 profile.

Offset 0x04 081C XIO Sel2 Profile

This register sets up the profile of the XIO select 2 line. All times are in reference to PCI clocks.

31:25 Reserved R 0

24 misc_ctrl R/W 0 68360: 1 synchronous DSACK; 0 asynchronous DSACK.

NOR: 1 = use REQ_B (untested feature); 0 = use XIO_ACK NAND: Not used IDE: Not used

23 en_16bit_xio R/W 0 0 = 8 bit XIO device

1 = 16 bit XIO device

22 sel2_use_ack R/W 0 0 = Fixed wait state.

1 = Wait for ACK Not used for IDE

21:18 sel2_we_hi R/W 0 68360: DS time high.

NOR: WN time high NAND: REN profile, [19:18] low time; [21:20] high time IDE: DIOR and DIOW high time

Preliminary Rev. 02 — July 22 2004 1 - 25

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Table 5: PCI-XIO Registers (Rev 0.9.6) …Continued

Bit Symbol Access Val ue Description

17:14 sel2_we_lo R/W 0 63860: Not used.

NOR: WN time low NAND: WEN profile, [15:14] low time; [17:16] high time IDE: DIOR and DIOW low time

13:9 sel2_wait R/W 0 68360: DS time low if using fixed timing.

NOR: OEN time low if not using ACK. NAND: Delay between address and data phase if not using ACK, delay until monitoring ACK. IDE: Not used.

8:5 sel2_offset R/W 0 Address offset form start address of XIO aperture, in 8M

increments. This field must be naturally aligned with the size of the profile.

4:3 sel2_type R/W Sel2 is configured as:

00 = 68360 type device 01 = NOR Flash 10 = NAND-Flash 11 = IDE

2:1 sel2_siz R/W 0 Amount of address space allocated to Sel2:

00 = 8M 01 = 16M 10 = 32M 11 = 64 M

0 en_sel2 R/W 0 Enable sel2 profile.

Offset 0x04 0820 GPXIO_address

31:0 gpxio_addr R/W 0 General Purpose XIO cycle address. This register sets the address

for an indirect read or write to/from XIO address space. Only 4 byte writes are allowed in this register. The values programmed for bits 0 and 1 are not used by the XIO module. Refer to gpxio_ben.

Offset 0x04 0824 GPXIO_write_data

31:0 gpxio_wdata R/W 0 General Purpose XIO cycle data. This register is programmed with

data for a write cycle.

Offset 0x04 0828 GPXIO_read_data

31:0 gpxio_rdata R 0 General Purpose XIO cycle data. This register contains the data of a

read cycle after completion.

Offset 0x04 082C GPXIO_ctrl

This register controls the type of access to XIO and provides status.

31:10 Reserved R 0

9 gpxio_cyc_pending R 0 1 = GPXIO transaction on XIO is pending.

0 = GPXIO has completed or not yet started.

8 gpxio_done R 0 General Purpose XIO cycle complete. This bit is cleared by writing 1

to bit 6 or 7. It will also be cleared by writing to the GPXIO interrupt clear register.

7 clr_gpxio_done W 0 1 = Clear “gpxio_done.”

6 gpxio_init R/W 0 1 = Initiate a transaction on XIO. The type of transaction will match

the profile of the selected aperture. This bit gets cleared if the cycle has been initiated. This bit clears bit 8 if set.

5 Reserved R 0

Preliminary Rev. 02 — July 22 2004 1 - 26

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

4 gpxio_rd R/W 0 1 = Read command on XIO

3:0 gpxio_ben R/W 0 Active low byte enables to be used on the indirect XIO cycle. These

Offset 0x04 0830 NAND-Flash controls

31:22 Reserved

21 nand_64meg R/W 17 1 = 64-MB device support;

20 nand_inc_data R/W 17 1 = Include data in access cycle;

19:18 nand_cmd_ph R/W 17 No. of commands to be used in NAND-Flash access.

17:16 nand_adr_ph R/W 17 No. of address phases to be used in NAND-Flash access.

15:8 command_b R/W 0 This is the second command for NAND-Flash when two commands

7:0 command_a R/W 0 This is the command type to be used with NAND-Flash cycles when

Offset 0x04 0834 XIO Sel3 Profile

This register sets up the profile of the XIO select 3 line. All times are in reference to PCI clocks.

31:25 Reserved R 0

24 misc_ctrl R/W 0 68360: 1 synchronous DSACK; 0 asynchronous DSACK.

23 en_16bit_xio R/W 0 0 = 8 bit XIO device

22 sel3_use_ack R/W 0 0 = Fixed wait state

21:18 sel3_we_hi R/W 0 68360: DS time high.

17:14 sel3_we_lo R/W 0 68360: Not used.

…Continued

0 = Write command on XIO

are used to determine how many bytes to access and the lower two address bits for use in “gpxio_addr”.

0 = 32 MB and smaller device support

0 = access does not include data phase(s)

10 = use command a at begining of transaction and command b at end of transaction.

01 = Use command a at begining of transaction.

00 = Use no commands in transaction.

For 64-MB devices, 11 provide four address phases and 10 provide three address phases.

are required to complete a cycle.

one or more commands are required to complete a cycle.

NOR: 1 = use REQ_B (untested feature); 0 = use XIO_ACK NAND: Not used IDE: Not used

1 = 16 bit XIO device

1 = Wait for ACK Not used for IDE.

NOR: WN time high NAND: REN profile, [19:18] low time; [21:20] high time IDE: DIOR and DIOW high time

NOR: WN time low NAND: WEN profile, [15:14] low time; [17:16] high time IDE: DIOR and DIOW low time

Preliminary Rev. 02 — July 22 2004 1 - 27

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

13:9 sel3_wait R/W 0 68360: DS time low if using fixed timing.

8:5 sel3_offset R/W 0 Starting address offset from start address of XIO aperture, in 8M

4:3 sel3_type R/W 0 Device type selected:

2:1 sel3_siz R/W 0 Amount of address space allocated to Sel3:

0 en_sel3 R/W 0 1 = Enable sel3 profile

Offset 0x04 0838 XIO Sel4 Profile

This register sets up the profile of the XIO select 4line. All times are in reference to PCI clocks.

31:25 Reserved R 0

24 misc_ctrl R/W 0 68360: 1 synchronous DSACK; 0 asynchronous DSACK.

23 en_16bit_xio R/W 0 0 = 8 bit XIO device

22 sel4_use_ack R/W 0 0 = Fixed wait state

21:18 sel4_we_hi R/W 0 68360: DS time high.

17:14 sel4_we_lo R/W 0 68360: Not used.

13:9 sel4_wait R/W 0 68360: DS time low if using fixed timing.

8:5 sel4_offset R/W 0 Starting address offset from start address of XIO aperture, in 8M

…Continued

NOR: OEN time low if not using ACK. NAND: Delay between address and data phase if not using ACK, delay until monitoring ACK. IDE: Not used.

increments. This field must be naturally aligned with the size of the profile.

00 = 68360 type device 01 = NOR Flash 10 = NAND Flash 11 = IDE

00 = 8M 01 = 16M 10 = 32M 11 = 64M

NOR: 1 = use REQ_B (untested feature); 0 = use XIO_ACK NAND: Not used IDE: Not used

1 = 16 bit XIO device

1 = Wait for ACK Not used for IDE.

NOR: WN time high NAND: REN profile, [19:18] low time; [21:20] high time IDE: DIOR and DIOW high time

NOR: WN time low NAND: WEN profile, [15:14] low time; [17:16] high time IDE: DIOR and DIOW low time

NOR: OEN time low if not using ACK. NAND: Delay between address and data phase if not using ACK, delay until monitoring ACK. IDE: Not used.

increments. This field must be naturally aligned with the size of the profile.

Preliminary Rev. 02 — July 22 2004 1 - 28

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

4:3 sel4_type R/W 0 Device type selected:

2:1 sel4_siz R/W 0 Amount of address space allocated to Sel4:

0 en_sel4 R/W 0 1 = Enable sel4 profile

Offset 0x04 0FB0 GPXIO Interrupt Status

31:15 Reserved R 0

14 gpxio_xio_ack_done R 0 Rising edge of xio_ack has been observed

13 gpxio_done R 0 GPXIO transaction completed

12:10 Reserved R 0

9 gpxio_err R 0 Non-supported GPXIO command attempted or not enabled

8:3 Reserved R 0

2 gpxio_r_mabort R 0 GPXIO Received Master Abort

1:0 Reserved R 0

Offset 0x04 0FB4 GPXIO Interrupt Enable

31:15 Reserved R 0

14 en_int_gpxio_xio_ack_d

one

13 en_int_gpxio_done R/W 0 Enable Interrupt on GPXIO transaction completed

12:10 Reserved R 0

9 en_int_gpxio_err R/W 0 Enable Interrupt on non-supported GPXIO command attempted or

8:3 Reserved R 0

2 en_int_gpxio_r_mabort R/W 0 Enable Interrupt on GPXIO Received Master Abort

1:0 Reserved R 0

Offset 0x04 0FB8 GPXIO Interrupt Clear

31:15 Reserved R 0

14 clr_gpxio_xio_ack_done W 0 Clear rising edge of xio_ack has been observed

13 clr_gpxio_done W 0 Clear GPXIO transaction completed

12:10 Reserved R 0

9 clr_gpxio_err W 0 Clear non-supported GPXIO command attempted or not enabled

8:3 Reserved R 0

2 clr_gpxio_r_mabort W 0 Clear GPXIO Received Master Abort

1:0 Reserved R 0

Offset 0x04 0FBC GPXIO Interrupt Set

31:15 Reserved R 0

…Continued

00 = 68360 type device 01 = NOR Flash 10 = NAND Flash 11 = IDE

00 = 8M 01 = 16M 10 = 32M 11 = 64M

R/W 0 Enable Interrupt on rising edge of xio_ack has been observed

not enabled

Preliminary Rev. 02 — July 22 2004 1 - 29

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

14 set_gpxio_xio_ack_done W 0 Set rising edge of xio_ack has been observed

13 set_gpxio_done W 0 Set GPXIO transaction completed

12:10 Reserved R 0

9 set_gpxio_err W 0 Set non-supported GPXIO command attempted or not enabled

8:3 Reserved R 0

2 set_gpxio_r_mabort W 0 Set GPXIO Received Master Abort

1:0 Reserved R 0

Offset 0x04 0FC0 GPPM Interrupt Status

31:11 Reserved R 0

10 gppm_done R 0 GPPM transaction completed

9 gppm_err R 0 Non-supported GPPM command attempted or not enabled

8:6 Reserved R 0

5 gppm_mstr_parity_err R 0 GPPM master set or observed parity error (PERR)

4 gppm_err_parity R 0 GPPM Detected parity error (PERR)

3 Reserved R 0

2 gppm_r_mabort R 0 GPPM Received Master Abort

1 gppm_r_tabor R 0 GPPM Received Target Abort

0 Reserved R 0

Offset 0x04 0FC4 GPPM Interrupt Enable

31:11 Reserved R 0

10 en_int_gppm_done R/W 0 GPPM transaction completed

9 en_int_gppm_err R/W 0 Non-supported GPPM command attempted or not enabled

8:6 Reserved R 0

5 en_int_gppm_mstr_parit

y err

4 en_int_gppm_err_parity R/W 0 GPPM Detected parity error (PERR)

3 Reserved R 0

2 en_int_gppm_r_mabort R/W 0 GPPM Received Master Abort

1 en_int_gppm_r_tabor R/W 0 GPPM Received Target Abort

0 Reserved R 0

Offset 0x04 0FC8 GPPM Interrupt Clear

31:11 Reserved R 0

10 clr_gppm_done W 0 Clear GPPM transaction completed

9 clr_gppm_err W 0 Clear non-supported GPPM command attempted or not enabled

8:6 Reserved R 0

5 clr_gppm_mstr_parity

err

4 clr_gppm_err_parity W 0 Clear GPPM Detected parity error (PERR)

3 Reserved R 0

…Continued

R/W 0 GPPM master set or observed parity error (PERR)

W 0 Clear GPPM master set or observed parity error (PERR)

Preliminary Rev. 02 — July 22 2004 1 - 30

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

2 clr_gppm_r_mabort W 0 Clear GPPM Received Master Abort

1 clr_gppm_r_tabor W 0 Clear GPPM Received Target Abort

0 Reserved R 0

Offset 0x04 0FCC GPPM Interrupt Set

31:11 Reserved R 0

10 set_gppm_done W 0 Set GPPM transaction completed

9 set_gppm_err W 0 Set non-supported GPPM command attempted or not enabled

8:6 Reserved R 0

5 set_gppm_mstr_parity_errW 0 Set GPPM master set or observed parity error (PERR)

4 set_gppm_err_parity W 0 Set GPPM Detected parity error (PERR)

3 Reserved R 0

2 set_gppm_r_mabort W 0 Set GPPM Received Master Abort

1 set_gppm_r_tabor W 0 Set GPPM Received Target Abort

0 Reserved R 0

Offset 0x04 0FD0 DMA Interrupt Status

31:15 Reserved R 0

14 dma_xio_ack_done R 0 Rising edge of xio_ack has been observed

13 Reserved R 0

12 dma_done R 0 DMA transaction completed

11:10 Reserved R 0

9 dma_err R 0 Non-supported DMA command attempted or not enabled

8:6 Reserved R 0

5 dma_mstr_parity_err R 0 DMA master set or observed parity error (PERR)

4 dma_err_parity R 0 DMA Detected parity error (PERR)

3 Reserved R 0

2 dma_r_mabort R 0 DMA Received Master Abort

1 dma_r_tabor R 0 DMA Received Target Abort

0 Reserved R 0

Offset 0x04 0FD4 DMA Interrupt Enable

31:15 Reserved R 0

14 en_int_dma_xio_ack_doneR/W 0 Rising edge of xio_ack has been observed

…Continued

13 Reserved R 0

12 en_int_dma_done R/W 0 DMA transaction completed

11:10 Reserved R 0

9 en_int_dma_err R/W 0 Non-supported DMA command attempted or not enabled

8:6 Reserved R 0

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

5 en_int_dma_mstr_parity

_err

4 en_int_dma_err_parity R/W 0 DMA Detected parity error (PERR)

3 Reserved R 0

2 en_int_dma_r_mabort R/W 0 DMA Received Master Abort

1 en_int_dma_r_tabor R/W 0 DMA Received Target Abort

0 Reserved R 0

Offset 0x04 0FD8 DMA Interrupt Clear

31:15 Reserved R 0

14 clr_dma_xio_ack_done W 0 Rising edge of xio_ack has been observed

13 Reserved R 0

12 clr_dma_done W 0 Clear DMA transaction completed

11:10 Reserved R 0

9 clr_dma_err W 0 Clear non-supported DMA command attempted or not enabled

8:6 Reserved R 0

5 clr_dma_mstr_parity_err W 0 Clear DMA master set or observed parity error (PERR)

4 clr_dma_err_parity W 0 Clear DMA Detected parity error (PERR)

3 Reserved R 0

2 clr_dma_r_mabort W 0 Clear DMA Received Master Abort

1 clr_dma_r_tabor W 0 Clear DMA Received Target Abort

0 Reserved R 0

Offset 0x04 0FDC DMA Interrupt Set

31:15 Reserved R 0

14 set_dma_xio_ack_done W 0 Set Rising edge of xio_ack has been observed

13 Reserved R 0

12 set_dma_done W 0 Set DMA transaction completed

11:10 Reserved R 0

9 set_dma_err W 0 Set Non-Supported DMA command attempted or not enabled

8:6 Reserved R 0

5 set_dma_mstr_parity_errW 0 Set DMA master set or observed parity error (PERR)

…Continued

R/W 0 DMA master set or observed parity error (PERR)

4 set_dma_err_parity W 0 Set DMA Detected parity error (PERR)

3 Reserved R 0

2 set_dma_r_mabort W 0 Set DMA Received Master Abort

1 set_dma_r_tabor W 0 Set DMA Received Target Abort

0 Reserved R 0

Offset 0x04 0FE0 PCI Interrupt Status

This register represents the status of direct access to PCI-XIO and PCI slave events.

31:27 Reserved R 0

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

26 pcii_wr_err R 0 Interrupt on PCI DTL initiator write error flag

25 pcii_rd_err R 0 Interrupt on PCI DTL initiator read error flag

24 xio_wr_err R 0 Interrupt on XIO DTL target write error flag

23 xio_rd_err R 0 Interrupt on XIO DTL target read error flag

22 pcir_wr_err R 0 Interrupt on mmio register DTL target write error flag

21 pcir_rd_err R 0 Interrupt on mmio register DTL target read error

20 pwrstate_chg R 0 Power management register has been changed

19 Reserved R 0

18 pci2_wr_err R 0 Interrupt on PCI2 DTL target write error flag

17 pci2_rd_err R 0 Interrupt on PCI2 DTL target read error flag

16 pci1_wr_err R 0 Interrupt on PCI1 DTL target write error flag

15 pci1_rd_err R 0 Interrupt on PCI1 DTL target read error flag

14 pci_xio_ack_done R 0 Rising edge of xio_ack has been observed

13:12 Reserved R 0

11 serr_seen R 0 SERR observed on PCI bus

10 Reserved R 0

9 pci_err R 0 PCI master transaction attempted when not enabled by config

8 err_base10_subword R 0 Subword attempt to base10 aperture when restrained to word only

7 err_base14_subword R 0 Subword attempt to base14 aperture when restrained to word only

6 err_base18_subword R 0 Subword attempt to base18 aperture when restrained to word only

5 pci_mstr_parity_err R 0 PCI master set or observed parity error (PERR)

4 err_pci_parity R 0 PCI Detected parity error (PERR)

3 sig_serr R 0 Signaled system error (SERR)

2 pci_r_mabort R 0 PCI Received Master Abort

1 pci_r_tabor R 0 PCI Received Target Abort

0 pci_s_tabort R 0 PCI Signaled Target Abort

Offset 0x04 0FE4 PCI Interrupt Enable

31:27 Reserved R 0

26 en_int_pcii_wr_err R/W 0 Enable interrupt on PCI DTL initiator write error flag

25 en_int_pcii_rd_err R/W 0 Enable interrupt on PCI DTL initiator read error flag

24 en_int_xio_wr_err R/W 0 Enable interrupt on XIO DTL target write error flag

23 en_int_xio_rd_err R/W 0 Enable interrupt on XIO DTL target read error flag

22 en_int_pcir_wr_err R/W 0 Enable interrupt on mmio register DTL target write error flag

21 en_int_pcir_rd_err R/W 0 Enable interrupt on mmio register DTL target read error

20 en_int_pwrstate_chg R/W 0 Enable interrupt on change of power state register

19 Reserved R 0

…Continued

(not used on the PNX8550)

(not used on PNX8550)

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

18 en_int_pci2_wr_err R/W 0 Enable interrupt on PCI2 DTL target write error flag

17 en_int_pci2_rd_err R/W 0 Enable interrupt on PCI2 DTL target read error flag

16 en_int_pci1_wr_err R/W 0 Enable interrupt on PCI1 DTL target write error flag

15 en_int_pci1_rd_err R/W 0 Enable interrupt on PCI1 DTL target read error flag

13:12 Reserved R 0

11 en_int_serr_seen R/W 0 Enable interrupt on SERR observed on PCI bus

10 Reserved R 0

9 en_int_pci_err R/W 0 Enable interrupt on pci_err flag

8 en_int_base10_subword R/W 0 Enable interrupt on Subword Attempt to Base10 Error Status

7 en_int_base14_subword R/W 0 Enable interrupt on Subword Attempt to Base14 Error Status

6 en_int_base18_subword R/W 0 Enable interrupt on Subword Attempt to Base18 Error Status

5 en_int_pci_mstr_parity

4 en_int_pci_parity R/W 0 Enable interrupt on PCI Parity Error Status

3 en_int_sig_serr R/W 0 Enable interrupt on System Error Status

2 en_int_pci_r_mabort R/W 0 Enable interrupt on PCI Received Master Abort Status

1 en_int_pci_r_tabort R/W 0 Enable interrupt on PCI Received Target Abort Status

0 en_int_pci_s_tabort R/W 0 Enable interrupt on PCI Signaled Target Abort Status

Offset 0x04 0FE8 PCI Interrupt Clear

31:27 Reserved R 0

26 clr_pcii_wr_err W 0 Clear PCI DTL initiator write error flag

25 clr_pcii_rd_err W 0 Clear PCI DTL initiator read error flag

24 clr_xio_wr_err W 0 Clear XIO DTL target write error flag

23 clr_xio_rd_err W 0 Clear XIO DTL target read error flag

22 clr_pcir_wr_err W 0 Clear mmio register DTL target write error flag

21 clr_pcir_rd_err W 0 Clear mmio register DTL target read error

20 clr_pwrstate_chg W 0 Clear power state change register flag

19 Reserved R 0

18 clr_pci2_wr_err W 0 Clear PCI2 DTL target write error flag

17 clr_pci2_rd_err W 0 Clear PCI2 DTL target read error flag

16 clr_pci1_wr_err W 0 Clear PCI1 DTL target write error flag

15 clr_pci1_rd_err W 0 Clear PCI1 DTL target read error flag

14 clr_pci_xio_ack_done W 0 Clear pci_xio_ack done flag

13:12 Reserved R 0

11 clr_serr_seen W 0 Clear serr_seen flag

10 Reserved R 0

9 clr_pci_err W 0 Clear pci_err flag

8 clr_base10_subword W 0 Clear Subword Attempt to Base10 Error Status

en_int_pci_xio_ack_done

err

…Continued

R/W 0 Enable interrupt on rising edge of xio_ack done

R/W 0 Enable interrupt on PCI Master Parity Error

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Table 5: PCI-XIO Registers (Rev 0.9.6) …Continued

Bit Symbol Access Val ue Description

7 clr_base14_subword W 0 Clear Subword Attempt to Base14 Error Status

6 clr_base18_subword W 0 Clear Subword Attempt to Base18 Error Status

5 clr_pci_mstr_parity_err W 0 Clear PCI Master Parity Error

4 clr_pci_parity W 0 Clear PCI Parity Error Status

3 clr_sig_serr W 0 Clear System Error Status

2 clr_pci_r_mabort W 0 Clear PCI Received Master Abort Status

1 clr_pci_r_tabort W 0 Clear PCI Received Target Abort Status

0 clr_pci_s_tabort W 0 Clear PCI Signaled Target Abort Status

Offset 0x04 0FEC PCI Interrupt Set

31:27 Reserved R 0

26 set_pcii_wr_err W 0 Set PCI DTL initiator write error flag

25 set_pcii_rd_err W 0 Set PCI DTL initiator read error flag

24 set_xio_wr_err W 0 Set XIO DTL target write error flag

23 set_xio_rd_err W 0 Set XIO DTL target read error flag

22 set_pcir_wr_err W 0 Set mmio register DTL target write error flag

21 set_pcir_rd_err W 0 Set mmio register DTL target read error

20 set_pwrstate_chg W 0 Set change of power state register flag

19 Reserved R 0

18 set_pci2_wr_err W 0 Set PCI2 DTL target write error flag

17 set_pci2_rd_err W 0 Set PCI2 DTL target read error flag

16 set_pci1_wr_err W 0 Set PCI1 DTL target write error flag

15 set_pci1_rd_err W 0 Set PCI1 DTL target read error flag

14 set_pci_xio_ack_done W 0 Set pci_xio_ack done flag

13:12 Reserved R 0

11 set_serr_seen W 0 Set serr_seen flag

10 Reserved R 0

9 set_pci_err W 0 Set pci_err flag

8 set_base10_subword W 0 Set Subword Attempt to Base10 Error Status

7 set_base14_subword W 0 Set Subword Attempt to Base14 Error Status

6 set_base18_subword W 0 Set Subword Attempt to Base18 Error Status

5 set_pci_mstr_parity_err W 0 Set PCI master Parity Error

4 set_pci_parity W 0 Set PCI Parity Error Status

3 set_sig_serr W 0 Set System Error Status

2 set_pci_r_mabort W 0 Set PCI Received Master Abort Status

1 set_pci_r_tabort W 0 Set PCI Received Target Abort Status

0 set_pci_s_tabort W 0 Set PCI Signaled Target Abort Status

Offset 0x04 0FFC Module ID

31:16 Module ID R 0xA051 Module ID

PNX8550

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Table 5: PCI-XIO Registers (Rev 0.9.6)

Bit Symbol Access Val ue Description

15:12 Major Revision number R 0 Major Revision number

11:8 Minor revision number R 0 Minor revision number

7:0 mod_size R 0 Module size is 4 kB.

Table 6: EJTAG DMA Registers (Rev 2.3)

Bit Symbol Access Val ue Description

Offset 0x04 1000 Implementation Register

31:26 Reserved R 0

25:24 Profiling Support R 0 No Profiling Support

23 SDBBP uses Special2

Opcode

22:21 Size of ASID field R 0 No ASIS in implementation

20 Complex Break Support R 0 Complex Break Support not supported

19 Physical Address Width R 0 Physical Address are 32-bit in length

18 Data Cache Coherency R 0 Data Cache does not keep coherency with DMA

17 Instruction Cache

Coherency

16 MIPS16 Support R 0 MIPS CPU does not support MIPS16

15 No PC Trace Support R 0 PC Trace is supported by implementation

14 No EJTAG DMA Support R 0 EJTAG DMA is supported by implementation

13:11 TPC Width R 1 2bits Extended EJTAG

10:8 PCST Width and DCLK

Division Factor

7 Processor Bus Break R 0 Processor Bus Break not implemented

6 Data Address Break R 0 Data Address Breask not implemented

5 Instruction Address

Break

4:1 Number of Break

Channels

0 MIPS 32/64 R 0 Mips is 32-bit wide data registers

Offset 0x04 1FFC Module ID Register

31:16 ID number R 0x0104 EJTAG module ID number

15:12 Major revision number R 1

11:8 Minor revision number R 0

7:0 Aperture R 0 Control space is 4 kB

…Continued

R 1 SDBBP is encoded using a Special2 Opcode

R 0 Instruction Cache does not keep DMA coherency

R 1 6bits (DCLK is 1/2 of MIPS CPU CLK)

R 0 Instruction Address Break not implemented

R 0 No break channels

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Table 7: M-Default Slv

Bit Symbol Access Val ue Description

Offset 0x04 2FFC

31:16 MOD_ID R 0x0124 Module ID Number

15:12 REV_MAJOR R 0 Major revision

11:8 REV_MINOR R 0 Minor revision

7:0 APP_SIZE R 00 Aperture size is 0 = 4 kB.

Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

Offset 0x04 3000 Reset Register (RER)

31:19 Reserved 0

18 RS_FIFO_LEVEL_INT W 0 Resets the bit FIFO_LEVEL_INT in Mixed Status register.

RS_FIFO_LEVEL_INT is automatically reset by hardware.

17 RS_DMA_WR_LEVEL_

INT

16 RS_DMA_RD_LEVEL_

INT

15 RS_DONE W 0 Resets the bit DONE in Mixed Status register. RS_DONE is

14 RS_BGT W 0 Resets the bit BGT in Mixed Status register. RS_BGT is

13 RS_OCH W 0 Resets the bit OCH in Mixed Status register. RS_OCH is

12 RS_DMAERR W 0 Resets the bit DMA_ERR in Mixed Status register. RS_DMAERR is

11 RS_DMAABORT W 0 Resets the bit DMA_ABORT in Mixed Status register.

10 RS_TO3 W 0 Resets the bit TO3 in UART Status register. RS_TO3 is

9 RS_TO2 W 0 Resets the bit TO2 in UART Status register. RS_TO2 is

8 RS_TO1 W 0 Resets the bit TO1 in UART Status register. RS_TO1 is

7 RS_EA W 0 Resets the bit EA in UART Status register. RS_EA is automatically

6 RS_PE W 0 Resets the bit PE in UART Status register. RS_PE is automatically

5 RS_OVR W 0 Resets the bit OVR in UART Status register. RS_OVR is

4 RS_FER W 0 Resets the bit FE in UART Status register. RS_FER is automatically

3 RS_TBERBF W 0 Resets the bit TBE/RBF in UART Status register. RS_TBERBF is

2 RFI W 0 Resets FIFO pointers.This bit is automatically reset by hardware.

W 0 Resets the bit DMA_WR_LEVEL_INT in Mixed Status register.

RS_DMA_WR_LEVEL_INT is automatically reset by hardware.

W 0 Resets the bit DMA_RD_LEVEL_INT in Mixed Status register.

RS_DMA_RD_LEVEL_INT is automatically reset by hardware.

automatically reset by hardware.

RS_DMAABORT is automatically reset by hardware.

automatically reset by hardware.

reset by hardware.

automatically reset by hardware.

reset by hardware.

automatically reset by hardware.

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Table 8: Smartcard UART 1 Registers (Rev 2.04) …Continued

Bit Symbol Access Value Description

1 RMS W 0 Reset Mixed Status register (RMS).

When set, this bit clears the OCH, DONE, DMA_ABORT, DMA_ERR and BGT bits in the MSR. It is automatically reset by hardware. Note that the BGT bit in the MSR register does not generate interrupts.

0 RUS W 0 Reset UART Status register (RUS).

When set, this bit clears all bits in the USR. It is automatically reset by hardware.

Offset 0x04 3004 Clock Configuration Register (CCR)

31:8 Reserved

7 SFD R/W 0 When set to ‘1’, 1 ETU = 624 clock card cycles.

6 RPB R/W 0 Remove Parity Bit. When this bit is set to ‘1’:

• In transmission mode: the parity bit is removed (allowing a 10 ETU data frame).

• In reception mode: there is no parity error check.

5 SHL R/W 0 When the CST bit (see below) is set to 1, the clock card signal

(output CLOCK_CARD) is stopped low if SHL=0, and stopped high if SHL=1.

4 CST R/W 1 In case of an asynchronous card, the Clock Stop (CST) bit defines

whether the clock card (output pin CLK_CARD) is stopped or not.

3 SC R/W 0 In case of a synchronous card (SAN bit in UCR2 is set to 1), the

output CLK_CARD is a copy of the SC bit.

2:0 AC2:AC0 R/W 0 If CST is reset (=0), the clock card frequency (output CLK_CARD) is

determined by those bits according to the following table:

AC2: AC1: AC0 = 000: CLK_CARD = CORE_CLK/2 AC2: AC1: AC0 = 001: CLK_CARD = CORE_CLK/4 AC2: AC1: AC0 = 010: CLK_CARD = CORE_CLK/6 AC2: AC1: AC0 = 011: CLK_CARD = CORE_CLK/8 AC2: AC1: AC0 = 100: CLK_CARD = CORE_CLK/12 AC2: AC1: AC0 = 101: CLK_CARD = CORE_CLK/16 AC2: AC1: AC0 = 110: CLK_CARD = CORE_CLK/24 AC2: AC1: AC0 = 111: CLK_CARD = CORE_CLK/32

All frequency changes are synchronous ensuring that no spike or unwanted pulse width occurs during changes.

Offset 0x04 3008 Programmable Divider Register (PDR)

31:8 Reserved

7:0 PD7:PD0 R/W 00000001This register is used for counting the card clock cycles forming the

ETU. The value 00000000 should never be written in this register.

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

Offset 0x04 300C UART Configuration Register 2 (UCR2)

31:16 DMA_WR_INT_THRES R/W h0000 During a DMA transfer in reception mode:

15:10 Reserved

9 DSDT R/W 0 Do not Stop DMA transfer:

8 DMA_SWITCH_RECEP R/W 0 When set, the Smartcard interface will automatically switch to

7 RSTIN R/W 0 Card reset signal from the controller. The output pin RSTIN is a

6 DISTBE/RBF R/W 0 If the bit DISTBE/RBF (disable TBE/RBF interrupt) is set, character

5 START R/W 0 If the controller sets START to 1, the card is activated (see

4 DMAE R/W 0 If bit DMAE (DMA enable) is set (=1), DMA mode is enabled. When

3 SAN R/W 0 Synchronous/Asynchronous is set by software if a synchronous

2 AUTOCONV R/W 0 If the bit AUTOCONV

…Continued

• if the number of received characters is equal to DMA_WR_INT_THRES, the DMA_WR_LEVEL_INT bit in the Mixed Status Register (MSR) will be set.

• If DMA_WR_INT_THRES is set to h’0000, DMA_WR_LEVEL_INT will not be set in the MSR and no interrupt will be generated. The DMA_WR_LEVEL_INT value can be changed during the DMA transfer.

• If DMA_WR_INT_THRES is higher or equal to the DMA Length Write (DLW) parameter, DMA_WR_LEVEL_INT in the (MSR) will not be set.

When this bit is set to ‘1’, in DMA reception mode, protocol T = 0. If a parity error is detected, the DMA transfer will be stopped.

Note: In DMA transmission mode, protocol T = 0. If a parity error is detected, the DMA transfer is stopped regardless of the value of DSDT.

reception mode at the end of a successful DMA transfer (transmission mode).

copy of this bit.

reception or transmission will not generate an interrupt.

description of activation sequence in the TDA 8004 product specification document).

If the controller resets START to 0, the card is deactivated (see description of deactivation sequence in the TDA 8004 product specification document). The output CMDVCC = NOT (START)

reset, interrupt mode is active.’

The bit DMAE is automatically reset (= 0) by hardware in the following conditions:

• DMA transfer successfully finished (bit DONE set in MSR).

• A parity error occurred during the DMA mode in T= 0 protocol (bit PE is set in USR).

• A change occurred on input pad OFF (bit OCH is set in MSR).

card is expected. The UART is bypassed and only the bit 0 in URR and UTR is connected to I/O. In this case, CLK_CARD output is controlled by the bit SC in the CCR register.

is set, software sets the CONV bit in the UCR1 register. If it is reset, the convention is automatically detected on the first received character while the Start Session (SS) bit is set.

Preliminary Rev. 02 — July 22 2004 1 - 39

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

1 CKU R/W 0 When the bit CKU is set, one ETU will last one half of the formula

0 PSC R/W 0 If PSC is set high, the prescaler value is 32. If PSC is set low, the

Offset 0x04 3010 DMA Read Address Register (DRA)

31:0 DRA31 - DRA0 R/W 0 Points to the memory address where the transfer is supposed to

Offset 0x04 3014 Guard Time Register (GTR)

31:8 Reserved

7:0 GT7:GT0 R/W 0 Used to store the number of guard ETUs returned by the card

Offset 0x04 3018 UART Configuration Register 1 (UCR1)

This register is used for setting parameters of the UART.

31:16 DMA_RD_INT_THRES R/W h0000 During a DMA transfer in transmission mode:

15:8 Reserved

7 RIU R/W 0 The Reset ISO UART (RIU

6 FIP R/W 0 If Force Inverse Parity (FIP) is set to high, then the UART will NACK

5 FC R/W 0 Flow Control (FC) is set if the flow control is used (not described in

4 PROT R/W 0 Protocol (PROT) determines the protocol type when in

…Continued

described below.

prescaler value is 31. One ETU will last the number of card clock cycles equal to PRESCALER x PDR.

start when the UART is in transmission mode. This register must be programmed before setting the DMAE bit in the UCR2. The DMA transfer must start at a double word-aligned boundary.

during ATR. In transmission mode, the UART will wait this number of ETUs before transmitting the character stored in the UTR.

In T=1 protocol, GTR=FF means operation at 11 ETUs. In protocol T=0, GTR=FF means operation at 12 ETUs.

• If the number of characters sent is equal to DMA_RD_INT_THRES, the DMA_RD_LEVEL_INT bit in the Mixed Status Register (MSR) will be set.

• If DMA_RD_INT_THRES is set to h’0000, the DMA_RD_LEVEL_INT bit will not be set in the MSR and no interrupt will be generated. The DMA_RD_LEVEL_INT bit value can be changed during the DMA transfer.

• If DMA_RD_INT_THRES is higher or equal to the DMA Length Read (DLR) parameter, the DMA_RD_LEVEL_INT bit in the MSR will not be set.

) bit must be set to 1 before any action on the UART. When reset =0, this bit resets all UART registers to their initial values except the following registers: MSR, CRE, SCIF_INT_STATUS, SCIF_INT_CLEAR, SCIF_INT_SET, SCIF_INT_ENABLE, SCIF_POWERDOWN and SCIF_MODULE_ID.

a correct received character and will transmit characters with the wrong parity bit.

this specification).

asynchronous transmission. If PROT = 1 protocol is T = 1. If PROT = 0 protocol is T = 0.

Preliminary Rev. 02 — July 22 2004 1 - 40

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Table 8: Smartcard UART 1 Registers (Rev 2.04) …Continued

Bit Symbol Access Value Description

3 T/R R/W 0 Transmit/Receive (T/R) is set by software for transmission mode. A

change from 0 to 1 will set the TBE bit in the USR. The T/R bit is automatically reset by hardware if Last Character to Transmit (LCT) has been used after transmitting the last character.

Note: Software must wait at least 12 ETUs after the last start bit before changing from reception mode (T/R = 0) to transmission mode (T/R = 1).

2 LCT R/W 0 Last Character to Transmit (LCT) is set by software after writing in

the UART Transmit Register (UTR). It allows an automatic change over to the reception mode, and is reset by hardware at the end of a successful transmission. The TBE/RBF bit in the UART Status register and MSR will not be set when changing from transmission to reception.

1 SS R/W 0 Start Session (SS) is set before ATR for automatic convention

detection and early answer detection. This bit must be reset by software after reception of a correct initial character.

0 CONV R/W 0 Convention (CONV) is set to High if the convention is direct, to Low

in case of inverse convention. The CONV bit is either automatically written by hardware according to the convention detected during ATR, or by software if the bit AUTOCONV

Offset 0x04 301C DMA Length Register (DLR)

31:16 DLW15 - DLW0 R/W 0 Determines the number of characters (bytes) to be transferred in

memory (65535 bytes max) when in reception mode. This register must be programmed before setting the DMAE bit in the UCR2.

15:12 Reserved R/W 0 Must be written with ‘0’.

11:0 DLR11 - DLR0 R/W 0 Determines the number of characters (bytes) to send (4095 bytes

max) to the smartcard when in transmission mode. This register must be programmed before setting the DMAE bit in the UCR2.

Offset 0x04 3020 Timeout Configuration Register (TOC)

31:8 Reserved 0

is set.

Preliminary Rev. 02 — July 22 2004 1 - 41

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

7:6 MODE31, MODE30 R/W 0 When MODE31, MODE30 = 00: STOP

5:4 MODE21, MODE20 R/W 0 When MODE21, MODE20 = 00: STOP

…Continued

Counter3 stops counting, no matter what the previous mode was.

When MODE31, MODE30 = 01: AUTORELOAD Counter3 starts counting the value stored in the associated register on the first start bit after this mode has been programmed, and automatically restarts counting this value when it has reached the terminal count. An interrupt is generated at every terminal count.

When MODE31, MODE30 = 10: SOFTWARE TRIGGERED The counter starts counting the value stored in the associated registers when this configuration has been written, and stops and generates an interrupt when it has reached its terminal count. At the end of count, the couple (MODE31, MODE30) is reset to (0,0) by hardware.

When MODE31, MODE30 = 11: TRIGGERED WHEN START BIT IS ON I/O In this mode, the counter will automatically start counting the value stored in the associated registers when a start bit occurs on I/0 (reception or transmission). An interrupt is only generated if the counter reaches the terminal count, then the Counter3 is stopped. At the end of the count, the couple (MODE31, MODE30) is reset to (0,0) by hardware.

Counter3 stops counting, no matter what the previous mode was.

When MODE21, MODE20 = 01: AUTORELOAD Counter3 starts counting the value stored in the associated register on the first start bit after this mode has been programmed, and automatically restarts counting this value when it has reached the terminal count. An interrupt is generated at every terminal count.

When MODE21, MODE20 = 10: SOFTWARE TRIGGERED The counter starts counting the value stored in the associated registers when this configuration has been written, and stops and generates an interrupt when it has reached its terminal count. At the end of count, the couple (MODE21, MODE20) is reset to (0,0) by hardware.

When MODE21, MODE20 = 11: TRIGGERED WHEN START BIT IS ON I/O In this mode, the counter will automatically start counting the value stored in the associated registers when a start bit occurs on I/0 (reception or transmission). An interrupt is only generated if the counter reaches the terminal count, then the Counter3 is stopped. At the end of the count, the couple (MODE21, MODE20) is reset to (0,0) by hardware.

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

3:2 MODE11, MODE10 R/W 0 When MODE11, MODE10 = 00: STOP

1:0 8/16, 16/24 R/W 0 When (8/16,16/24)=00 then TOR3, TOR2 and TOR1 are linked as a

Offset 0x04 3024 Timeout Register 1 (TOR1)

31:8 Reserved

7:0 TOL7: TOL0 W 0 An 8-bit ETU counter that can be linked to TOR2 and TOR3

Offset 0x04 3028 Timeout Register 2 (TOR2)

31:8 Reserved

7:0 TOL15:TOL8 W 0 An 8-bit ETU counter that can be linked to:

Offset 0x04 302C Timeout Register 3 (TOR3)

31:8 Reserved

7:0 TOL23:TOL16 W 0 An 8-bit ETU counter that can be linked to:

Offset 0x04 3030 Mixed Status Register (MSR)

31:11 Reserved

…Continued

Counter3 stops counting, no matter what the previous mode was.

When MODE11, MODE10 = 01: AUTORELOAD Counter3 starts counting the value stored in the associated register on the first start bit after this mode has been programmed, and automatically restarts counting this value when it has reached the terminal count. An interrupt is generated at every terminal count.

When MODE11, MODE10 = 10: SOFTWARE TRIGGERED The counter starts counting the value stored in the associated registers when this configuration has been written, and stops and generates an interrupt when it has reached its terminal count. At the end of count, the couple (MODE11, MODE10) is reset to (0,0) by hardware.

When MODE11, MODE10 = 11: TRIGGERED WHEN START BIT IS ON I/O In this mode, the counter will automatically start counting the value stored in the associated registers when a start bit occurs on I/0 (reception or transmission). An interrupt is only generated if the counter reaches the terminal count, then the Counter3 is stopped. At the end of the count, the couple (MODE11, MODE10) is reset to (0,0) by hardware.

24-bit ETU counter.

When (8/16,16/24)=01 then TOR3 and TOR2 are linked as a 16-bit ETU counter, and TOR1 is an independent 8-bit ETU counter.

When (8/16,16/24)=1X, TOR3, TOR2 and TOR1 are 3 independent 8-bit ETU counters.

registers to form a 24-bit ETU counter. (See the 0x04 3020 Timeout

Configuration Register (TOC) description.)

• TOR1 and TOR3 registers to form a 24-bit ETU counter

• TOR3 only to form a 16-bit ETU counter. (See the 0x04 3020

Timeout Configuration Register (TOC) description.)

• TOR2 and TOR3 registers to form a 24-bit ETU counter

• TOR2 only to form a 16-bit ETU counter. (See the 0x04 3020

Timeout Configuration Register (TOC) description.)

Preliminary Rev. 02 — July 22 2004 1 - 43

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Table 8: Smartcard UART 1 Registers (Rev 2.04) …Continued

Bit Symbol Access Value Description

10 FIFO_LEVEL_INT R 0 FIFO_LEVEL_INT is set to ‘1’ when the number of characters

present in the FIFO reaches the FIFO_THRES parameter in the FIFO Configuration Register (FCR).

The bit is reset when the RMS or RS_FIFO_LEVEL_INT bit is set in the Reset register.

9 DMA_WR_LEVEL_INT R 0 DMA_WR_LEVEL_INT is set to ‘1’ when during a DMA transfer,

reception mode, the number of received characters reaches the DMA_WR_INT_THRES parameter in UART Configuration Register 2 (UCR2).

The bit is reset when RMS or RS_DMA_WR_LEVEL_INT bit is set in the Reset register.

8 DMA_RD_LEVEL_INT R 0 DMA_RD_LEVEL_INT is set to ‘1’ when during a DMA transfer, in

transmission mode, the number of transmitted characters reaches the DMA_RD_INT_THRES parameter in the UART Configuration Register 1 (UCR1).

The bit is reset when RMS or RS_DMA_RD_LEVEL_INT bit is set in the Reset register.

7 DONE R 0 DONE is set when DMA transfer ends successfully. When this bit is

set, INT goes high. The bit is reset when RMS or RS_DONE bit is set in the Reset register.

6 FE R 1 FIFO Empty (FE) is set when the reception FIFO is empty. It is reset

when at least one character has been loaded in the FIFO.

5 BGT R 0 BGT is linked with a counter with a value of 22 ETUs that is

triggered at every start bit on I/O. If the count is finished before the next start bit, the BGT bit is set. This helps to verify that the card does not answer until 22 ETUs after the last transmitted character, or does not transmit a character until 22 ETUs after the last received character. This bit is reset by setting the RMS bit in the Reset register. It should be reset by the software when initiating a transaction (before the ATR phase).

4 BOF R 0 The BOF bit is a copy of the pin OFF.

3 OCH R 0 The OCH bit is set when a change occurs on pin OFF. When this bit

is set, INT goes high. The bit is reset when RMS or RS_OCH bit is set in the Reset register.

2 DMA_ERR R 0 This bit is always reads a zero.

1 DMA_ABORT R 0 DMA_ABORT is set when an anomaly occurs during a DMA

transfer. These anomalies include DMA_ERROR, OCH, and when the Parity Error counter reaches its terminal count (except if the DSDT bit is set in reception mode in the UCR2). When DMA_ABORT is set, the DMAE bit in the UCR2 is reset (DMA transfer stopped). Bit is reset when the RMS or RS_DMAABORT bit is set in the Reset register.

0 TBE/RBF R 0 Transmit Buffer Empty/ Receive Buffer Full (TBE/RBF) is set when:

• Changing from reception mode to transmission mode

• A character has been transmitted by the UART.

• The reception FIFO is full.

TBE/RBF is reset when a character has been written in UTR, or when the RUR bit in the Command Register (CRE) is set High, or when changing from transmission mode to reception mode.

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

Offset 0x04 3030 FIFO Control Register (FCR)

31:12 Reserved

11:8 FIFO_THRES W 0000 Set the trigger level for FIFO level interrupt (FIFO_LEVEL_INT).

7 Reserved

6:4 PEC2:PEC0 W 000 PEC2, PEC1 and PEC0 determine the number of accepted parity

3:0 FL3:FL0 W 0000 FL3, FL2, FL1 and FL0 determine the depth of the FIFO.

In protocol T=0, if a correct character is received before the programmed error number is reached, then the error counter is reset. If the programmed number of allowed parity errors is reached, then the PE bit within the UART Status register is set as long as the RUS bit in the Reset register has not been set. In protocol T= 1, the error counter has no action. (PE is set at the first wrong received character). When DMA is enabled, (DMAE bit is set in UCR2), the bits FL3:FL0 must be reset.

Offset 0x04 3034 UART Transmit Register (UTR)

31:8 Reserved

7:0 UT7:UT0 W 0 When the controller wants to transmit a character to the card, it

Offset 0x04 3034 UART Receive Register (URR)

31:8 Reserved

…Continued

0000 means that the trigger level is not active. (FIFO_LEVEL_INT will not be set in the Mixed Status register. 0001 means that the trigger level is 1.

....

1111 means the trigger level is 15 (decimal).

Note: If the FIFO_THRES is higher or equal to the FIFO depth, the FIFO_LEVEL_INT bit will not be set in the Mixed Status register.

errors before setting the Parity Error (PE) bit (within UART Status Register and setting INT high in protocol T=0).

000 means that only 1 parity error will be accepted. 111 means 8 will be accepted.

0000 means the FIFO depth is 1.

....

1111 means the FIFO depth is 16.

writes the data in this register. The data transmission proceeds as follows:

• Starts at the end of this writing if the previous character has been transmitted and if the extra guard time has expired.

• Starts at the end of the extra guard time if this one has not expired.

• Does not start if the transmission of the previous character is not completed.

In synchronous mode the data UT0 is written on the IO line of the card when UTR has been written and remains unchanged.

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

7:0 UR7:UR0 R 0 When the controller wants to read a data from the card, it reads it

Offset 0x04 3038 UART Status Register (USR)

This register is used by the controller to monitor the activity of the ISO UART and the timeout counters.

31:8 Reserved

7:5 TO3:TO1 R 0 TO1 is set when counter1 has reached its terminal count.

4 EA R 0 Early Answer (EA) is high if the first start bit on I/O during ATR has

3 PE R 0 Parity Error (See PEC2:PEC0 bit field in 0x04 3030 FIFO Control

2 OVR R 0 Overrun (OVR) is high if the UART has received a new character

1 FER R 0 Framing Error (FER) is high when I/O was not in a high impedance

0 TBE/RBF R 0 Transmission Buffer Empty (TBE) is high when the UART is in

In T= 0 protocol, Parity Error (PE) is high if the UART has detected a number of received characters with parity error equal to the number written in PEC2, PEC1 and PEC0, or if a transmitted character has not been acknowledged by the card. In T = 0 protocol, a character received with a parity error is not stored in the FIFO. In T = 1 protocol, a character with parity error is stored in the FIFO and the parity error counter is not operating. If any of the status bits FER, OVR, PE, EA, TO1, TO2 and TO3 is set, then INT is high. The bit causing the interrupt is reset when the RUS bit is set in the Reset register. If TBE/RBF is set, and if the mask bit DISTBE/RBF within the UCR2 is not set, then INT is also high. TBE/RBF is reset when data has been written in the UART Transmit register, or when the RUR bit is set in the Command register, or when changing from transmission mode to reception mode.

…Continued

from this register in direct convention. When needed, this register may be tied to the FIFO whose length n is programmable between 1 and 8 (see FL2:FL0 bit in the FIFO Control register).

Reading this register does not affect the state of the UART, which means the TBE/RBF bit present in the USR and MSR registers is not affected and the FIFO pointers are not updated. To update the state of the UART, the controller must set the RUR bit in the Command register. In synchronous mode, the UR0 bit is directly linked to the IO line of the card.

TO2 is set when counter2 has reached its terminal count. TO3 is set when counter3 has reached its terminal count.

been detected between 200 and 384 CLK card pulses. (All activities on I/O line during the first 200 CLK card pulses with RST low or high are not taken into account.)

while the URR was full. In this case, at least one character has been lost.

state at 10.25 ETUs after a start bit.

transmission mode and when the controller may write the next character to transmit in the UTR. It is reset when the controller has written data in the transmit register, or when the T/R bit within the UCR1 has been reset either automatically or by software.

Reception Buffer Full (RBF) is high when the FIFO is full. The controller may set the RUR bit in the Command register, which clears the RBF bit after it has read the URR register. TBE and RBF share the same bit within the USR. (In transmission mode, the relevant one is TBE; in reception mode, the relevant one is RBF.)

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

Offset 0x04 303C DMA Write Address Register (DWA)

31:0 DWA31 - DWA0 R/W 0 Points to the memory address where the transfer is supposed to

Offset 0x04 3040 Command Register (CRE)

31:4 Reserved

3 RAF Resets the DMA autoflush mode.

2 SDA When this bit is set to 1, DMA autoflush mode is enabled. When in

1 FDG W 0 Flushes the uart dma_wr when set High. It is automatically reset by

0 RUR W 0 After it has read the UART Receive register, the controller may set

Offset 0x04 3FE0 SCIF_INT_STATUS

31:15 Reserved

14 FIFO_LEVEL_INT R 0

13 DMA_WR_LEVEL_INT R 0

12 DMA_RD_LEVEL_INT R 0

11 D ONE R 0

10 OCH R 0

9DMA_ERR R 0

8DMA_ABORT R 0

7TO3 R 0

6TO2 R 0

5TO1 R 0

4EA R 0

3PE R 0

2OVR R 0

1FER R 0

0 TBE/RBF R 0

Offset 0x04 3FE4 SCIF_INT_ENABLE

31:15 Reserved

14 ENA_FIFO_LEVEL_INT R/W 0 Enables FIFO_LEVEL_INT interrupt.

13 ENA_DMA_WR_LEVEL

_INT

R/W 0 Enables DMA_WR_LEVEL_INT interrupt.

…Continued

start (32-bit register) when the UART is in reception mode. This register must be programmed before setting the DMAE bit in the UCR2. The DMA transfer must start at a double word-aligned boundary.

reception mode, the dma_flush signal is asserted automatically if no character has been received 100us after the last received character.

hardware.

this bit in order to update:

• the FIFO pointers

• the TBE/RBF bit in the USR and MSR registers (when in reception mode).

See bit descriptions in 0x04 3030 Mixed Status Register (MSR).

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Table 8: Smartcard UART 1 Registers (Rev 2.04) …Continued

Bit Symbol Access Value Description

12 ENA_DMA_RD_LEVEL

_INT

11 ENA_DONE R/W 0 Enables DONE interrupt.

10 ENA_OCH R/W 0 Enables OCH interrupt.

9 ENA_DMA_ERR R/W 0 Enables DMA_ERR interrupt

8 ENA_DMA_ABORT R/W 0 Enables DMA_ABORT interrupt.

7 ENA_TO3 R/W 0 Enables TO3 interrupt.

6 ENA_TO2 R/W 0 Enables TO2 interrupt.

5 ENA_TO1 R/W 0 Enables TO1 interrupt.

4 ENA_EA R/w 0 Enables EA interrupt.

3 ENA_PE R/W 0 Enables PE interrupt.

2 ENA_OVR R/W 0 Enables OVR interrupt.

1 ENA_FER R/W 0 Enables FER interrupt.

0 ENA_TBE/RBF R/W 0 Enables TBE/RBF interrupt.

Offset 0x04 3FE8 SCIF_INT_CLEAR

31:15 Reserved

14 CLR_FIFO_LEVEL_INT R/W 0 Clears FIFO_LEVEL_INT interrupt.

13 CLR_DMA_WR_LEVEL

_INT

12 CLR_DMA_RD_LEVEL_

INT

11 CLR_DONE R/W 0 Clears DONE interrupt.

10 CLR_OCH R/W 0 Clears OCH interrupt.

9 CLR_DMA_ERR R/W 0 Clears DMA_ERR interrupt.

8 CLR_DMA_ABORT R/W 0 Clears DMA_ABORT interrupt.

7 CLR_TO3 R/W 0 Clears TO3 interrupt.

6 CLR_TO2 R/W 0 Clears TO2 interrupt.

5 CLR_TO1 R/W 0 Clears TO1 interrupt.

4 CLR_EA R/W 0 Clears EA interrupt.

3 CLR_PE R/W 0 Clears PE interrupt.

2 CLR_OVR R/W 0 Clears OVR interrupt.

1 CLR_FER R/W 0 Clears FER interrupt.

0 CLR_TBE/RBF R/W 0 Clears TBE/RBF interrupt.

Offset 0x04 3FEC SCIF_INT_SET

31:15 Reserved

14 SET_FIFO_LEVEL_INT R/W 0 Sets FIFO_LEVEL_INT interrupt.

13 SET_DMA_WR_LEVEL

_INT

12 SET_DMA_RD_LEVEL_

INT

R/W 0 Enables DMA_RD_LEVEL_INT interrupt.

R/W 0 Clears DMA_WR_LEVEL_INT interrupt.

R/W 0 Clears DMA_RD_LEVEL_INT interrupt.

R/W 0 Sets DMA_WR_LEVEL_INT interrupt.

R/W 0 Sets DMA_RD_LEVEL_INT interrupt.

PNX8550

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Table 8: Smartcard UART 1 Registers (Rev 2.04)

Bit Symbol Access Value Description

11 SET_DONE R/W 0 Sets DONE interrupt.

10 SET_OCH R/W 0 Sets OCH interrupt.

9 SET_DMA_ERR R/W 0 Sets DMA_ERR interrupt.

8 SET_DMA_ABORT R/W 0 Sets DMA_ABORT interrupt.

7 SET_TO3 R/W 0 Sets TO3 interrupt.

6 SET_TO2 R/W 0 Sets TO2 interrupt.

5 SET_TO1 R/W 0 Sets TO1 interrupt.

4 SET_EA R/W 0 Sets EA interrupt.

3 SET_PE R/W 0 Sets PE interrupt.

2 SET_OVR R/W 0 Sets OVR interrupt.

1 SET_FER R/W 0 Sets FER interrupt.

0 SET_TBE/RBF R/W 0 Sets TBE/RBF interrupt.

Offset 0x04 3FF4 SCIF_POWERDOWN

31 PWDN R/W When set, access to smartcard interface registers is forbidden,

30:1 Reserved 0

Offset 0x04 3FFC SCIF_MODULE_ID

31:0 Module ID R 0x01060

000

…Continued

except for SCIF_MODULE_ID and SCIF_POWERDOWN.

Smartcard Interface Identity code.

Table 9: Smartcard UART 2 Registers (Rev 2.04)

Bit Symbol Access Value Description

Offset 0x04 4000 Reset Register (RER)

31:19 Reserved W 0

18 RS_FIFO_LEVEL_INT W 0 Resets the bit FIFO_LEVEL_INT in Mixed Status register.

RS_FIFO_LEVEL_INT is automatically reset by hardware.

17 RS_DMA_WR_LEVEL_

INT

16 RS_DMA_RD_LEVEL_

INT

15 RS_DONE W 0 Resets the bit DONE in Mixed Status register. RS_DONE is

14 RS_BGT W 0 Resets the bit BGT in Mixed Status register. RS_BGT is

13 RS_OCH W 0 Resets the bit OCH in Mixed Status register. RS_OCH is

12 RS_DMAERR W 0 Resets the bit DMA_ERR in Mixed Status register. RS_DMAERR is

11 RS_DMAABORT W 0 Resets the bit DMA_ABORT in Mixed Status register.

10 RS_TO3 W 0 Resets the bit TO3 in UART Status register. RS_TO3 is

W 0 Resets the bit DMA_WR_LEVEL_INT in Mixed Status register.

RS_DMA_WR_LEVEL_INT is automatically reset by hardware.

W 0 Resets the bit DMA_RD_LEVEL_INT in Mixed Status register.

RS_DMA_RD_LEVEL_INT is automatically reset by hardware.

automatically reset by hardware.

RS_DMAABORT is automatically reset by hardware.

automatically reset by hardware.

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