Philips AN10216-01 Application note
INTEGRATED CIRCUIT
S
AN10216-01 I
2
C Manual
APPLICATION NOTE
AN10216-01
I2C MANUAL
Abstract – The I
why the I
works, previous limitations/solutions, comparison to the SMBus, Intelligent Platform
Management Interface implementations, review of the different I
available and patent/royalty information. The I
hour TecForum at DesignCon 2003 in San Jose, CA on 27 January 2003.
2
C bus should be considered, technical detail of the I2C bus and how it
Jean-Marc Irazabal –
Steve Blozis – I
Specialty Logic Product Line
Logic Product Group
2
C Manual provides a broad overview of the various serial buses,
2
2
C Manual was presented during the 3
C devices that are
I2C Technical Marketing Manager
2
C International Product Manager
Philips Semiconductors March 24, 2003
1
AN10216-01 I2C Manual
TABLE OF CONTENTS
TABLE OF CONTENTS ...................................................................................................................................................2
OVERVIEW .......................................................................................................................................................................4
DESCRIPTION..................................................................................................................................................................... 4
SERIAL BUS OVERVIEW............................................................................................................................................... 4
UART OVERVIEW.............................................................................................................................................................6
SPI OVERVIEW.................................................................................................................................................................. 6
CAN OVERVIEW ...............................................................................................................................................................7
USB OVERVIEW................................................................................................................................................................ 9
1394 OVERVIEW ............................................................................................................................................................. 10
I2C OVERVIEW ................................................................................................................................................................11
SERIAL BUS COMPARISON SUMMARY .............................................................................................................................12
I2C THEORY OF OPERATION .................................................................................................................................... 13
I2C BUS TERMINOLOGY................................................................................................................................................... 13
START AND STOP CONDITIONS ....................................................................................................................................14
HARDWARE CONFIGURATION ...............................................................................................................................14
BUS COMMUNICATION.............................................................................................................................................14
TERMINOLOGY FOR BUS TRANSFER ................................................................................................................................15
I2C DESIGNER BENEFITS ................................................................................................................................................. 17
I2C MANUFACTURERS BENEFITS .....................................................................................................................................17
OVERCOMING PREVIOUS LIMITATIONS ............................................................................................................. 18
ADDRESS CONFLICTS ......................................................................................................................................................18
CAPACITIVE LOADING > 400 PF (ISOLATION) .................................................................................................................19
VOLTAGE LEVEL TRANSLATION .....................................................................................................................................20
INCREASE I2C BUS RELIABILITY (SLAVE DEVICES).........................................................................................................21
INCREASING I2C BUS RELIABILITY (MASTER DEVICES)..................................................................................................22
CAPACITIVE LOADING > 400 PF (BUFFER)...................................................................................................................... 22
LIVE INSERTION INTO THE I2C BUS ................................................................................................................................. 24
LONG I2C BUS LENGTHS .................................................................................................................................................25
PARALLEL TO I2C BUS CONTROLLER ..............................................................................................................................25
DEVELOPMENT TOOLS AND EVALUATION BOARD OVERVIEW..................................................................26
PURPOSE OF THE DEVELOPMENT TOOL AND I2C EVALUATION BOARD ...........................................................................26
WIN-I2CNT SCREEN EXAMPLES.....................................................................................................................................28
HOW TO ORDER THE I2C 2002-1A EVALUATION KIT .....................................................................................................31
COMPARISON OF I2C WITH SMBUS........................................................................................................................31
I2C/SMBUS COMPLIANCY ...............................................................................................................................................31
DIFFERENCES SMBUS 1.0 AND SMBUS 2.0 ....................................................................................................................32
INTELLIGENT PLATFORM MANAGEMENT INTERFACE (IPMI)....................................................................32
INTEL SERVER MANAGEMENT......................................................................................................................................... 33
PICMG ........................................................................................................................................................................... 33
VMEBUS.........................................................................................................................................................................34
I2C DEVICE OVERVIEW ..............................................................................................................................................35
TV RECEPTION................................................................................................................................................................36
RADIO RECEPTION .......................................................................................................................................................... 36
2
AN10216-01 I2C Manual
UDIO PROCESSING ........................................................................................................................................................ 37
A
DUAL TONE MULTI-FREQUENCY (DTMF)......................................................................................................................37
LCD DISPLAY DRIVER....................................................................................................................................................37
LIGHT SENSOR ................................................................................................................................................................ 38
REAL TIME CLOCK/CALENDAR .......................................................................................................................................38
GENERAL PURPOSE I/O EXPANDERS ...............................................................................................................................38
LED DIMMERS AND BLINKERS .......................................................................................................................................40
DIP SWITCH....................................................................................................................................................................42
MULTIPLEXERS AND SWITCHES.......................................................................................................................................43
VOLTAGE LEVEL TRANSLATORS .....................................................................................................................................45
BUS REPEATERS AND HUBS ............................................................................................................................................45
HOT SWAP BUS BUFFERS ................................................................................................................................................45
BUS EXTENDERS .............................................................................................................................................................46
ELECTRO-OPTICAL ISOLATION........................................................................................................................................47
RISE TIME ACCELERATORS .............................................................................................................................................47
PARALLEL BUS TO I2C BUS CONTROLLER ...................................................................................................................... 48
DIGITAL POTENTIOMETERS .............................................................................................................................................48
ANALOG TO DIGITAL CONVERTERS ................................................................................................................................48
SERIAL RAM/EEPROM ................................................................................................................................................. 49
HARDWARE MONITORS/TEMP & VOLTAGE SENSORS .....................................................................................................49
MICROCONTROLLERS ......................................................................................................................................................49
I2C PATENT AND LEGAL INFORMATION.............................................................................................................. 50
ADDITIONAL INFORMATION ...................................................................................................................................50
APPLICATION NOTES..................................................................................................................................................50
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AN10216-01 I2C Manual
OVERVIEW
Description
Philips Semiconductors developed the I2C bus over 20 years ago and has an extensive collection of specific use and
general purpose devices. This application note was developed from the 3 hour long I
at DesignCon 2003 in San Jose, CA on 27 January 2003 and provides a broad overview of how the I2C bus compares to
other serial buses, how the I2C bus works, ways to overcome previous limitations, new uses of I2C such as in the
Intelligent Platform Management Interface, overview of the various different categories of I
information. Full size Slides are posted as a PDF file on the Philips Logic I2C collateral web site as DesignCon 2003
TecForum I2C Bus Overview PDF file. Place holder and title slides have been removed from this application note and
some slides with all text have been incorporated into the application note speaker notes.
three shared signal lines, for bit timing, data, and R/W.
Serial Bus Overview
C
om
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uni
c
a
t
i
on
s
r
e
m
u
s
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o
C
The selection of communicating partners is made with
one separate wire for each chip. As the number of chips
grows, so do the selection wires. The next stage is to
use multiplexing of the selection wires and call them an
address bus.
If there are 8 address wires we can select any one of
e
v
i
t
o
m
o
t
u
A
SERIAL
BUSES
IEEE1394
256 devices by using a ‘one of 256’ decoder IC. In a
parallel bus system there could be 8 or 16 (or more)
data wires. Taken to the next step, we can share the
function of the wires between addresses and data but it
SPI
DesignCon 2003 TecForum I2C Bus Overview
Slide 5
UART
S
BBUUS
I
n
d
u
s
t
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l
5
starts to take quite a bit of hardware and worst is, we
still have lots of wires. We can take a different
approach and try to eliminate all except the data wiring
itself. Then we need to multiplex the data, the selection
(address), and the direction info - read/write. We need
to develop relatively complex rules for that, but we save
on those wires. This presentation covers buses that use
only one or two data lines so that they are still attractive
for sending data over reasonable distances - at least a
General concept for Serial communications
SCL
SDA
DATA
• A point to point communication does not require a Select control signal
• An asynchronous communication does not have a Clock signal
• Data, Select and R/W signals can share the same line, depending on the protocol
• Notice that Slave 1 cannot communicate with Slave 2 or 3 (except via the ‘master’)
Only the ‘master’ can start communicating. Slaves can ‘only speak when spoken to’
DesignCon 2003 TecForum I2C Bus Overview
Shift Register
Parallel to Serial
“MASTER”
select 3
select 2
select 1
READ
or
WRITE?
Shift Reg#
enable enable
// to Ser.
R/W
SLAVE 1
R/W
SLAVE 2
Shift Reg#
// to Ser.
enable
R/W
SLAVE 3
Shift Reg#
// to Ser.
6
few meters, but perhaps even km.
Typical Signaling Characteristics
RS422/485
PECL
LVPECL
Slide 6
Buses come in two forms, serial and parallel. The data
DesignCon 2003 TecForum I2C Bus Overview
and/or addresses can be sent over 1 wire, bit after bit, or
over 8 or 32 wires at once. Always there has to be some
way to share the common wiring, some rules, and some
synchronization. Slide 6 shows a serial data bus with
Devices can communicate differentially or single ended
with various signal characteristics as shown in Slide 7.
2
C Overview TecForum presentation
2
C devices and patent/royalty
LVTTL
I2C
2
C
I
1394
LVDS
CML
3.3 V
5 V
LVT
LVC
Slide 7
SMBus
2.5 V
I2C
GTL+
GTL
GTLP
7
4
AN10216-01 I2C Manual
2
Transmission Standards
2500
GTLP
BTL
ETL
General
Purpose
Logic
Data Transfer Rate (Mbps)
0.5
DesignCon 2003 TecForum I2C Bus Overview
The various data transmission rates vs length or cable
or backplane length of the different transmission
standards are shown in Slide 8.
Speed of various connectivity methods (bits/sec)
CAN (1 Wire) 33 kHz (typ)
I
C (‘Industrial’, and SMBus)
SPI
CAN (fault tolerant)
2
I
C
CAN (high speed)
2
I
C ‘High Speed mode’
USB (1.1)
SCSI (parallel bus) 40 MHz
Fast SCSI 8-80 MHz
Ultra SCSI-3 18-160 MHz
Firewire / IEEE1394 400 MHz
Hi-Speed USB (2.0)
DesignCon 2003 TecForum I2C Bus Overview
Increasing fast serial transmission specifications are
shown in Slide 9. Proper treatment of the 480 MHz
version of USB - trying to beat the emerging 400 MHz
1394a spec - that is looking to an improved ‘b’ spec - etc is beyond the scope of this presentation. Philips is
developing leading-edge components to support both
USB and 1394 buses.
Today the path forward in USB is built on “OTG” (On
The Go) applications but the costs and complexity of
this are probably beyond the limits of many customers.
If designers are identified as designing for large
international markets then please contact the USB
group for additional support, particularly of Host and
OTG solutions. Apologies for inclusion of the parallel
SCSI bus. It is intended for comparison purposes and
655
400
CML
1394.a
35
10
1
0.1
I2C
0
RS-232
L
V
D
S
=
E
R
C
S
L
-
6
/
P
4
4
E
C
L
/
L
V
P
E
C
L
RS-422
RS-485
RS-423
10
100
Cable Length (meters)Backplane Length (meters)
1000
8
Slide 8
100 kHz
110 kHz (original speed)
125 kHz
400 kHz
1 MHz
3.4 MHz
1.5 MHz or 12 MHz
480 MHz
9
Slide 9
also because it may be used within the PC software as a
general data path that USB drivers can use.
Terminology for USB: The use of older terms such as
the spec version 1.1 and 2.0 is now discouraged. There
is just “USB” (meaning the original 12 Mbits/sec and
1.5 Mbits/sec speeds of USB version 1.1) and Hi-Speed
USB meaning the faster 480 Mbits/sec option included
in spec version 2.0. Parts conforming to or capable of
the 480 Mbits/sec are certified as Hi-Speed USB and
will then feature the logo with the red stripe “Hi-Speed”
fitted above the standard USB logo. The reason to avoid
use of the new spec version 2.0 as a generic name is
that this version includes all the older versions and
speeds as well as the new Hi-Speed specs. So USB 2.0
compliance does NOT imply Hi-Speed (480 Mbits/sec).
ICs can be compliant with USB 2.0 specifications yet
only be capable of the older ‘full speed’ or 12
Mbits/sec.
Bus characteristics compared
Data rate
Bus
2
I
C 400k 2
w ith buffer
I2C
high speed
I2C
1 wire
CAN
diff erential
CAN
(low -speed, 1.1)
US B
(full -speed, 1.1)
USB
(2.0)
Hi- S pe e d US B
IEEE-1394 100 to 400M+ 72
DesignCon 2003 TecForum I2C Bus Overview
(bits / sec)
400k 100
3.4M 0.5
33k 100
5k 10km
125k 500
1M 40
1.5M 3
1.5/12M
480M
Length
(meters) Length limiting factor
w iring capacitance
propagation delays
w iring capacitance
total capacitance
propagation delays
cable specs
5 cables linking 6 nodes
25
(5m cable node to node)
16 hops, 4.5M each
Slide 10
In Slide 10 we look at three important characteristics:
• Speed, or data rate
• Number of devices allowed to be connected (to
share the bus wires)
• Total length of the wiring
Numbers are supposed to be realistic estimates but are
based on meeting bus specifications. But rules are made
to be broken! When buffered, I
wiring propagation delays but it is still possible to run
much longer distances by using slower clock rates and
maybe also compromising the bus rise and fall-time
specifications on the buffered bus because it is not
bound to conform to I2C specifications.
The figure in Slide 10 limiting I
propagation delays is conservative and allows for
published response delays in chips like older E2
memories. Measured chip responses are typically <
700 ns and that allows for long cable delays and/or
Nodes
Typ.number
20
any
5
32
load resistance and
transc eiver cur rent
100
2
bus and hub specs
127
63
2
C can be limited by
2
C range by
Node number
limiting factor
400pF max
no limi t
100pF max
drive
bus specs
6-bit address
10
5
AN10216-01 I2C Manual
operation well above 100 kHz with the P82B96. The
theoretical round-trip delay on 100 m of cable is only
approx 1 µs and the maximum allowed delay, assuming
zero delays in ICs, is about 3 µs at 100 kHz. The
figures for CAN are not quite as conservative; they are
the ‘often quoted values’. The round trip delay in 10
km cable is about 0.1 ms while 5 kbps implies 0.2 ms
nominal bit time, and a need to sample during the
second half of the bit time. That is under the user’s
control, but needs attention.
USB 2 and IEEE-1394 are still ‘emerging standards’.
Figures quoted may not be practical; they are just based
on the specification restrictions.
UART Overview
What is UART?
(Universal Asynchronous Receiver Transmitter)
• Communication standard implemented in the 60’s.
• Simple, universal, well understood and well supported.
• Slow speed communication standard: up to 1 Mbits/s
• Asynchronous means that the data clock is not included in
the data: Sender and Receiver must agree on timing
parameters in advance.
• “Start” and “Stop” bits indicates the data to be sent
• Parity information can also be sent
0 1 2 3 4 5 6 7
Start bit
DesignCon 2003 TecForum I2C Bus Overview
UARTs (Universal Asynchronous Receiver
Transmitter) are serial chips on your PC motherboard
(or on an internal modem card). The UART function
may also be done on a chip that does other things as
well. On older computers like many 486's, the chips
were on the disk IO controller card. Still older
computers have dedicated serial boards.
The UARTs purpose is to convert bytes from the PC's
parallel bus to a serial bit-stream. The cable going out
of the serial port is serial and has only one wire for each
direction of flow. The serial port sends out a stream of
bits, one bit at a time. Conversely, the bit stream that
enters the serial port via the external cable is converted
to parallel bytes that the computer can understand.
UARTs deal with data in byte-sized pieces, which is
conveniently also the size of ASCII characters.
Say you have a terminal hooked up to your PC. When
you type a character, the terminal gives that character to
its transmitter (also a UART). The transmitter sends
that byte out onto the serial line, one bit at a time, at a
specific rate. On the PC end, the receiving UART takes
8 Bit Data
Slide 11
Stop bit
Parity Information
11
all the bits and rebuilds the (parallel) byte and puts it in
a buffer.
Along with converting between serial and parallel, the
UART does some other things as a byproduct (side
effect) of its primary task. The voltage used to represent
bits is also converted (changed). Extra bits (called start
and stop bits) are added to each byte before it is
transmitted. Also, while the flow rate (in bytes/s) on the
parallel bus speed inside the computer is very high, the
flow rate out the UART on the serial port side of it is
much lower. The UART has a fixed set of rates
(speeds) that it can use at its serial port interface.
UART - Applications
Public / Private
Modemtr
Modem
x
Address
Data
l
Memory
Memory
DUART
DUART
SC28L92
SC28L92
LAN application
Telephone / Internet
Network
al Interf
Seri ace
Analog or Digital
WAN application
Cash
register
Interface to
Server
Bar code
reader
Parallel
Interface
t
t
Modem
r
r
Modem
x
x
Serial Interface
• Entertainment
• Home Security
• Robotics
• Automotive
• Cellular
• Medical
Client
Client
Processor
Processor
t
t
Datacom
Datacom
r
r
controller
controller
x
x
Server
Server
Processor
Datacom
Datacom
controller
controller
Printer
t
r
x
Micro
contr.
UART
Digita
t
r
x
Micro
contr.
Processor
Appliance Terminals
Display
DesignCon 2003 TecForum I2C Bus Overview
Slide 12
SPI Overview
What is SPI?
• Serial Peripheral Interface (SPI) is a 4-wire full-duplex
synchronous serial data link:
– SCLK: Serial Clock
– MOSI: Master Out Slave In - Data from Master to Slave
– MISO: Master In Slave Out - Data from Slave to Master
– SS: Slave Select
• Originally developed by Motorola
• Used for connecting peripherals to each other and to
microprocessors
• Shift register that serially transmits data to other SPI devices
• Actually a “3 + n” wire interface with n = number of devices
• Only one master active at a time
• Various Speed transfers (function of the system clock)
DesignCon 2003 TecForum I2C Bus Overview
Slide 13
The Serial Peripheral Interface (SPI) circuit is a
synchronous serial data link that is standard across
many Motorola microprocessors and other peripheral
chips. It provides support for a high bandwidth (1 mega
baud) network connection amongst CPUs and other
devices supporting the SPI.
12
13
6
AN10216-01 I2C Manual
SPI - How are the connected devices recognized?
SCLK
MOSI
MISO
SS 1
SS 2
SS 3
MASTER
• Simple transfer scheme, 8 or 16 bits
• Allows many devices to use SPI through the addition of a shift register
• Full duplex communications
• Number of wires proportional to the number of devices in the bus
DesignCon 2003 TecForum I2C Bus Overview
Slide 14
The SPI is essentially a “three-wire plus slave selects”
serial bus for eight or sixteen bit data transfer
applications. The three wires carry information between
devices connected to the bus. Each device on the bus
acts simultaneously as a transmitter and receiver. Two
of the three lines transfer data (one line for each
direction) and the third is a serial clock. Some devices
may be only transmitters while others only receivers.
Generally, a device that transmits usually possesses the
capability to receive data also. An SPI display is an
example of a receive-only device while EEPROM is a
receiver and transmit device.
The devices connected to the SPI bus may be classified
as Master or Slave devices. A master device initiates an
information transfer on the bus and generates clock and
control signals. A slave device is controlled by the
master through a slave select (chip enable) line and is
active only when selected. Generally, a dedicated select
line is required for each slave device. The same device
can possess the functionality of a master and a slave but
at any point of time, only one master can control the
bus in a multi-master mode configuration. Any slave
device that is not selected must release (make it high
impedance) the slave output line.
The SPI bus employs a simple shift register data
transfer scheme: Data is clocked out of and into the
active devices in a first-in, first-out fashion. It is in this
manner that SPI devices transmit and receive in full
duplex mode.
All lines on the SPI bus are unidirectional: The signal
on the clock line (SCLK) is generated by the master and
is primarily used to synchronize data transfer. The
master-out, slave-in (MOSI) line carries data from the
master to the slave and the master-in, slave-out (MISO)
line carries data from the slave to the master. Each
slave device is selected by the master via individual
select lines. Information on the SPI bus can be
transferred at a rate of near zero bits per second to 1
Mbits per second. Data transfer is usually performed in
eight/sixteen bit blocks. All data transfer is
SCLK
MOSI
MISO
SS
SCLK
MOSI
MISO
SS
SCLK
MOSI
MISO
SS
SLAVE 1
SLAVE 2
SLAVE 3
14
synchronized by the serial clock (SCLK). One bit of
data is transferred for each clock cycle. Four clock
modes are defined for the SPI bus by the value of the
clock polarity and the clock phase bits. The clock
polarity determines the level of the clock idle state and
the clock phase determines which clock edge places
new data on the bus. Any hardware device capable of
operation in more than one mode will have some
method of selecting the value of these bits.
CAN Overview
What is CAN ? (Controller Area Network)
• Proposed by Bosch with automotive applications in mind
(and promoted by CIA - of Germany - for industrial
applications)
• Relatively complex coding of the messages
• Relatively accurate and (usually) fixed timing
• All modules participate in every communication
• Content-oriented (message) addressing scheme
Filter Filter
Frame
DesignCon 2003 TecForum I2C Bus Overview
Slide 15
CAN objective is to achieve reliable communications in
relatively critical control system applications e.g.
engine management or anti-lock brakes. There are
several aspects to reliability - availability of the bus
when important data needs to be sent, the possibility of
bits in a message being corrupted by noise etc., and
electrical/mechanical failure modes in the wiring.
At least a ceramic resonator and possibly a quartz
crystal are needed to generate the accurate timing
needed. The clock and data are combined and 6 ‘high’
bits in succession is interpreted as a bus error. So the
clock and bit timings are important. All connected
modules must use the same timings. All modules are
looking for any error in the data at any point on the
wiring and will report that error so the message can be
re-sent etc.
15
7
AN10216-01 I2C Manual
Start Of Frame
Identifier
Remote Transmission Request
• Very intelligent controller requested to generate such protocol
DesignCon 2003 TecForum I2C Bus Overview
CAN protocol
Identifier Extension
Data Length Code
Data
Cyclic Redundancy Check
Acknowledge
End Of Frame
Intermission Frame
Space
16
Slide 16 Slide 17
2
Like I
C, the CAN bus wires are pulled by resistors to
their resting state called a ‘recessive’ state. When a
transceiver drives the bus it forces a voltage called the
‘dominant’ state. The identifier indicates the meaning
of the data, not the intended recipient. So all nodes
receive and ‘filter’ this identifier and can decide
whether to act on the data or not. So the bus is using
‘multicast’ - many modules can act on the message, and
all modules are checking the message for transmission
errors. Arbitration is ‘bit wise’ like I
2
C - the module
forcing a ‘1’ beats a module trying for a ‘0’ and the
loser withdraws to try again later.
- DLC: data length code
- CRC: cyclic redundancy check (remainder of a
division calculation). All devices that pass the CRC
will acknowledge or will generate an error flag
after the data frame finishes.
- ACK: acknowledge.
- Error frame: (at least) 6 consecutive dominant bits
then 7 recessive bits.
A message ‘filter’ can be programmed to test the 11-bit
identifier and one or two bytes of the data (In general
up to 32 bits) to decide whether to accept the message
and issue an interrupt. It could also look at all of the
29-bit identifier.
CAN Bus Advantages
• Accepted standard for Automotive and industrial applications
– interfacing between various vendors easier to implement
• Freedom to select suitable hardware
– differential or 1 wire bus
• Secure communications, high Level of error detection
– 15 bit CRC messages (Cyclic Redundancy Check)
– Reporting / logging
– Faulty devices can disconnect themselves
– Low latency time
– Configuration flexibility
• High degree of EMC immunity (when using Si-On-Insulator
technology)
DesignCon 2003 TecForum I2C Bus Overview
2
I
C products from many manufacturers are all
compatible but CAN hardware will be selected and
dedicated for each particular system design. Some CAN
transceivers will be compatible with others, but that is
more likely to be the exception than the rule. CAN
designs are usually individual systems that are not
intended to be modified. Philips parts greatly enhance
the feature of reliability by their ability to use partbroken bus wiring and disconnect themselves if they are
recording too many bus errors.
There are several aspects to reliability - availability of
the bus when important data needs to be sent, the
possibility of bits in a message being corrupted by noise
etc., and the consequences of electrical/mechanical
failure modes in the wiring. All these aspects are treated
seriously by the CAN specifications and the suppliers
of the interface ICs - for example Philips believes
conventional high voltage IC processes are not good
enough and uses Silicon-on-insulator technology to
increase ruggedness and avoid the alternative of using
common-mode chokes for protection. To give an
example of immunity, a transceiver on 5 V must be able
to cope with jump-start and load-dump voltages on its
supply or bus wires. That is 40 V on the supply and +/40 V on the bus lines, plus transients of –150 V/+100 V
capacitively coupled from a pulse generator in a test
circuit!
17
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AN10216-01 I2C Manual
USB Overview
What is USB ? (Universal Serial Bus)
• Originally a standard for connecting PCs to peripherals
• Defined by Intel, Microsoft, …
• Intended to replace the large number of legacy ports in the PC
• Single master (= Host) system with up to 127 peripherals
• Simple plug and play; no need to open the PC
• Standardized plugs, ports, cables
• Has over 99% penetration on all new PCs
• Adapting to new requirements for flexibility of Host function
– New Hardware/Software allows dynamic exchanging of Host/Slave
roles
– PC is no longer the only system Host. Can be a camera or a printer.
DesignCon 2003 TecForum I2C Bus Overview
Slide 18
USB is the most complex of the buses presented here.
While its hardware and transceivers are relatively
simple, its software is complex and is able to efficiently
service many different applications with very different
data rates and requirements. It has a 12 Mbps rate (with
200 Mbps planned) over a twisted pair with a 4-pin
connector (2 wires are power supply). It also is limited
to short distances of at most 5 meters (depends on
configuration). Linux supports the bus, although not all
devices that can plug into the bus are supported. It is
synchronous and transmits in special packets like a
network. Just like a network, it can have several devices
attached to it. Each device on it gets a time-slice of
exclusive use for a short time. A device can also be
guaranteed the use of the bus at fixed intervals. One
device can monopolize it if no other device wants to use
it.
18
USB Bus Advantages
• Hot pluggable, no need to open cabinets
• Automatic configuration
• Up to 127 devices can be connected together
• Push for USB to become THE standard on PCs
– standard for iMac, supported by Windows, now on > 99%of PCs
• Interfaces (bridges) to other communication channels
exist
– USB to serial port (serial port vanishing f rom laptops)
– USB to IrDA or to Ethernet
• Extreme volumes force down IC and hardware prices
• Protocol is evolving fast
DesignCon 2003 TecForum I2C Bus Overview
Slide 20
USB aims at mass-market products and design-ins may
be less convenient for small users. The serial port is
vanishing from the laptop and gone from iMac. There
are hardware bridges available from USB to other
communication channels but there can be higher power
consumption to go this way. Philips is innovating its
USB products to minimize power and offer maximum
flexibility in system design.
Versions of USB specification
• USB 1.1
– Establish ed, large PC peripheral markets
– Well controlled hardware, special 4-pin plugs/sockets
– 12MBits/sec (normal) or 1.5Mbits/sec (low speed) data rate
• USB 2.0
– Challenging IEEE1394/Firewire for video possibilities
– 480 MHz clock for Hi-Speed means it’s real “UHF” transmission
– Hi-Speed option needs more complex chip hardware and software
– Hi-Speed component prices about x 2 compared to full speed
20
USB Topology (original concept, USB1.1, USB2.0)
¾ Host
− One PC host per system
− Provides power to peripherals
¾ Hub
− Provides ports for connecting more
peripheral devices.
− Provides power, terminations
− External supply or Bus Powered
¾ Device, Interfaces and Endpoints
− Device is a collection of data
interface(s)
− Interface is a collection of
endpoints (data channels)
− Endpoint associated with FIFO(s) -
for data I/O interfacing
DesignCon 2003 TecForum I2C Bus Overview
Slide 19
Slide 19 shows a typical USB configuration.
Host
PC
5m
Device
5m
5m
5m
Hub
Monitor
5m
• USB “OTG” (On The Go) Supplement
– New hardware - smaller 5-pin plugs/sockets
– Lower power (reduced or no bus-power ing)
DesignCon 2003 TecForum I2C Bus Overview
21
Slide 21
For USB 1.1 and 2.0 the hardware is well established.
The shape of the plug/socket at Host end is different
from the shape at the peripheral end. USB is always a
single point-to-point link over the cable. To allow
connection of multiple peripherals a HUB is introduced.
The Hub functions to multiplex the data from the
19
‘downstream’ peripherals into one ‘upstream’ data
linkage to the Host. In Hi-Speed systems it is necessary
for the system to start communicating as a normal USB
1.1 system and then additional hardware (faster
transceivers etc) is activated to allow a higher speed.
The Hi-Speed system is much more complex
(hardware/software) than normal USB (1.1). For USB
9
AN10216-01 I2C Manual
and Hi-Speed the development of ‘stand-alone’ Host
ICs such as ISP1161 and ISP1561 allowed the Host
function to be embedded in products such as Digital
Still Cameras or printers so that more direct transfer of
data was possible without using the path Camera → PC
→ Printer under control of the PC as the host. That two
step transfer involves connecting the camera to the PC
(one USB cable) and also the PC to the printer (second
USB cable). The goal is to do without the PC.
The next step involved the shrinking of the USB
connector hardware, to make it more compatible with
small products like digital cameras, and making
provision (extra pin) for dynamic exchanging of Host
and slave device functions without removing the USB
cable for reversing the master/slave connectors. The
new hardware and USB specification version is called
“On The Go” (OTG). The OTG specification no longer
requires the Host to provide the 1/2 A power supply to
peripherals and indeed allows arbitration to determine
whether Host or peripheral (or neither) will provide the
system power.
1394 Overview
What is IEEE1394 ?
• A bus standard devised to handle the high data throughput
requirements of MPEG-2 and DVD
– Video requires constant transfer rates with guaranteed bandwidth
– Data rates 100, 200, 400 Mbits/sec and looking to 3.2 Gb/s
• Also known as “Firewire” bus (registered trademark of Apple)
• Automatically re-configures itself as each device is added
– True plug & pl ay
– Hot-plugging of devices allowed
• Up to 63 devices, 4.5 m cable ‘hops’, with max. 16 hops
• Bandwidth guaranteed
DesignCon 2003 TecForum I2C Bus Overview
Slide 22
1394 may claim to be more proven or established than
USB but both are ‘emerging’ specifications that are
trying to out-do each other! Philips strongly supports
BOTH. 1394 was chosen by Philips as the bus to link
set-top boxes, DVD, and digital TVs. 1394 has an ’a’
version taking it to 400 Mb/sec and more recently a ‘b’
version for higher speed and to allow longer cable runs,
perhaps 100 meter hops!
1394 sends information over a PAIR of twisted pairs.
One for data, the other is the clocking strobe. The clock
is simply recovered by an Ex-Or of the data and strobe
line signals. No PLL is needed. There is provision for
lots of remote device powering via the cable if the 6-pin
plug connection version is used. The power wires are
22
specified to well over 1A at 8-30 volts (approx) leading to some unkind references to a ‘fire’ wire!
1394 software or message format consists of timeslots
within which the data is sent in blocks or ‘channels’.
For real-time data transfer it is possible to guarantee the
availability of one or more channels to guarantee a
certain data rate. This is important for video because
it’s no good sending a packet of corrected data after a
blank has appeared on the screen!
Microsoft says, “IEEE 1394 defines a single
interconnection bus that serves many purposes and user
scenarios. In addition to its adoption by the consumer
electronics industry, PC vendors—including Compaq,
Dell, IBM, Fujitsu, Toshiba, Sony, NEC, and
Gateway—are now shipping Windows-based PCs with
1394 buses.
The IEEE 1394 bus complements the Universal Serial
Bus (USB) and is particularly optimized for connecting
digital media devices and high-speed storage devices to
a PC. It is a peer-to-peer bus. Devices have more builtin intelligence than USB devices, and they run
independently of the processor, resulting in better
performance.
The 100-, 200-, and 400-Mbps transfer rates currently
specified in the IEEE 1394a standard and the proposed
enhancements in 1394b are well suited to meeting the
throughput requirements of multiple streaming
input/output devices connected to a single PC. The
licensing fee for use of patented IEEE 1394 technology
has been established at US $0.25 per system.
With connectivity for storage, scanners, printers, and
other types of consumer A/V devices, IEEE 1394 gives
users all the benefits of a great legacy-free connector—
a true Plug and Play experience and hassle-free PC
connectivity.”
1394 Topology
• Physical layer
– Analog interface to the cable
– Simple repeater
– Performs bus arbitration
•Link layer
– Assembles and dis-assembles bus packets
– Handles response and acknowledgment f unctions
• Host controller
– Implements higher levels of the protocol
DesignCon 2003 TecForum I2C Bus Overview
Slide 23
23
10
AN10216-01 I2C Manual
2
C Overview
I
What is I2C ? (Inter-IC)
• Originally, bus defined by Philips providing a simple way to
talk between IC’s by using a minimum number of pins
• A set of specifications to build a simple universal bus
guaranteeing compatibility of parts (ICs) from different
manufacturers:
– Simple Hardware standards
– Simple Software protocol standard
• No specific wiring or connectors - most often it’s just PCB
tracks
• Has become a recognised standard throughout our industry
and is used now by ALL major IC manufacturers
DesignCon 2003 TecForum I2C Bus Overview 24
Slide 24
Originally, the I
number of devices on a single card, such as to manage
the tuning of a car radio or TV. The maximum
allowable capacitance was set at 400 pF to allow proper
rise and fall times for optimum clock and data signal
integrity with a top speed of 100 kbps. In 1992 the
standard bus speed was increased to 400 kbps, to keep
up with the ever-increasing performance requirements
of new ICs. The 1998 I
speed to 3.4 Mbits/sec. All I2C devices are designed to
be able to communicate together on the same two-wire
bus and system functional architecture is limited only
by the imagination of the designer.
But while its application to bus lengths within the
confines of consumer products such as PCs, cellular
phones, car radios or TV sets grew quickly, only a few
system integrators were using it to span a room or a
building. The I
multiple card systems, such as a blade servers, where
the I2C bus to each card needs to be isolatable to allow
for card insertion and removal while the rest of the
system is in operation, or in systems where many more
devices need to be located onto the same card, where
the total device and trace capacitance would have
exceeded 400 pF.
New bus extension & control devices help expand the
I2C bus beyond the 400 pF limit of about 20 devices
and allow control of more devices, even those with the
same address. These new devices are popular with
designers as they continue to expand and increase the
range of use of I
applications.
2
C Features
I
• Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL).
2
C bus was designed to link a small
2
C specification, increased top
2
C bus is now being increasingly used in
2
C devices in maintenance and control
• Each device connected to the bus is software
addressable by a unique address and simple
master/slave relationships exist at all times;
masters can operate as master-transmitters or as
master-receivers.
• It’s a true multi-master bus including collision
detection and arbitration to prevent data corruption
if two or more masters simultaneously initiate data
transfer.
• Serial, 8-bit oriented, bi-directional data transfers
can be made at up to 100 kbit/s in the Standardmode, up to 400 kbit/s in the Fast-mode, or up to
3.4 Mbit/s in the High-speed mode.
• On-chip filtering (50 ns) rejects spikes on the bus
data line to preserve data integrity.
• The number of ICs that can be connected to the
same bus segment is limited only by the maximum
bus capacitive loading of 400 pF.
I2C Bus - Software
• Simple procedures that allow communication to start, to
achieve data transfer, and to stop
– Described in the Philips protocol (rules)
– Message serial data format is very simple
– Often generated by simple software in general purpose micro
– Dedicated peripheral devices contain a complete interface
– Multi-master capable with arbitration feature
• Each IC on the bus is identified by its own address code
– Address has to be uni que
• The master IC that initiates communication provides the clock
signal (SCL)
– There is a maximum clock frequency but NO MINIMUM SPEED
DesignCon 2003 TecForum I2C Bus Overview 25
Slide 25
2
C Communication Procedure
I
One IC that wants to talk to another must:
1) Wait until it sees no activity on the I
and SCL are both high. The bus is 'free'.
2) Put a message on the bus that says 'its mine' - I
have STARTED to use the bus. All other ICs then
LISTEN to the bus data to see whether they might
be the one who will be called up (addressed).
3) Provide on the CLOCK (SCL) wire a clock signal.
It will be used by all the ICs as the reference time
at which each bit of DATA on the data (SDA) wire
will be correct (valid) and can be used. The data on
the data wire (SDA) must be valid at the time the
clock wire (SCL) switches from 'low' to 'high'
voltage.
4) Put out in serial form the unique binary 'address'
(name) of the IC that it wants to communicate
with.
5) Put a message (one bit) on the bus telling whether
it wants to SEND or RECEIVE data from the other
chip. (The read/write wire is gone!)
2
C bus. SDA
11
AN10216-01 I2C Manual
6) Ask the other IC to ACKNOWLEDGE (using one
bit) that it recognized its address and is ready to
communicate.
7) After the other IC acknowledges all is OK, data
can be transferred.
8) The first IC sends or receives as many 8-bit words
of data as it wants. After every 8-bit data word the
sending IC expects the receiving IC to
acknowledge the transfer is going OK.
9) When all the data is finished the first chip must
free up the bus and it does that by a special
message called 'STOP'. It is just one bit of
information transferred by a special 'wiggling' of
the SDA/SCL wires of the bus.
The bus rules say that when data or addresses are being
sent, the DATA wire is only allowed to be changed in
voltage (so, '1', '0') when the voltage on the clock line is
LOW. The 'start' and 'stop' special messages BREAK
that rule, and that is how they are recognized as special.
How are the connected devices
recognized?
• Master device ‘polls’ used a specific unique identification or
“addresses” that the designer has included in the system
• Devices with Master capability can identify themselves to
other specific Master devices and advise their own specific
address and functionality
– Allows design ers to build ‘plug and play’ systems
– Bus speed can be different for each device, only a max imum limit
• Only two devices exchange data during one ‘conversation’
DesignCon 2003 TecForum I2C Bus Overview 26
Slide 26
Any device with the ability to initiate messages is
called a ‘master’. It might know exactly what other
chips are connected, in which case it simply addresses
the one it wants, or there might be optional chips and it
then checks what’s there by sending each address and
seeing whether it gets any response (acknowledge).
An example might be a telephone with a micro in it. In
some models, there could be EEPROM to guarantee
memory data, in some models there might be an LCD
display using an I
written to cover all possibilities. If the micro finds a
display then it drives it, otherwise the program is
arranged to skip that software code. I
of the buses in this presentation. Only two chips are
involved in any one communication - the Master that
initiates the signals and the one Slave that responded
when addressed.
2
C driver. There can be software
2
C is the simplest
But several Masters could control one Slave, at
different times. Any ‘smart’ communications must be
via the transferred DATA, perhaps used as address info.
2
The I
C bus protocol does not allow for very complex
systems. It’s a ‘keep it simple’ bus. But of course
system designers are free to innovate to provide the
complex systems - based on the simple bus.
Serial Bus Comparison Summary
Pros and Cons of the different buses
UART
• Well Kn own
• Cost effective
•Simple
•Limited
functionality
• Point to Point
DesignCon 2003 TecForum I2C Bus Overview
•Secure
•Fast
• Complex
• Automotive
oriented
•Limited
portfolio
• Expensive
firmware
•Fast
• Plug&Play HW
•Simple
• Low cost
•Powerful master
required
•No Plug&Play
SW - Spec ific
drivers required
Slide 27
Most Philips CAN devices are not plug & play. That is
because for MOST chips the system needs to be fixed
and nothing can be added later. That is because an
added chip is EXPECTED to take part in EVERY data
conversation but will not know the clock speed and
cannot synchronize. That means it falsely reports a bus
timing error on every message and crashes the system.
Philips has special transceivers that allow them listen to
the bus without taking part in the conversations. This
special feature allows them to synchronize their clocks
and THEN actively join in the conversations. So, from
Philips, it becomes POSSIBLE to do some minor
plug/play on a CAN system.
USB/SPI/MicroWire and mostly UARTS are all just
'one point to one point' data transfer bus systems. USB
then uses multiplexing of the data path and forwarding
of messages to service multiple devices.
Only CAN and I2C use SOFTWARE addressing to
determine the participants in a transfer of data between
2
C) or more (CAN) chips all connected to the
two (I
same bus wires. I
2
C is the best bus for low speed
maintenance and control applications where devices
may have to be added or removed from the system.
SPIUSBCAN
•Fast
•Universally
accepted
•Low cost
• Large Portfolio
•No Plug&Play
HW
• No “fixed”
standard
•Simple
• Well known
• Universally
accepted
• Plug&Play
• Large portfolio
•Cost effective
•Limited speed
I2C
27
12
AN10216-01 I2C Manual
I2C Theory Of Operation
I2C Introduction
•I2C bus = Inter-IC bus
• Bus developed by Philips in the 80’s
• Simple bi-directional 2-wire bus:
– serial data (SDA)
– serial clock (SCL)
• Has become a worldwide industry standard and used by all
major IC manufacturers
• Multi-master capable bus with arbitration feature
• Master-Slave communication; Two-device only communication
• Each IC on the bus is identified by its own address code
• The slave can be a:
– receiver-only device
– transmitter with the capability to both receive and send data
DesignCon 2003 TecForum I2C Bus Overview
Slide 29
2
The I
C bus is a very easy bus to understand and use.
Slides 29 and 30 give a good explanation of bus
specifics and the different speeds. Many people have
asked where rise time is measured and the specification
stipulates it’s between 30% and 70% of V
becomes important when buffers ‘distort’ the rising
edges on the bus. By keeping any waveform distortions
below 30% of VDD, that portion of the rising edge will
not be counted as part of the formal rise time.
I2C by the numbers
Standard-Mode Fast-Mode High-Speed-
Bit Rate
(kbits/s)
Max Cap Load
(pF)
Rise time
(ns)
Spike Filtered
(ns)
Address Bits 7 and 10 7 and 10 7 and 10
V
DD
V
IH
V
IL
V
OL
GND
DesignCon 2003 TecForum I2C Bus Overview
0 to 100 0 to 400
400 400 400 100
1000 300 160 80
N/A 50 10
Rise Time
0.4 V @ 3 mA Sink Current
Slide 30
2
I
C is a low to medium speed serial bus with an
impressive list of features:
• Resistant to glitches and noise
• Supported by a large and diverse range of
peripheral devices
• A well-known robust protocol
• A long track record in the field
• A respectable communication distance which can
be extended to longer distances with bus extenders
0 to
1700
Mode
0.7xV
0.3xV
. This
DD
0 to
3400
DD
DD
29
30
• Compatible with a number of processors with
integrated I
2
C ports (micro 8,16,32 bits) in 8048,
80C51 or 6800 and 68xxx architectures
• Easily emulated in software by any microcontroller
• Available from an important number of component
manufacturers
I2C Hardware architecture
Pull-up resistors
Typical value 2 kΩ to 10 kΩ
SCL
DesignCon 2003 TecForum I2C Bus Overview
2
C Bus Terminology
I
• Transmitter - the device that sends data to the bus.
A transmitter can either be a device that puts data
on the bus of its own accord (a ‘mastertransmitter’), or in response to a request from data
from another devices (a ‘slave-transmitter’).
• Receiver - the device that receives data from the
bus.
• Master - the component that initializes a transfer,
generates the clock signal, and terminates the
transfer. A master can be either a transmitter or a
receiver.
• Slave - the device addressed by the master. A slave
can be either receiver or transmitter.
• Multi-master - the ability for more than one
master to co-exist on the bus at the same time
without collision or data loss.
• Arbitration - the prearranged procedure that
authorizes only one master at a time to take control
of the bus.
• Synchronization - the prearranged procedure that
synchronizes the clock signals provided by two or
more masters.
• SDA - data signal line (Serial DAta)
• SCL - clock signal line (Serial CLock)
Slide 31
Open Drain structure (or
Open Collector) for both
SCL and SDA
10 pF Max
31
13
AN10216-01 I2C Manual
START/STOP conditions
• Data on SDA must be stable when SCL is High
• Exceptions are the START and STOP conditions
S
DesignCon 2003 TecForum I2C Bus Overview
SCL
SDA
• Each device is addressed individually by software
• Unique address per device: fully fixed or with a program mable part
through hardware pin(s).
P
32
• Programmable pi ns mean that several same devices can share the
same bus
• Address allocation coordinated by the I
• 112 different types of devices max with the 7-bit format (others reserv ed)
DesignCon 2003 TecForum I2C Bus Overview
I2C Address, Basics
µcon-
I/O A/D
troller
1010 0 1 1
1010A2A1A0R/W
Fixed Hardware
D/A
Selectable
LCD RTC
2
C-bus committee
Slide 32 Slide 33
START and STOP Conditions HARDWARE CONFIGURATION
Within the procedure of the I
arise which are defined as START (S) and STOP (P)
conditions.
START: A HIGH to LOW transition on the SDA line
while SCL is HIGH
STOP: A LOW to HIGH transition on the SDA line
while SCL is HIGH
The master always generates START and STOP
conditions. The bus is considered to be busy after the
START condition. The bus is considered to be free
again a certain time after the STOP condition. The bus
stays busy if a repeated START (Sr) is generated
instead of a STOP condition. In this respect, the
START (S) and repeated START (Sr) conditions are
functionally identical. The S symbol will be used as a
generic term to represent both the START and repeated
2
C bus, unique situations
Slide 33 shows the hardware configuration of the I
bus. The ‘bus’ wires are named SDA (serial data) and
SCL (serial clock). These two bus wires have the same
configuration. They are pulled-up to the logic ‘high’
level by resistors connected to a single positive supply,
usually +3.3 V or +5 V but designers are now moving
to +2.5 V and towards 1.8 V in the near future.
All the connected devices have open-collector (opendrain for CMOS - both terms mean only the lower
transistor is included) driver stages that can transmit
data by pulling the bus low, and high impedance sense
amplifiers that monitor the bus voltage to receive data.
Unless devices are communicating by turning on the
lower transistor to pull the bus low, both bus lines
remain ‘high’. To initiate communication a chip pulls
the SDA line low. It then has the responsibility to drive
the SCL line with clock pulses, until it has finished, and
is called the bus ‘master’.
START conditions, unless Sr is particularly relevant.
Detection of START and STOP conditions by devices
connected to the bus is easy if they incorporate the
necessary interfacing hardware. However,
microcontrollers with no such interface have to sample
the SDA line at least twice per clock period to sense the
transition.
BUS COMMUNICATION
Communication is established and 8-bit bytes are
exchanged, each one being acknowledged using a 9th
data bit generated by the receiving party, until the data
transfer is complete. The bus is made free for use by
other ICs when the ‘master’ releases the SDA line
during a time when SCL is high. Apart from the two
special exceptions of start and stop, no device is
allowed to change the state of the SDA bus line unless
the SCL line is low.
If two masters try to start a communication at the same
time, arbitration is performed to determine a “winner”
(the master that keeps control of the bus and continue
the transmission) and a “loser” (the master that must
abort its transmission). The two masters can even
generate a few cycles of the clock and data that
‘match’, but eventually one will output a ‘low’ when
the other tries for a ‘high’. The ‘low’ wins, so the
µcon-
troller II
A0
A1
A2
New devices or
functions can be
easily ‘clipped on to
an existing bus!
EEPROM
33
2
C
14
AN10216-01 I2C Manual
‘loser’ device withdraws and waits until the bus is freed
again.
There is no minimum clock speed; in fact any device
that has problems to ‘keep up the pace’ is allowed to
‘complain’ by holding the clock line low. Because the
device generating the clock is also monitoring the
voltage on the SCL bus, it immediately ‘knows’ there is
a problem and has to wait until the device releases the
SCL line.
For full details of the bus capabilities refer to Philips
Semiconductors Specification document ‘The I
specification’ or ‘The I
2
C bus from theory to practice’
book by Paret and Fenger published by John Wiley &
Sons.
2
C specification and other useful application
The I
information can be found on Philips Semiconductors
web site at
http://www.semiconductors.philips.com/i2c/
I2C Address, 7-bit and 10-bit formats
• The 1st byte after START determines the Slave to be addressed
• Some exceptions to the rule:
– “General Call” address : all devices are addressed : 0000 000 + R/W = 0
– 10-bit slave addressing : 1111 0XX + R/W = X
•7-bit addressing
S AX X X X X X X R/W
The 7 bits
• 10-bit addressing
S A1
1 1 1 1 0 X X
XX = the 2 MSBs The 8 remaining
More than one device can
DesignCon 2003 TecForum I2C Bus Overview
acknowledge
R/W
Slide 34 shows the I
can be attached to the common I
with each other, passing information back and forth.
Each device has a unique 7-bit or 10-bit I
For 7-bit devices, typically the first four bits are fixed,
the next three bits are set by hardware address pins (A0,
A1, and A2) that allow the user to modify the I2C
address allowing up to eight of the same devices to
operate on the I
2
C bus. These pins are held high to V
sometimes through a resistor, or held low to GND.
The last bit of the initial byte indicates if the master is
going to send (write) or receive (read) data from the
slave. Each transmission sequence must begin with the
start condition and end with the stop condition.
On the 8th clock pulse, SDA is set ‘high’ if data is
going to be read from the other device, or ‘low’ if data
is going to be sent (write). During its 9th clock, the
DATA
Only one device will acknowledge
X X X X X X X X
bits
A2
Only one device will
acknowledge
Slide 34
2
C address scheme. Any I2C device
2
C bus and they talk
DATA
2
C address.
2
C bus
34
CC,
master releases SDA line to accomplish the
Acknowledge phase. If the other device is connected to
the bus, and has decoded and recognized its ‘address’, it
will acknowledge by pulling the SDA line low. The
responding chip is called the bus ‘slave’.
I2C Read and Write Operations (1)
• Write to a Slave device
S slave address W A data A data
S slave address W A data A data A P
A P
“0” = Write
The master is a “MAST ER - TRANSMITTER”:
–it transmits both Clock and Data during the all communication
• Read from a Slave device
S slave address R A data A data A P
“1” = Read
The master is a “MASTER TRANSMITTER then MASTER - RECEIVER”:
– it transmits Clock all the time
– it sends slave address data and then becomes a receiver
DesignCon 2003 TecForum I2C Bus Overview
< n data bytes >
Each byte is acknowledged by the slave device
< n data bytes >
Each byte is acknowledged by the master device (except the last
one, just before the STOP condition)
Slide 35
Terminology for Bus Transfer
• F (FREE) - the bus is free; the data line SDA and
the SCL clock are both in the high state.
• S (START) or S
(Repeated START) - data
R
transfer begins with a start condition (not a start
bit). The level of the SDA data line changes from
high to low, while the SCL clock line remains high.
When this occurs, the bus is ‘busy’.
• C (CHANGE) - while the SCL clock line is low,
the data bit to be transferred can be applied to the
SDA data line by a transmitter. During this time,
SDA may change its state, as along as the SCL line
remains low.
• D (DATA) - a high or low bit of information on the
SDA data line is valid during the high level of the
SCL clock line. This level must be maintained
stable during the entire time that the clock remains
high to avoid misinterpretation as a Start or Stop
condition.
• P (STOP) - data transfer is terminated by a stop
condition, (not a stop bit). This occurs when the
level on the SDA data line passes from the low
state to the high state, while the SCL clock line
remains high. When the data transfer has been
terminated, the bus is free once again.
Master
transmitter
receiver
Slave
SCL
receiver
SDA
SCL
transmitter
SDA
35
15
AN10216-01 I2C Manual
I2C Read and Write Operations (2)
• Combined Write and Read
S slave address W A data A data
S slave address W A data A data A Sr
A P
“0” = Write “1” = Read
• Combined Read and Write
S slave address R A data A data A P
“1” = Read “0” = Write
DesignCon 2003 TecForum I2C Bus Overview
Slide 36 shows a combined read and write operation.
Acknowledge; Clock Stretching
• Acknowledge
Done on the 9th clock pulse and is mandatory
• Clock Stretching
- Slave device can hold the CLOCK li ne LOW when performing
other functions
- Master can slow down the clock to accommodate slow slaves
DesignCon 2003 TecForum I2C Bus Overview
Slide 37 shows how the Acknowledge phase is done
and how slave devices can stretch the clock signal.
Most Philips slave devices do not control the clock line.
I2C Protocol - Clock Synchronization
Master 1 Master 2
CLK 1 CLK 2
• LOW period determined by the longest clock LOW period
•
HIGH period determined by shortest clock HIGH period
DesignCon 2003 TecForum I2C Bus Overview
< n data bytes >
Each byte is
acknowledge d
by the slave device
< n data bytes >
Each byte is
acknowledge d
by the master device
(except the last one, just
before the Re-START
condition)
Sr slave address R A data A data A P
S slave address W A data A data
Sr slave address W A data A data A P
A P
< m data bytes >
Each byte is
acknowledged
by the master device
(except the last one, just
before the STOP
condition)
< m data bytes >
Each byte is
acknowledge d
by the slave device
Slide 36
Æ Transmitter releases the SDA line
Æ Receiver pulls down the SDA line (SCL must be HIG H)
Æ Transfer is aborted if no acknowledge
No acknowledge
Acknowledge
Slide 37
Vdd
SCL
1
4
3
2
Slide 38
36
37
38
Slide 38 shows how multiple masters can synchronize
their clocks, for example during arbitration. When bus
capacitance affects the bus rise or fall times the master
will also adjust its timing in a similar way.
I2C Protocol - Arbitration
• Two or more masters may generate a START condition at the same time
• Arbitration is done on SDA while SCL is HIGH - Slaves are not involved
Master 1 loses arbitration
DATA1 ≠SDA
Start
“1”
command
DesignCon 2003 TecForum I2C Bus Overview
“0”
“0” “1” “0”
“1”
Slide 39
If there are two masters on the same bus, there are
arbitration procedures applied if both try to take control
of the bus at the same time. When two chips try to start
communication at the same time they may even
generate a few cycles of the clock and data that
‘match’, but eventually one will output a ‘low’ when
the other tries for a ‘high’. The ‘low’ wins, so the
‘loser’ device withdraws and waits until the bus is freed
again. Once a master (e.g., microcontroller) has control,
no other master can take control until the first master
sends a stop condition and places the bus in an idle
state.
What do I need to drive the I2C bus?
Master
There are 3 basic way s to drive the I2C bus:
1) With a Microcontroller with on-chip I2C Interface
Bit oriented - CPU is interrupted after every bit transmission
(Example: 87LPC76x)
Byte oriented - CPU can be interrupted after every byte transmission
(Example: 87C552)
2) With ANY microcontroller: 'Bit Banging’
The I2C protocol can be emulated bit by bit via any bi-directional open drain port
3) With a microcontroller in conjunction with bus controller like the
PCF8584 or PCA9564 parallel to I
DesignCon 2003 TecForum I2C Bus Overview
I2C BUS
2
C bus interface IC
Slide 40
Slide 40 shows there are multiple ways to control I
slaves.
Slave 4Slave 3Slave 2Slave 1
39
40
2
C
16
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