Philips AN10148 Application note

INTEGRATED CIRCUIT

S

Control signals

µController

µProcessor

DSP or ASIC

Abstract

Philips Semiconductors family of bus controllers is detailed in this application note. PCA9564
device operation, software and hardware methodology and typical applications are discussed.

8 bits

PCA9564

SDA

SCL

AN10148

2

PCA9564 – I

C-bus controller

Jean-Marc Irazabal, PCA Technical Marketing Manager
Paul Boogaards, Sr. Field Application Engineer
Steve Blozis,

PCA International Product Manager

Supersedes data of 2004 August 11

Philips
Semiconductors

2004 November 22

1

TABLE OF CONTENTS

OVERVIEW.......................................................................................................................................................................3

DESCRIPTION..................................................................................................................................................................... 3

APPLICATIONS................................................................................................................................................................... 3

FEATURES ......................................................................................................................................................................... 4

DEVICE PINOUT.................................................................................................................................................................5

ORDERING INFORMATION.................................................................................................................................................. 7

DATA SHEETS AND IBIS MODELS .....................................................................................................................................7

PCF8584 TECHNICAL INFORMATION.......................................................................................................................7

PCA9564 TECHNICAL INFORMATION......................................................................................................................7

BLOCK DIAGRAM............................................................................................................................................................... 7

REGISTERS DEFINITIONS ....................................................................................................................................................8

READ AND WRITE STROBES ............................................................................................................................................12

POLLING SI BIT VERSUS USING INT PIN AS INTERRUPT ..................................................................................................12

RESET.............................................................................................................................................................................. 13

INTERFACING THE PCA9564 WITH CPU AND SLAVE DEVICES – HARDWARE .................................................................13

INTERFACING THE PCA9564 WITH CPU AND SLAVE DEVICES – SOFTWARE ................................................................... 14

MASTER AND SLAVE MODES HANDLING..........................................................................................................................15

FLOWCHARTS.............................................................................................................................................................16

Initialization Sequence ...............................................................................................................................................16

Master Transmitter Mode...........................................................................................................................................17

Master Receiver Mode................................................................................................................................................19

Slave Transmitter / Receiver mode.............................................................................................................................21

Time-out – SCL Stuck Low Error...............................................................................................................................22

Bus Recovery – SDA Stuck Low Error .......................................................................................................................23

Bus error.....................................................................................................................................................................23

APPLICATIONS..............................................................................................................................................................24

TYPICAL APPLICATION USING THE 80C51 MICROCONTROLLER....................................................................................... 24

INTERFACING THE PCA9564 TO SEND/RECEIVE I2C COMMANDS OVER LONG CABLES..................................................... 24

PCA9564 EVALUATION BOARD ................................................................................................................................27

FREQUENTLY ASKED QUESTIONS.........................................................................................................................27

ADDITIONAL INFORMATION...................................................................................................................................30

REVISION HISTORY...................................................................................................................................................30

DISCLAIMERS ..................................................................................................................................................................31

2

OVERVIEW

)

%

Description

The PCF8584 and the PCA9564 are bus controller devices performing the following functions:

- Receive data in a parallel format from a microcontroller/microprocessor, convert them to a serial format conforming

- Receive serial data from the I

The PCF8584 is an integrated circuit designed in CMOS technology that serves as an interface between most standard
parallel-bus microcontrollers/microprocessors and the serial I
functions. Communication with the I
controls all the I
communicate bi-directionally with the I

The PCA9564 is an integrated circuit designed in CMOS technology that serves as an interface between most standard
parallel-bus microcontrollers/microprocessors and the serial I
communicate bi-directionally with the I
or receiver. Communication with the I
PCA9564 controls all the I

The PCA9564 is similar to the PCF8584 but operates at lower voltages and higher I²C frequencies. Other programming
enhancements requested by design engineers have also been incorporated although the PCA9564 does not support bus
monitor “snoop” mode, General Call Address or long distance mode, as does the PCF8584.

Characteristics PCF8584 PCA9564 Comments PCA9564

Voltage range 4.5 V - 5.5 V 2.3 V - 3.6 V 5 V tolerant

Maximum I

2

to the I

C protocol and send them to I2C devices located on the bus

2

C-bus, convert them to a parallel format and send them to the microcontroller /

microprocessor connected to the controllers

2

2

C -bus specific sequences, protocol, arbitration and timing. The PCF8584 allows parallel-bus systems to

2

C-bus specific transactions with no external timing element required.

2

C freq. 90 kHz 360 kHz Fast-mode I2C compatible

C-bus is carried out on a byte-wise basis using interrupt or polled handshake. It

2

C-bus.

2

C-bus. The PCA9564 can operate as a master or a slave and can be a transmitter

2

C-bus is carried out on a byte-wise basis using interrupt or polled handshake. The

2

C-bus. The PCF8584 provides both master and slave

2

C-bus allowing the 8-bit parallel bus system to

External Internal

Clock source Less expensive and more flexible

TTL (3 to 12

MHz

Parallel interface Compatible with faster processors

Slow Fast

3 MHz 50 MHz

accuracy:

±15

Snoop Mode Yes No
Long Distance Mode Yes No

While the PCF8584 supported most parallel-bus microcontrollers/microprocessors including the Intel 8049/8051,
Motorola 6800/68000 and the Zicor Z80, the PCA9564 has been designed to be very similar to the Philips standard

80C51 microcontroller I

2

C hardware so existing code, for devices such as Philips 8xC552 can be utilized with a few
modifications. There is already code written on the Philips Microcontroller website which would greatly reduce the
software development for the PCA9564. For more information, please check the following URL:

http://www.semiconductors.philips.com/markets/mms/products/microcontrollers/support/software_download/8051/index
.html

Applications

These bus controller devices can be used for a wide variety of applications:

2

I

C-bus Mastering – Some microprocessors have none or an insufficient number of I

be a way to add an I
from the processor to interface to the I

2

the I

C-bus using 2 bits of GPIO, one for the data and one for the clock, if it is the only master on the bus and needs to

2

C port to the microcontroller. The PCF8584 and PCA9564 use 8-bit I/Os and several control signals

2

C-bus in a multiple master capable environment. Any processor can “bit bang”

2

C ports and sometimes there must

3

send only simple commands. The PCF8584 or PCA9564 is required when full multiple master compliance with the I
specification is required.

2

I

C-bus Slaving – The PCF8584 and PCA9564 can be used to interface any processor to the I

2

C-bus using 8-bit of

GPIO and some control signals.

2

I

C-bus Sniffing (PCF8584 only) – The PCF8584 provides an I

2

C-bus snoop mode that allows the microprocessor to

monitor communications on the bus without changing the structure.

2

I

C General Call Address (PCF8584 only) – The PCF8584 provides an I

2

C General Call Address mode that allows I2C

General Call Address detection (0x00) when bus controller addressed as a slave.

2

I

C Long Distance Mode (PCF8584 only) -The long-distance mode provides the possibility of longer-distance serial

communication between parallel processors via two I

2

C-bus controllers. In this mode the I2C -bus protocol is transmitted
over 4 unidirectional lines, SDA OUT, SCL IN, SDA IN and SCL IN (pins 2, 3, 4 and 5). These communication lines
should be connected to line drivers/receivers for long-distance applications. Hardware characteristics for long-distance
transmission are then given by the chosen standard. Control of data transmission is the same as in normal I

2

C -bus mode.

Features

PCA9564 Features

• Parallel-bus to I

• Both master and slave functions

• Multi-master capability

• I2C and SMBus compatible

• 2.3 V to 3.6 V operating supply voltage

• 5.5 V tolerant I/Os

• -45 ºC to 85 ºC operating temperature range

• 0 kHz to 360 kHz (400 kHz in slave mode) clock frequency

• Glitch free operation at power-up and power-down, supports hot insertion

• Manufactured in high-volume CMOS process

• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per

JESD22-C101

• JESDEC Standard JESD78 Latch-up testing exceeds 100mA.

• Offered in 20-pin DIP (N), SO (D), TSSOP (PW) and HVQFN (BS)

PCF8584 Features

• Parallel-bus to I

• Compatible with most parallel-bus microcontrollers/microprocessors including 8049, 8051, 6800, 68000 and Z80

• Both master and slave functions

• Automatic detection and adaptation to bus interface type

• Programmable interrupt vector

• Multi-master capability

2

C-bus monitor mode

• I

2

C-bus All Call Mode

• I

• Long-distance mode (4-wire)

• 4.5 V to 5.5 V operating supply voltage

• -40 °C to +85 °C operating temperature range

• 0 kHz to 90 kHz (100 kHz in slave mode) clock frequency

• Manufactured in high-volume CMOS process

• Offered in 20-pin DIP (P) and SO (T)

2

C -bus protocol converter and interface

2

C -bus protocol converter and interface

2

C

4

Device Pinout

PCA9564 Pinout

5

PCF8584 Pinout

6

Ordering Information

Package Container

DIP

SO

TSSOP

HVQFN

Tube
Tube PCF8584D PCA9564D
T & R PCF8584D -T PCA9564D -T
Tube Not Available PCA9564P W
T & R Not Available PCA9564P W-T
T & R

PCF8564 PCA9564
PCF8584 PCA9564N

Not Available PCA9564B S-T

Data Sheets and IBIS Models

Data sheet of the PCF8584 and PCA9564 and IBIS model of the PCA9564 can be downloaded from

http://www.standardproducts.philips.com/i2c

PCA9564 HSPICE model is available upon request via email at [e-mail]
There are no IBIS and HSPICE models available for the PCF8584.

PCF8584 TECHNICAL INFORMATION

PCF8584 Technical information can be found in the following Philips Application Notes.

• AN425: Interfacing the PCF8584 I

http://www.semiconductors.philips.com/acrobat/applicationnotes/IC22_AN425.pdf

• AN95068: C Routines for the PCx8584

http://www.semiconductors.philips.com/acrobat/applicationnotes/AN95068.pdf

• AN96098: Interfacing 68000 family peripherals to the XA

http://www.semiconductors.philips.com/acrobat/applicationnotes/AN96098.pdf

• AN96040: Using the 8584 with non specified timings and other frequently asked questions

http://www.semiconductors.philips.com/acrobat/applicationnotes/AN96040.pdf

2

C-bus controller to 80C51 family microcontrollers

PCA9564 TECHNICAL INFORMATION

Block diagram

The block diagram of the PCA9564 is shown in Figure 1. Interfacing to the microcontroller, microprocessor or any
device able to communicate with the bus controller (“CPU” will be used from now to designate such a device) and to I
slave or master devices is done through the following pins:

•

: Active-LOW Chip Enable input signal allowing the PCA9564 to communicate with the CPU. This signal may

CE

be held low when it is the only device on the CPU address/data bus.

• D7 to D0: 8-bit bi-directional 3-statable data bus

• A1, A0: Address input pins for internal register-selection

•

and RD: Active-LOW Strobe input signals allowing writing or reading the content of the register addressed

WR

through A1 and A0 pins.

•

: Active-LOW Interrupt output indicating to the master that an event pertinent to the PCA9564 occurred on the

INT

2

C-bus or that an action requested by the CPU has been performed by the PCA9564. Nature of the event or result of

I
the requested action is available by reading the Status register (I2CSTA)

•

RESET

• SDA and SCL: Data and Clock lines of the I
Five internal registers allow the PCA9564 to be configured and data to be sent or received.
An internal 9 MHz oscillator controls I
(Standard-Mode and Fast-Mode I

: Active-LOW Reset input pin clearing the PCA9564 internal registers and resetting the I2C state machine.

2

C-bus timings and generates the I2C clock when the PCA9564 is used as a master

2

C protocol)

2

C-bus

7

2

C

K

SDA

SCL

AA

SCL Control

STA STO SI ENSIO

CLOCK

SELECTOR

OSCILLATOR

SDA Control

STA STO SI ENSIO

Filter

Filter

CR0

CR1

CR2

CE

DATA

D7 D6 D5 D4 D3 D2

Bus Buffer

I2CDAT – Data Register – Read / Write

I2CTO – Timeout Register – Write Only

BIT7 BIT5 BIT4 BIT3 BIT2 BIT1 0

BIT6

I2CADR – Own Address – Read / Write

I2CSTA – Status Register – Read Only

AA ENSIO STA STO SI CR2 CR1 CR0

I2CCON – Control Register – Read / Write

INTERRUPT CONTROL

WR

RD

CONTROL SIGNALS

INT

D1

CONTROL BLOC

RESET

Figure 1. PCA9564 Block Diagram

D0

A1

A1 A0

0 1

0 0

1 0

0 0

1 1

A0

POWER

ON

RESET

VDD

Registers definitions

The five internal registers allow the PCA9564 to be configured and data to be sent or received. Definition of the registers
is shown in Table 1. The logic level of pins A1 and A0 determines access to a register. Read or Write operation is

determined by signals applied on pins

A1 A0 Register Name Register Function Read / Write Default Value

0 0 I2CSTA Status Register Read Only 0xF8
0 0 I2CTO Time-out Register Write Only 0xFF
0 1 I2CDAT Data Register Read / Write 0x00
1 0 I2CADR Own Address Register Read / Write 0x00
1 1 I2CCON Control Register Read / Write 0x00

RD and WR .

Table 1. Registers definition

8

2

• I2CTO is the time-out register used to determine the maximum time that SCL is low before the I

C state machine is

reset.

Time-Out Period = I2CTO[6:0] x 113.7 µs

The MSB of I2CTO register contains the TE bit.

TE = 0 Time-out function disabled
TE = 1 Time-out function enabled

• I2CADR contains the own address of the CPU connected to the PCA9564 when the device is used in slave mode.

Content of the register is irrelevant when the PCA9564 is functioning as a master.
The seven MSB’s determine the slave address that the PCA9564 will respond to. The LSB should be programmed
with a “0”.

- A “0” in the I2CADR register corresponds to a LOW level in the I

- A “1” in the I2CADR register corresponds to a HIGH level in the I

• I2CDAT contains the byte to be transmitted on the I

In master mode, along with the data byte to be transmitted, it also includes the slave address that the master CPU
wants to send out on the I

2

C-bus: the seven MSB’s are the slave I2C address (SD[7:1] with SD7 as the MSB of the

2

C-bus or a byte that has been received from the I2C-bus.

2

C-bus

2

C-bus

address) while the LSB (SD[0]) is the Read/Write bit.

• I2CCON is the Control Register where the CPU can read from and write to.

A Write to the I2CCON register via the parallel interface automatically clears the SI bit (bit 3), which causes the
Serial Interrupt line to be de-asserted and the next clock pulse on the SCL line to be generated. Since none of the
registers should be written to via the parallel interface once the Serial Interrupt line has been de-asserted, all the
other registers that need to be modified should be written to before the content of the I2CCON register is modified

.

- Bit 7 is the AA bit: Assert Acknowledge Flag

AA = 1 An Acknowledge is sent (Low on SDA) during the Acknowledge clock pulse if:

- The “own slave address” has been received

- A data byte has been received in Master Receiver mode

- A data byte has been received in Addressed Slave Receiver mode

AA = 0 An Acknowledge is not sent (High on SDA) during the Acknowledge clock pulse if:

- The “own slave address” has been received

- A data byte has been received in Master Receiver mode

- A data byte has been received in Addressed Slave Receiver mode

Note:

1. AA bit can be used to temporarily remove the PCA9564 (and the connected CPU) by setting it to “0”.
No acknowledge will then be sent to the device accessing the PCA9564.

- Bit 6 is the ENSIO bit: Enable Serial Input Output (I

2

C-bus)

ENSIO = 1 Serial Input Output enabled – Internal oscillator enabled
ENSIO = 0 Serial Input Output disabled (Hi-Z) – Internal oscillator disabled

Notes:

1. When ENSIO = 0, the PCA9564 is in a “not addressed” slave state and will not respond if its address is
sent by a master on the I

2. When ENSIO = 1, it takes 500 µs for the internal oscillator to stabilize.

3. ENSIO bit should not be used to temporarily remove the PCA9564 form the I

2

C-bus.

2

C-bus since the I2C-bus

status is lost when ENSIO = 0. The AA flag should be used instead as explained above.

- Bit 5 is the STA bit: START command

STA = 1 START command requested – PCA9564 enters Master mode
STA = 0 START command not requested

9

Notes:

1. START command is generated when the I

2. If the I

2

C-bus is not free at the request moment, the PCA9564 waits until a STOP command is placed on the

2

C-bus is free.

bus and then generates a START command after the bus free time between a STOP and a START
condition (t

) has elapsed.

BUF

3. If STA is set and the PCA9564 is already in a master mode (and one or more bytes have been sent or
received), the device sends a repeated START command.

- Bit 4 is the STO bit: STOP command

STO = 1 STOP command requested – Bus is free after the t

time has elapsed

BUF

STO = 0 STOP command not requested

Notes:

1. If both STA and STO are set when PCA9564 is in master mode, then a STOP command is generated on the

2

I

C-bus. PCA9564 then generates a START condition after the t

time has elapsed.

BUF

- Bit 3 is the SI bit: Serial Interrupt Flag

SI = 1 Serial Interrupt requested when ENSIO bit is set to 1

The serial interface entered one of 24 of the 25 possible states
(see I2CSTA register definition below)
Serial transfer is suspended
Low period of SCL is stretched

SI = 0 Serial Interrupt not requested

No stretching of SCL

Notes:

1. SI bit must be reset by software (by writing a “0” on that bit)

2. SI bit should never be set to “1” by the user

3. SI bit is not set to 1 when the value in I2CSTA is equal to F8

h

- Bit 2 to Bit 0 are the CR2 to CR0 bits: Clock Rate bits

CR2 CR1 CR0 Serial Clock Frequency (kHz)

0 0 0 330
0 0 1 288
0 1 0 217
0 1 1 146
1 0 0 88

Note 1

1 0 1 59
1 1 0 44
1 1 1 36

Notes:

1. The clock frequency values are approximate and may vary with temperature, supply voltage, process, and
SCL output loading. If normal mode I

2

C parameters must be strictly followed (SCL < 100 kHz), it is
recommended not to use CR[2:0] = 100 (SCL = 88 kHz) since the clock frequency might be slightly higher
than 100 kHz (109 kHz under worst case temperature, voltage, and process conditions) and use CR[2:0] =
101 (SCL = 59 kHz) instead.

2. Clock frequency values in the table are only for master mode. When PCA9564 is used in slave mode, the
device automatically synchronizes with any clock in the I

2

C-bus up to 400 kHz.

• I2CSTA contains the status code. It is a Read Only register and the 3 LSB are always “0”. 25 different codes are

possible and are shown in Table 2. Each code represents a different serial interface state. The first 24 states when

entered sets the SI bit in I2CCON Register to 1 and forces the

INT pin to go low. The 25

th

state (0xF8) does not set
the SI bit to 1 and does not generate an Interrupt because no relevant information is available and no serial interrupt
is then required.

10