Philips AN01045 APPLICATION NOTE

APPLICATION NOTE

Application information for

TV processor + µP + CC decoder

TDA937X PS N2

AN01045

Version 1.0

February 2002

Philips Semiconductors

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

ABSTRACT

This report gives a description of the TDA937X PS N2 version, together with application aspects.

Application Note

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Purchase of Philips I2Ccomponents conveys a license under the I components in the I system conforms to the I

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

defined by Philips.

C patent to use the

C system, provided the

C specifications

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Application Note

Application information for TV Signal

processor & µP & Closed Caption decoder

TDA 937X PS N2

AN01045

Author(s):

D. Allerton

L. Bakema

D. v.d. Brul

T. Bruton

G. Folmer

P.C.T.J. Laro

D. Siersema

E. Arnold

F. Giuliano

J. Liu

T. Lee

System Application, Mainstream T.V. Solutions

Consumer ICs Nijmegen,

The Netherlands

Keywords

Embedded micro-controller

OSD

Closed Caption, VPS

Alignment free IF-PLL, Sound PLL

Synchronisation H/V

Geometry on vertical and E-W

Switches and filters

PAL/NTSC decoder

Delay line

Continuous Cathode Calibration

Date: February 2002

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Summary

This report gives a description of the application aspects of the TDA937X, a combination of TV signal processor plus Closed caption decoder plus embedded microprocessor in one device.

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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CONTENTS

1 INTRODUCTION...................................................................................................................................... 7

2 DEVICE INFORMATION ......................................................................................................................... 9

3 PINNING CONFIGURATION................................................................................................................. 11

4 DEVELOPMENT TOOLS ...................................................................................................................... 13

C CONTROL VIDEO PROCESSOR PART......................................................................................... 17

5.1 INPUT CONTROL BITS.................................................................................................................. 20

5.2 OUTPUT CONTROL BITS ............................................................................................................. 35

6 APPLICATION INFORMATION............................................................................................................. 41

6.1 MICROPROCESSOR.....................................................................................................................45

6.2 IF PART .......................................................................................................................................... 47

6.3 FM SOUND..................................................................................................................................... 50

6.4 QSS SOUND................................................................................................................................... 55

6.5 THE NARROW BAND PLL............................................................................................................. 57

6.6 FILTERS, SWITCHES AND COLOUR DECODER........................................................................ 59

6.7 HORIZONTAL AND VERTICAL SYNC GEOMETRY..................................................................... 63

6.8 GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION ........ 71

6.9 YUV / RGB PROCESSING AND CONTROL.................................................................................. 77

6.10 PICTURE IMPROVEMENT FEATURES ........................................................................................ 89

6.11 SUPPLY, GROUNDING AND DECOUPLING................................................................................ 95

6.12 EMC LAYOUT............................................................................................................................... 107

7 ALIGNMENTS...................................................................................................................................... 109

7.1 TUNER AGC................................................................................................................................. 109

7.2 GEOMETRY.................................................................................................................................. 110

7.3 SCREEN VOLTAGE ALIGNMENT............................................................................................... 114

7.4 COLOUR TEMPERATURE ALIGNMENT .................................................................................... 118

8 BLOCK DIAGRAM .............................................................................................................................. 120

9 INTERNAL PINNING........................................................................................................................... 121

10 APPLICATION EXAMPLE ( DEMO-BOARD ).................................................................................... 128

11 REFERENCES..................................................................................................................................... 129

12 INDEX .................................................................................................................................................. 131

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

1 INTRODUCTION

This report gives hardware/software application information concerning the TDA937x PS N2 family. The TDA937x PS N2 series have both microprocessor and videoprocessor functions integrated in one

single chip and this device is intended for economy TV applications with 90º and 110º picture tubes. Several features are implemented and control of TDA937x functions/features is carried out using the supported I

The microprocessor, which uses an enhanced 80c51-microprocessor core (12MHz clock) has OTP ROM and built in RAM and it caters for:

The videoprocessor includes all the functions necessary for TV processing such as:

C bus and embedded software.

- Closed Caption decoding (subtitle system in USA for people with hearing impediments).

- OSD generation

- Data Capture decoding of either Line 21 Data Services (525 Timing) or Euro-Caption (625 Timing)

- IF video processing and sound (FM + QSS).

- Sync and geometry processing.

- PAL/NTSC colour decoder.

- RGB generation and processing of signals.

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The device is encapsulated in a SDIP64 package (Shrink Dual In-line, 64 pin SOT274-1) and uses both BIMOS and CMOS technologies.

The TDA937X family has been designed in order to have a low external component count for application and a single layer PCB technology can be used.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

2 DEVICE INFORMATION

The TDA937X family offers complete control and small signal video processing needed for TV applications in one device; it includes a microprocessor and a videoprocessor, both being encapsulated in a SDIP64 (Shrink Dual In-line, 64 pins) package. The microprocessor block diagram is shown in chapter 8.

A summary of the functions/features of the microprocessor is:

• Combined 55K x 8 bit OTP Micro-controller Program ROM and 4.5K x 16 bit OTP Character ROM.

• 0.25K x 8 bit Main Data RAM ( Mov address space).

• 2.25K x 8 bit Auxiliary Data RAM (Movx address space).

• Additional 16 bit Timer with 8 bit pre-scaler.

• 4 bit software A/D convert with 4 multiplexed inputs.

• Low resolution PWMs for VST.

• Byte level I2C up to 400KHz.

• Watchdog Timer with 16-bit pre-scaler.

• Three power saving modes : Stand-by, Idle and Power-Down.

• 13 I/O for SDIP64 via individual addressable controls.

• Programmable micro-controller I/O for Push-Pull, Open Drain, Quasi-Bidirectional & highImpedance.

• OSD graphics engine with up to 48 characters in width by 16 rows.

• Closed Caption style organized as 34 characters by 16 rows.

• 256 displayable characters.

• Globally selectable character matrix: 12 x 10, 12 x 13, 12 x 16 and 16 x 18 (h x v).

• Globally selectable horizontal character spacing (up to 4 pixels).

• Globally selectable vertical character spacing (up to 7 TV lines).

• 16 DRCS at up to 16 x 18 character matrix.

• 16 Foreground and 16 Background display colours selectable from a palette of 64.

• Enhanced display features including shadowing, underlining, overlining, italics and smoothing.

• Cursor Function.

• Contrast Reduction.

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The videoprocessor block diagram, which is subdivided into four subsections, is shown in chapter 8 A summary of the functions/features of the

IF video & sound:

− Multi-standard vision IF circuit with alignment free PLL demodulator and IF frequency selection by I

− Internal time constant for IF AGC circuit which can be selected via I

− The FM PLL sound demodulator can be switched between 4.5/5.5/6.0/6.5 MHz frequencies with the I

bus. At these frequencies extra internal selectivity can be selected under critical reception conditions by selecting the internal bandpass filter with the I

− Types available with FM demodulator or with QSS sound output as an input for a stereo decoder..

Filters/Switches & colour decoder:

− CVBS switching between the CVBS from the front end (IF) and CVBS from SCART which can also be used as an Y/C input.

− Integrated chroma trap, chroma bandpass (switchable center frequency with I

− Integrated luminance delay line with adjustable delay time.

− Peaking function including depeaking and a variable positive/negative overshoot ratio .

− Integrated baseband delay line (for NTSC systems can be applied as comb filter).

− ACL implemented for deviating standards having large chroma/burst ratios (>3).

videoprocessor are:

C bus.

C) and cloche filters

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

ACL function switched via I

− PAL/NTSC colour decoder with fully automatic colour search system including LATAM colour decoding for PAL M and PAL N signals.

− Only one 12MHz crystal required for all internal timing e.g. in the microprocessor, Close Caption decoder, OSD and in the video processor IF frequency, sound carrier, colour decoder and horizontal frequency

HV sync & geometry:

− Horizontal synchronization with 2 control loops and alignment free horizontal oscillator

− Vertical count down circuit

− Vertical driver optimized for DC coupled vertical output stages

− Horizontal and vertical geometry processing

− Horizontal and vertical zoom function for 16 : 9 applications

− Horizontal parallelogram and bow correction for large screen picture tubes

Low stress by innovative slow start/stop of H

−

energy Only 3.3V 65mA needed for start up which simplifies the stand-by power supply

−

C bus.

implying a gradual build-up of the EHT and deflection

OUT

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YUV/RGB processing & control:

− Picture improvement features as:

− dynamic skin tone

− black stretching

− contrast reduction possibility during mixed mode of OSD signals

− Linear RGB/YUV/ Y P

bus.

− CC or OSD signals are internally supplied from the CC decoder.

− Independent adjustable colour temperature for high/low light calibration.

− Beam current limiting, peak white limiting and soft clipper.

with fast blanking where the synchronisation on Y signals is possible via I2C

B PR

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

3 PINNING CONFIGURATION

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P1.6/SCL

P1.7/SDA

P2.0/TPWM P3.0/ADC0/PWM0 P3.1/ADC1/PWM1 P3.2/ADC2/PWM2

P3.3/ADC3/PWM3

VSSC/P

P0.5 P0.6

VSSA

I.C.

VP2

DECDIG

PH2LF PH1LF

GND3

DECBG

AVL/EWD

VDRB VDRA

IFIN1 IFIN2

IREF

VSC

AGCOUT

AUDEEM/SIFIN1

DECSDEM/SIFIN2

GND2

SNDPLL/SIFAGC

AVL/SNDIF/

REFO

11 12

14 15 16

22 23 24 25 26

28 29 30 31 32

1 2 3 4 5 6 7 8 9

LEADER

TDA937X PS N2

64P1.3/T1

P1.2/INT0 P1.1/T0

P1.0/INT1

62 61

VDDP RESET

XTALOUT

XTALIN

OSCGND

57 56

VDDC VPE

55 54

VDDA

BO GO

51 50

BLKIN BCLIN

B2/UIN/PbIN

48 47

G2/YIN

R2/VIN/PrIN

INSSW2

AUDOUT C

43 42

CVBS/Y GND1

41 40

CVBS1

VP1 IFVO/SVO

38 37

PLLIF EHTO

AUDEXT/QSSO

35 34

FBISO HOUT

Figure 1: Pinning configuration

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

IC version FM PLL version QSS version East-west Y/N CMB1, 0 bits Pin 20 Pin 28 Pin 29 Pin 31 Pin 32 Pin 35

Table 1: Pin functions for various modes of operation Note

1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF input. This function is selected by means of SIF bit in subaddress 28H.

SNDIF REFO AVL/SNDIF REFO REFO

NY N Y

00 01/10/11 00 01/10/11 00 01/10/11 00 01/10/11

AVL EWD AVL EWD

AUDEEM SIFIN1

DECSDEM SIFIN2

SNDPLL SIFAGC

AUDEXT AUDEXT QSSO AUDEXT QSSO

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

4 DEVELOPMENT TOOLS

To develop with the TDA937XPS/N2 family, the tools, listed below, need to be adapted/upgraded. To order the necessary upgrades, please contact your local marketing representative.

Emulator

Depending on the emulator brand used, the following adaptations are necessary:

HITEX

Currently, Hitex can supply a probe, namely PxTDA93xx-N2, for the TDA935X/6X/8XPS/N2 family, which is also suitable for emulating the TDA937XPS/N2 family, as well. This probe includes all the adapters for the µprocessor bond-outs (SAA5512) and video processor bond-out. (KN10161 QSS/FM).

However, existing UOC-N1 customers can upgrade their system, as well, for emulating the TDA937XPS/N2 devices, as described below. The HITEX with the existing PXSAA55xx probe for emulation of the TDA935X/6X/8X N1 consists of the following PCBs:

1. Main probe PCB, ref. 7313-903-0027-2 or ref. 7313-903-0027-3

2. QFP120 Daughter board PCB, ref. 7313-903-0033-2

3. UOC Interface board, ref. 7313-903-0007-2.

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In order to emulate the TDA937XPS/N2 family devices, the above boards have to be replaced as below:

1. Main probe PCB ref. 7313-903-0027-3 (Only in case version is ref. 7313-903-0027-2)

2. QFP120 Daughter board ref. 7313-903-0264-1 (replaces ref. 7313-903-0033-2)

3. UOC interface board ref. 7313-903-0317-1 (replaces ref. 7313-903-0007-2)

The new Daughter board (ref. 7313-903-2641) plugs into the main probe PCB (ref. 7313-903-0027-3) via an array of connectors, SK1...SK8. This board can accommodate the new υprocessor bond-outs (SAA5512). The new UOC interface board can accommodate the new video processor bond-out. (KN10161 QSS/FM).

BL-MTS Systems Applications Group Southampton supplies the necessary µprocessor, video processor bond-outs for emulation and replacement boards. The new set of boards supports the internal reset feature of the TDA937XPS/N2 family. Before using the probe, a set of jumpers on the Daughter board needs to be set as described below:

J1: HI J2: HI J3: OPEN (not used) J4: OPEN (not used)

A brochure with information about the new probe heads and bondouts is attached to this document. More details can be found in the Application Note PxTDA93xx-N2 available at our Support area on the Semiconductor Internet Site http://www.semiconductors.com.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

ASHLING ULTRA 51

Ashling announced that they would no longer support the existing CTS51 system. They offer full support for the TDA937XPS/N2 with their new Ultra-51 Ashling system. The system is supplied with and adapter (AD-SAA55L+) to use for accommodating the microprocessor bond-out. An additional adapter, ref. 7313-903-03171, is needed for the video-processor bond-out and it can be requested from BL-MTS Systems Applications Group Southampton. Information about the new probe head can be found in the attached brochure.

Display Development Studio (DDS)

The DDS is needed to generate the proper character sets and the matching with the type number of the device.

The new version DDS 2.2 supports the new UOC–N2. PAT/PROMT tool is out of date; it is recommended to use the new PROMPT tool, which is included within DDS 2.2 .It can be downloaded from our Support area on the Semiconductor Internet Site http://www.semiconductors.com.

This Support area is located at http://download.semiconductors.com/protected/video/. To apply for access, please complete the electronic form located at our Support Area:

Application Note

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http://downloads.semiconductors.com/unregistered/

GTV development tool

GTV release 2.0 supports the TDA937XPS/N2 family. Older releases are not suitable for the these devices.

Bench programmer

For programming the TDA937XPS/N2 the bench programmer must be a recent version. These versions can be easily recognized because they have a blue PCB. Some of older bench programmer versions (with green PCB) cannot be used with the TDA937XPS/N2 PS/N1 devices, until a FPGA(s) upgrade is implemented.

Please contact the BL-MTS Systems Applications Group Southampton for more details.

TV demoboard and WIC software

For evaluation, a TV demoboard plus the latest WIC software is available for the TDA937XPS/N2 version

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

5 I

C CONTROL VIDEO PROCESSOR PART

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FUNCTION SUBADDR DATA BYTE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0

Horizontal parallelogram 06 0 0 A5 A4 A3 A2 A1 A0 20 Horizontal Bow 07 0 0 A5A4A3A2 A1 A020 Hue 08 0 0 A5A4A3A2 A1 A000 Horizontal shift (HS) 09 0 0 A5 A4 A3 A2 A1 A0 20 EW width (EW) EW parabola/width (PW) EW upper corner parabola EW lower corner parabola EW trapezium (TC) Vertical slope (VS) 0F 0 0 A5 A4 A 3 A2 A1 A0 20 Vertical amplit ude (V A) 10 0 0 A5 A4 A3 A2 A1 A0 20 S-correction (SC) 11 0 0 A5 A4 A3 A2 A1 A0 20 Vertical shift (VSH) 12 0 0 A5A4A3A2 A1 A020 Vertical zoom (VX) Black level off-set R 14 0 0 A5A4A3A2 A1 A020 Black level off-set G 15 0 0 A5A4A3A2 A1 A020 White point R 16 0 0 A5 A4 A3 A2 A1 A0 20 White point G 17 0 0 A5 A4 A3 A2 A1 A 0 20 White point B 18 0 0 A5 A4 A3 A2 A1 A0 20 Peaking 19 0 0 A5A4A3A2 A1 A020 Luminance delay time 1A 0000YD3YD2YD1YD000 Brightness 1B 0 0 A5 A4 A3 A2 A1 A0 20 Saturation 1C 0 0 A5 A4 A3 A2 A1 A0 20 Contrast 1D 0 0 A5 A4 A3 A2 A1 A0 20 AGC take-over 1E 0 0 A5A4A3A2 A1 A020 Volume control 1F 0 0 A5A4A3A2 A1 A020 Colour decoder 0 20 CM3 CM2 CM1 CM0 MAT MUS ACL CB 00 Colour decoder 1 21 00000PSNSBPSFCO00 AV-switch 0 22 0 0 SVO CMB1 CMB0 INA INB 0 00 AV-switch 1 23 000000 0RGBL00 Synchronisation 0 24 0 HP2 FOA FOB P OC STB VIM VID 00 Synchronisation 1 25 0 0 FSL OSO FORF FORS DL NCIN 00 Deflection 26 0 AFN DFL XDT SBL AVG EVG HCO Vision IF 0 27 0 IFB IFC VSW 0 AFW IFS STM 00 Vision IF 1 28 SIF 0 0 IFLH 0 AGC1 AGC0 FFI 00 Sound 0 29 AGN SM1 FMWS 0 SM0 0 FMB FMA 00 Control 0 2A 0 IE2 RBL AKB CL3 CL2 CL1 CL0 00 Control 1 2B 0 0 VSD SOY 0 YUV1 YUV0 HBL Sound 1 2C 0 0 ADX 0 0 AVL Features 0 2D 0000DSK0 0BKS00 Features 1 2E 0 BPB RPO1 RPO0 0 0 0 0 00

(1)

0A 0 0 A5 A4 A3 A2 A1 A0 20 0B 0 0 A5 A4 A3 A2 A1 A0 20 0C 0 0 A5 A4 A3 A2 A1 A0 20 0D 0 0 A5 A4 A3 A2 A1 A0 20 0E 0 0 A5 A4 A3 A2 A1 A0 20

13 0 0 A5 A4 A3 A2 A1 A0 20

(2)

QSS 0 00

POR

Value

(1)

Table 2: I2C input bits NOTE:

1. These functions are only available in versions that have the East-West drive output.

2. The AVL function is only available in versions which have no East-West drive output or when the subcarrier output is used for the connection of the AVL capacitor (via the bits CMB1, 0 in subaddress 22

hex

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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DATA BYTEFUNCTION SUBADDR

Output status bytes

(HEX)

00 POR IFI LOCK SL CD3 CD2 CD1 CD0 01 XPR NDF FSI IVW WBC HBC BCF IN2 02 SUP X X QSS AFA AFB FMW FML

D7 D6 D5 D4 D3 D2 D1 D0

Table 3: I2C output bits

The TDA937X PS N2 uses an internal I²C-bus to read and write all its functions:

• Write slave address: 8A

• Read slave address: 8B

: A6 A5 A4 A3 A2 A1 A0 R/W: 1 0 0 0 1 0 1 0

HEX

: A6 A5 A4 A3 A2 A1 A0 R/W: 1 0 0 0 1 0 1 1

HEX

For I²C-bus write-transmissions the TDA937X PS N2 has automatic sub-address increment, so multiple data bytes can be sent in one transmission.

Acknowledge acknowledge acknowledge from slave from slave from slave

Sub addressStart Slave address A c k Ack Data Byte Ack Stop

R/W first sub-address multiple data bytes, = = destination of each acknowledged write first data byte by slave

Reading the three status bytes is done without sub-addressing. After receiving the I²C-bus read address, the TDA937X PS N2 always starts with status byte 0.

No acknowledge acknowledge acknowledge from master from slave from master (just clock pulse)

Start Slave addres s

Ack Ack

Status byte 0

Status byte 2

Nack

Stop

R/W = Read 1, 2 or 3 status bytes read

I²C-bus start-up procedure.

The TDA937X PS N2 has many alignment-free internal circuits that are calibrated with the frequency of the reference Xtal oscillator. To ensure correct start-up after the 3.3 Volt is applied, a start-up routine is available which should be included in the software to run as first block. We strongly advice to use this routine to prevent problems with initialising

1. Write all sub addresses from 00

slow start when register 2E

2. Keep reading I

C-bus status bytes till SUP = 1 (+ 8 Volt present)

HEX

to 2E

. When STB is written 1, the horizontal out will begin with

HEX

is written, else the video processor will remain in stand-by.

Note: When the +8 Volt is supplied via the EHT flyback transformer, this has only sense when the device is set in operational mode (STB = 1)

Before the horizontal drive output can become active, all sub-address bytes 00

HEX

to 2E

must be loaded.

HEX

Registers or register bits, not available or defined in certain versions, must be loaded with zero’s for (future) compatibility. Only when the +8 Volt supply is present, the oscillator is calibrated. Non-successful calibration forces SUP to 0 irrespective the + 8 Volt supply to indicate a failure.

Each time before the sub-address bytes are refreshed, the status bytes must be read. If POR=1 then the start-up routine and step 1, 2 must be executed to restart the IC. Not following this procedure may result in undesired conditions after power-up or a power dip (e.g. incorrect horizontal line frequency).

Philips Semiconductors Version 1.0

TDA937X PS N2

TV-processor + µP + CC

Software monitoring or external I2C bus control is possible via the SCL, SDA pins at pins 2 and 3 respectively.

Software monitoring (I ports 1.6/1.7 (SCL, SDA) as open drain and having pull up resistors on these pins. When programming the TXT21.1 (I Monitoring the I Drv_InitUOC() function in the UOC BOOT Library has been called.

External I2C bus control (e.g. with WIC software) of a programmed device is possible via the SCL, SDA pins only when communication between microprocessor and videoprocessor is disabled by customer software. Similarly, customer software can be implemented whereby required registers for alignment etc. can be changed (e.g. Factory Service Mode).

C Port0) then the I2C data can be enabled/disabled on these pins.

C data) between microprocessor and videoprocessor can be done by programming

C data is only possible after the software initialisation is completed therefore when the

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

5.1 INPUT CONTROL BITS

Reg 06 D0..5 HP HOR. PARALLELOGRAM

CORRECTION

Corrects when the vertical lines are not orthogonal on the horizontal lines.

Reg 07 D0..5 HB HOR. BOW CORRECTION Corrects when the top and bottom of the vertical lines are slightly bent from the middle to left or right. This

can be used with black flatline cathode ray tubes to have optimum adjustment of vertical lines.

Reg 08 D0..5 HUE HUE The hue control is active when the NTSC colour system is received

Application Note

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Reg 09 D0..5 HS HORIZONTAL SHIFT Adjusts the horizontal position of the picture on the screen.

Reg 0A D0..5 EW E-W WIDTH Adjusts the picture width. When all higher order terms (BCP, PW, TC, UCP) are aligned, the geometry

corrections will remain correct when changing the EW register for horizontal zoom.

Reg 0B D0..5 PW E-W PARABOLA WIDTH Adjusts the parabola correction.

Reg 0C D0..5 UCP E-W UPPER CORNER

PARABOLA Adjusts the upper curve of the vertical lines. Set UCP in neutral position before starting alignment.

Reg 0D D0..5 BCP E-W BOTTOM CORNER

PARABOLA Adjusts the bottom curve of the vertical lines. Set BCP in neutral position before starting alignment.

Reg 0E D0..5 TC E-W TRAPEZIUM COR. Adjusts the position of the vertical lines at the sides: can be bend inwards or outwards. The vertical lines

remain straight. Set in neutral position before starting alignment.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 0F D0..5 VS VERTICAL SLOPE Adjusts the vertical slope. This alignment is meant to compensate for spread on the value of the external

sawtooth capacitor (major) and spread on the internal reference current source (minor). This is the first vertical alignment to execute in order to adjust the internal levels to exact nominal value. These nominal values are important to ensure that all derived correction waveforms (vertical S and horizontal geo) are correct. Use SBL (service blanking) for correct alignment. See also chapter geometry alignments.

Reg 10 D0..5 VA VERTICAL AMPLITUDE Adjusts vertical amplitude. Adjustment does affect all horizontal geometry corrections and also the vertical

S-correction. Before using VA, first align VS and VSH. Do not use for vertical zoom because overscan is not blanked!

Reg 11 D0..5 SC VERTICAL S-CORRECTION Adjusts the vertical S-correction.

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Reg 12 D0..5 VSH VERTICAL SHIFT Adjusts the vertical shift. This alignment is meant to compensate for vertical offsets like DC offset vertical

amplifier (major), mechanical offset picture tube gun (major) and internal offsets (minor). In this way, exact landing in the vertical middle of the screen is ensured when the vertical deflection current outputs are zero. This alignment must be carried out after alignment of VS and is important to ensure that all derived correction waveforms (vertical S and horizontal geo) are correct. See also chapter geometry alignments.

Reg 13 D0..5 VX VERTICAL ZOOM/EXPAND This bit can be used to shrink the vertical amplitude (compressed 16:9 format on 4:3 tube) or expand the

vertical amplitude (4:3 format on 16:9 tube). The vertical amplitude adjustment is 1 % per step, the neutral position is chosen such (19 height), suitable for displaying compressed 16:9 format on 4:3 tube. When zooming larger than 100 %, vertical overscan larger than 106 % will be blanked to prevent picture tube damage. It is important to set VX in neutral position before starting alignment!

Reg 14 D0..5 BLOR BLK LEVEL OFFSET RED

Reg 15 D0..5 BLOG BLK LEVEL OFFSET GREEN Adjustment of an offset in the red and /or green channel to realise another colour temperature setting for

low lights as for high lights.

HEX

, 25

) that VX = 00 gives 25 % picture height reduction (75% picture

DEC

Reg 16..18 D0..5 WPR, G, B WHITE POINT RGB Adjustment of the white point setting for colour temperature at high light in order to compensate for the

phosphor efficiencies of different CRTs.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 19 D0..5 PEAK PEAKING The peaking on the Y signal can be adjusted with this 6 bit register Reg 1B D0..5 BRI BRIGHTNESS Reg 1C D0..5 SAT SATURATION Reg 1D D0..5 CON CONTRAST

Reg 1A D0..3 YD0..3 Y-DELAY Adjusts the Y delay in order to achieve correct Y and chroma timing

Reg 1E D5..0 AGC TAKE OVER AGC TAKE OVER POINT Reg 1F D5..0 VOLUME CONTROL VOLUME CONTROL

Application Note

AN01045

Reg 20 D0 CB CHROMA BANDPASS

CENTRE FREQUENCY To compensate for the roll-off at higher frequency in the SAW filter / IF part, the centre frequency of the

chroma bandpass can be shifted upwards.

0 = Centre frequency at Fsc (chroma subcarrier frequency) 1 = Centre frequency at 1.1 x Fsc (in principle used for internal mode only)

Reg 20 D1 ACL AUTOMATIC COLOUR

LIMITING For signals with very large chroma/burst ratio this ACL can be enabled to maintain correct colour saturation.

ACL has no influence on colour sensitivity (e.g. colour loss in VCR feature mode). It is not recommended to use the ACL function when SECAM is identified.

0 = ACL function not enabled (for standard burst/chroma transmissions) 1 = ACL function enabled (for non-standard burst/chroma ratio)

Reg 20 D2 MUS MATRIX USA Selects between the two built-in NTSC matrices.

0 = Japanese NTSC matrix 1 = USA NTSC matrix

Reg 20 D3 MAT MATRIX SELECTION Forces PAL matrix, even when NTSC is detected.

When RGB-2 input is used, PAL matrix should be selected for correct colour reproduction (MAT = 0) because the RGB -> YUV conversion is complementary to the PAL matrix.

0 = matrix adapted to standard (PAL matrix or by MUS selected NTSC matrix) 1 = PAL matrix

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 20 D4..7 CM0..3 COLOUR DECODER MODE These bits select one of the automatic modes or forces to one of the standards.

CM3 CM2 CM1 CM0 Colour decoder mode Subcarr. freq.

0 0 0 0 PAL/NTSC A 0 0 0 1 Spare 001 0PAL A 001 1NTSC A 0 1 0 0 Spare 0 1 0 1 PAL/NTSC (auto) B 011 0PAL B 011 1NTSC B 1 0 0 0 PAL/NTSC(auto) ABCD 1 0 0 1 PAL/NTSC(auto) C 101 0PAL C 101 1NTSC C 1 1 0 0 PAL/NTSC (auto tri-normal) BCD 1 1 0 1 PAL/NTSC (auto) D 111 0PAL D 111 1NTSC D

Table 4: Automatic colour standard manager settings

Application Note

AN01045

Frequencies:

- A: 4.433619 MHz

- B: 3.582056 MHz (PAL N)

- C: 3.575611 MHz (PAL M)

- D: 3.579545 MHz (NTSC M)

Reg 21 D0 FCO FORCED COLOUR ON With this bit the colour killer function can be disabled to ensure maximum colour sensitivity under abnormal

conditions e.g. VCR trick modes. Only active when one single colour system is forced.

0 = normal colour killer function 1 = no colour killing (in forced single colour system mode only)

Reg 21 D1 BPS BYPASS CHROMA DELAY

LINE When active then the U, V signals bypass the built-in base band chroma delay line (e.g. for NTSC or

PALplus) and are internally amplified by 6 dB to correct the levels.

0 = Baseband chroma delay line active 1 = Bypass baseband chroma delay line

Reg 21 D2 PSNS PAL SENSITIVITY NOISY

SIGNALS With this bit the colour killer sensitivity level for PAL can be increased for noisy signal conditions. This

feature is intended for the ASIAN countries.

0 = Normal PAL sensitivity, killing level typical 26 dBuV 1 = Increased PAL sensitivity, killing level typical 21 dBuV

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 22 D0, 1 INA, INB INPUT SELECTION Selects CVBS/YC video inputs.

INA INB Selected signal

0 0 CVBS1 0 1 CVBS2/Y 11Y/C

Table 5: Video input selection

Reg 22 D3, 4 CMB0, 1 COMB PIN FUNCTION

CMB1 CMB0 Function

00 0 1 Output voltage 2.3 Volt + subcarrier 1 0 Output voltage 0 Volt 1 1 Output voltage 4.5 volt

Table 6: Comb filter pin function selection

AVL / SNIF active (depends on SIF bit)

Application Note

AN01045

Reg 22 D5 SVO SELECTED VIDEO OUT With this bit it is possible to realise a monitor out function on pin 38.

When SVO = 0, pin 38 delivers the CVBS

out (including sound carrier) from IF.

INT

When SVO = 1, the signal, selected by the CVBS switch is routed to pin 38. At the same time, inside the IF the CVBS

out is muted by forcing VSW = 1.

INT

To realise the monitor out function, both SVO and INA, B must be used.

SVO INA INB Signal on pin 38 Level pk - pk

0 X X CVBS 100

Internal CVBS pin 40 (not CVBS

out + intercarrier sound from IF

INT

from IF!!)

2.5 V

2.0 V

1 0 1 External CVBS pin 42 2.0 V 110Y (pin 42) + C (pin 43) 2.0 V

Table 7: Selected video out options and corresponding video output levels

The level difference is related to technical differences between IF output and needed headroom in the

CVBS switch block.

Intercarrier sound only in case of mono FM versions

Note that in this condition CVBS

out from IF is muted (VSW is forced to 1 for SVO = 1).

INT

When in this condition another CVBS signal (e.g. from a satellite tuner) is fed to the internal CVBS input pin

40, this signal will be available on pin 38.

To have CVBS

out from IF available on pin 38, SVO must be set to 0!!

INT

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 23 D0 RGBL RGB OUTPUTS LOW When this bit is set high, the RGB outputs are below 1.5V. This can be applied at start-up and switch-off for

picture blanking.

0 = normal operation 1 = RGB outputs blanked, black current loop disabled.

Reg 24 D0 VID VIDEO IDENT COUPLING With this bit it is possible to activate a coupling between video ident (IFI) and PHI-1 loop. If this coupling is

active and no video is present (IFI = 0), the PHI-1 loop is switched to very slow. This assures a stable OSD display under noisy conditions e.g. during search tuning or when no antenna input is connected (tuner noise). 0 = Video ident (IFI) switches PHI-1 loop on/off

1 = No influence of the video ident (IFI) on the PHI-1 loop

Reg 24 D1 VIM VIDEO IDENT MODE

Application Note

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The IF ident circuit (output IFI) can be connected to the internal CVBS input (CVBS selection switch to the selected video input for display. (see also VID reg 24 D0)

0 = Video ident circuit coupled to CVBS1 1 = Video ident coupled to selected CVBS or Y/C (see INA, INB)

Reg 24 D2 STB STAND BY When set to 1, the horizontal drive is initialised via slow start. Note that after power-up the horizontal drive

only will be released when POR = 0 and all I the 3.3 Volt supply is present. In this way, the horizontal drive will be initialised via slow start and the + 8 Volt supply can be derived from the flyback transformer. When STB is set to 0, the horizontal drive is stopped via slow stop and the RGB outputs are set for 1 mA discharge current of the picture tube (measured via the black current loop). When no picture tube discharge via RGB drive is needed (e.g. applications with EHT bleeder) it is possible to force black switch-off by setting RBL = 1 together with STB = 0

0 = device in stand-by 1 = device operational

Reg 24 D3 POC PHI ONE CONTROL When this bit is switched to high, the PHI-1 loop is switched off completely.

In this mode very stable OSD or TEXT can be displayed, independent of the selected source. This is useful for e.g. installation menu’s, blue mute, ea. It is also useful to measure the free running frequency using in this condition.

INT

C registers are written. It is possible to set STB to 1 when only

) or after the input

INT

When forcing POC = 1, immediately SL is forced 0. This has the following consequences:

- AFC information is disabled

- Vertical divider switches immediately to mode, set by FORF/FORS

- SL cannot be used to detect a valid CVBS signal on the selected input, IFI can be used for this purpose For stable OSD during search tuning, it is better to use VID in stead of POC, see below:

0 = Synchronisation active 1 = Synchronisation not active

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 24 D4, 5 FOA, FOB FORCED PHI ONE TIME

CONSTANT These two bits determine the speed of the phi-1-loop. It can be forced to slow and fast or set it in the

automatic mode. In auto mode a noise detector circuit can switch to slow time constant, when the signal has too much noise.

Application Note

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FOA FOB PHI –1 loop mode

0 0 Auto, PHI-1 gating in slow mode 0 1 Slow, always gating (only for test purposes.) 1 0 Slow/fast depends on noise detector, always gating 1 1 Fast, no gating

Table 8: PHI-1 loop speed settings

Note:

Suggested use of these bits: Normal off-air reception conditions or cable:

- Use FOA/FOB = 0 0 for program numbers, VCR reception via antenna possible

- Use FOA/FOB = 1 1 for external input (VCR, DVD) Difficult off-air reception conditions (Weak signal and/or interference):

- Use FOA/FOB = 1 0 for program nr. (optimal off-air reception due to gating)

- Use FOA/FOB = 1 1 for special program nr. (program 0) for VCR reception via antenna

- Use FOA/FOB = 1 1 for external input (VCR, DVD)

Reg 24 D6 HP2 HORIZONTAL REFERENCE

Not suitable for weak video recorder signals, because of active ph-1 gating in slow mode. Use FOA,

FOB=1,1 instead.

OSD FROM PHI-2 Determines where the horizontal reference for OSD positioning is taken.

0 = Ref. from PHI-1 (needed when HB and HP (see geo) are used) 1 = Ref. from PHI-2 (For problems with OSD, no HB, HP possible)

Reg 25 D0 NCIN NO VERTICAL

COINCIDENCE Vertical divider mode: This forces the vertical divider immediately to the search window, to speed up vertical

catching at channel change. It saves the time for the vertical divider to switch back from standard mode to narrow window and from narrow window to search window, which takes at least 6 fields.

For optimal performance, NCIN should be set back to 0 when SL becomes 1 (sync lock, indicating a valid input signal is detected) after forcing the vertical divider to the search window.

0 = Normal operation of the vertical divider 1 = Vertical divider switched to search window

Reg 25 D1 DL DE-INTERLACE

0 = Interlace 1 = De-interlace

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 25 D2, 3 FORS/FORF FORCED FIELD

FREQUENCY This forces the vertical divider in a 60 Hz mode or automatic. In auto mode it can be given a preference for

50 or 60 Hz (useful for multi-system situations when video signals are only 50 or 60 Hz) or to keep the last detected field frequency.

FORF FORS Vertical frequency

0 0 Auto, 60 Hz if not locked 0 1 60 Hz forced 1 0 Auto, keep last detected frequency 1 1 Auto, 50 Hz if not locked

Table 9: Vertical frequency selection options

Note:

60 Hz is immediately forced after writing FORF, FORS, so when a 50 Hz signal is present, it will start

rolling.

This mode is useful for areas where both 50 and 60 Hz signals can be received but due to bad reception condition the signal can be lost for a short moment. In that case, vertical catching is fast and screen disturbance remains limited, because the vertical divider does not change the vertical frequency.

Application Note

AN01045

Reg 25 D4 OSO OVERSCAN SWITCH OFF Enable switch-off in vertical overscan. When switching to stand-by, the vertical deflection is kept in overscan

position at the top of the screen while during switch-off the picture tube is discharged with a fixed current so the white drive is less visible

0 = Switch-off undefined 1 = Enable switch-off in vertical overscan function

Reg 25 D5 FSL FIXED VERTICAL SLICING

LEVEL

Forces the slicing level during vertical synchronisation to 60 % amplitude of the sync pulse (measured from black level). Can solve problems with decoders, which insert a wrong and varying black level during vertical synchronisation. Normal, the slicing level during vertical (measured from black level) is 35% at strong signal and 60% at noisy signals (S/N < 20 dB), switched by the built-in noise detector.

0 = Automatic vertical slicing level 1 = Vertical slicing level fixed to 60% of sync amplitude

Reg 26 D0 HCO HOR. COMPENSATION EHT tracking mode. Selects to modulate only vertical or vertical and East-West with the voltage on pin 36.

EHT tracking compensates picture size variations due to beam current variation. HCO = 0 is useful when East-West and vertical require different gain for the compensation. Vertical compensation can then be done via the IC, while the East/West compensation is realised outside the IC with a different gain.

0 = EHT tracking only on vertical 1 = EHT tracking on both vertical and East-West

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 26 D1 EVG ENABLE VERTICAL GUARD

Application Note

AN01045

With this bit set high, a vertical guard failure will immediately blank RGB tube. To use this function, a vertical guard pulse has to be connected to pin 50 (BLKLIN / Vertical guard). When no vertical guard pulse is connected to pin 50, EVG must be set to zero to prevent unwanted blanking of RGB

Reg 26 D2 AVG ADJUSTMENT VG2

When this bit is set high, the vertical deflection remains running and a black bar is visible at the top of the screen. The beam current measurement is done during the black bar. The AVG bit can be used for Vg2 alignment.

Readout of the WBC and HBC bits via OSD in the lower half of the screen can also be used.

Reg 26 D3 SBL SERVICE BLANKING This bit blanks the bottom half of the picture, starting exactly in the middle of the vertical scan (deflection

currents are zero). This bit is intended to align the vertical parameter VS in order to compensate for component tolerances. See also the chapter about geometry alignment.

OUT

0 = Only vertical guard detection (output bit NDF) 1 = Detection (output bit NDF) and protection by blanking RGB

VOLTAGE

0 = Normal operation 1 = Vg2 adjustment (WBC and HBC bits in output byte 01 can be read)

0 = No service blanking 1 = Service blanking active

to avoid damage to the picture

OUT

Reg 26 D4 XDT X-RAY DETECTION This bit selects whether at triggering of the X-ray protection (voltage on pin 36 higher than 3.9 Volt) besides

setting XPR = 1 the device switches automatically off via the slow stop procedure with RGB drive for picture tube discharge or that only the XPR bit is set and latched.

0 = XPR + automatic switch-off 1 = XPR only

Reg 26 D5 DFL DISABLE FLASH PROTECT. The flash protection function on the PHI-2 pin 16 can be disabled using this bit. In this way, unwanted

switch-off from H-out by triggering due to disturbance can be prevented when this function is not used. This increases the robustness (H-out remains running) under conditions like ESD, flash, etc. at the cost of higher stress for line transistor etc.

0 = Flash protection enabled 1 = Flash protection disabled

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 26 D6 AFN AFC NOT ACTIVE The AFC information is updated every vertical retrace. Under weak signal conditions, this updating can

cause some disturbance of the AM sound output. By setting AFN = 1 the AFC updating can be disabled to minimise the disturbance. Advice for use:

- When a PLL tuner is used and the transmitter is stable, switch-off the AFC when receiving AM sound.

- When transmitter drift is expected, enable very short the AFC once every five minutes (two fields is

enough) to retune

0 = AFC normal active, updated every vertical retrace 1 = AFC circuit switched off

Reg 27 D0 STM SEARCH TUNING MODE Can make the coincidence detector less sensitive, to avoid that search tuning systems stop at very weak

signals (output bit SL).

0 = Normal operation 1 = Reduced dynamic sensitivity of coincidence detector (approx. 5 dB)

Note: this function is effective in static signal conditions

Application Note

AN01045

Reg 27 D1 IFS IF SENSITIVITY When switched to an external source, the cross talk of noise on the internal signal to the external signal can

be reduced. This function is mainly intended for no-antenna input conditions.

0 = Normal sensitivity 1 = Maximum gain reduced by 20 dB (sensitivity in practice 12dB less)

Reg 27 D2 AFW AFC WINDOW AFC window around IF centre frequency: (to optimise search-tuning speed, see also output bits AFA and

AFB).

0 = Nominal window, about 100 kHz wide 1 = Enlarged window, about 300 kHz wide

Reg 27 D4 VSW VIDEO MUTE SWITCH When this bit is set to high, it is possible to use the internal CVBS input pin 40 (CVBS1

external CVBS signal.

0 = Normal operation 1 = IF video signal switched off (pin 27 and 38 are forced to ground level)

Reg 27 D5..7 IFB, IFC FREQUENCY SELECTION

) to supply an

INT

IFB IFC IF frequency

0 0 58.75 MHz 0 1 45.75 MHz 1 0 38.90 MHz 1 1 38.00 MHz

Table 10: IF frequency options

These frequencies are suitable for all market areas. Any adaptation on frequency response should be done via the SAW filter.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 28 D0 FFI FAST FILTER IFPLL For RF-transmitter input signals with large phase modulation. (Not suitable for overmodulation, that requires

a slow filter)

0= normal time constant for standard transmitter signals 1= fast time constant for special market areas

The function can be used for both positive and negative modulated signals. The standard loopfilter of 390E/100nF is recommended for both settings of FFI.

Use FFI = 1 only:

- For TV sets for special market areas. Set FFI = 1 during IC-initialisation

- After sale service. Set FFI = 1 via service mode in case of specific field problems. See also application info on the IF-PLL loopfilter pin 37 in the IF Chapter.

Reg 28 D1, 2 AGC0, 1 AGC TIME CONSTANT With previous IC versions an external IF-AGC capacitor was used. The standard value then was 2.2uF that

is now equivalent to the “norm” mode, see table on next page. The AGC speed can be adjusted with AGC1, AGC0 for:

Application Note

AN01045

AGC1, 0 AGC speed Equivalent AGC

capacitor

0 0 0.7 x norm 3.1uF Slow AGC action, reserved if required in the field 0 1 Norm 2.2uF Standard recommended setting, optimal for both

positive and negative modulation

1 0 3 x norm Faster AGC for negative modulation as to

improve airplane flutter performance

1 1 6 x norm Fastest AGC for negative modulation as to

improve airplane flutter performance

Table 11: AGC speed settings

Reg 28 D4 IFLH IF LOCK HOLD Special bit for AV mode. Prevents IF video disturbance in case LOCK becomes zero at high modulation

depth. With IFLH it’s possible to make the IF-PLL calibration under control of IFI and not of LOCK anymore.

0 = standard, auto calibration under control of LOCK 1 = calibration under software control, see below.

Recommended: If VIM = 0 than define IFLH := IFI. If VIM = 1 and in STB mode set VIM=0, so than IFLH := IFI which is same as above If VIM = 1 and in AV mode: set IFLH=1 for no calibration at all. The IC automatically calibrates after poweron or after change of IFB and IFC. Some risk: after a flash the PLL might need re-c alibration as to avoid PLL-out lock. This r e-calibration will not occur unless also a power on reset is active.

Function

Reg 28 D7 SIF SOUND CARRIER IF INPUT

0 = No SIF input, pin can be used for combfilter or AVL 1 = SIF input/output available when CMB0/1 = 00 This allows insertion of external sound pass

filters, also separate SIF signal from a other source can be applied.

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