Philips AN01045 APPLICATION NOTE

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APPLICATION NOTE

Application information for

TV processor + µP + CC decoder

TDA937X PS N2

AN01045

Version 1.0

February 2002

Philips Semiconductors

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

ABSTRACT

This report gives a description of the TDA937X PS N2 version, together with application aspects.

Application Note

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Purchase of Philips I2Ccomponents conveys a license under the I components in the I system conforms to the I

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

defined by Philips.

C patent to use the

C system, provided the

C specifications

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Application Note

Application information for TV Signal

processor & µP & Closed Caption decoder

TDA 937X PS N2

AN01045

Author(s):

D. Allerton

L. Bakema

D. v.d. Brul

T. Bruton

G. Folmer

P.C.T.J. Laro

D. Siersema

E. Arnold

F. Giuliano

J. Liu

T. Lee

System Application, Mainstream T.V. Solutions

Consumer ICs Nijmegen,

The Netherlands

Keywords

Embedded micro-controller

OSD

Closed Caption, VPS

Alignment free IF-PLL, Sound PLL

Synchronisation H/V

Geometry on vertical and E-W

Switches and filters

PAL/NTSC decoder

Delay line

Continuous Cathode Calibration

Date: February 2002

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Summary

This report gives a description of the application aspects of the TDA937X, a combination of TV signal processor plus Closed caption decoder plus embedded microprocessor in one device.

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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CONTENTS

1 INTRODUCTION...................................................................................................................................... 7

2 DEVICE INFORMATION ......................................................................................................................... 9

3 PINNING CONFIGURATION................................................................................................................. 11

4 DEVELOPMENT TOOLS ...................................................................................................................... 13

C CONTROL VIDEO PROCESSOR PART......................................................................................... 17

5.1 INPUT CONTROL BITS.................................................................................................................. 20

5.2 OUTPUT CONTROL BITS ............................................................................................................. 35

6 APPLICATION INFORMATION............................................................................................................. 41

6.1 MICROPROCESSOR.....................................................................................................................45

6.2 IF PART .......................................................................................................................................... 47

6.3 FM SOUND..................................................................................................................................... 50

6.4 QSS SOUND................................................................................................................................... 55

6.5 THE NARROW BAND PLL............................................................................................................. 57

6.6 FILTERS, SWITCHES AND COLOUR DECODER........................................................................ 59

6.7 HORIZONTAL AND VERTICAL SYNC GEOMETRY..................................................................... 63

6.8 GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION ........ 71

6.9 YUV / RGB PROCESSING AND CONTROL.................................................................................. 77

6.10 PICTURE IMPROVEMENT FEATURES ........................................................................................ 89

6.11 SUPPLY, GROUNDING AND DECOUPLING................................................................................ 95

6.12 EMC LAYOUT............................................................................................................................... 107

7 ALIGNMENTS...................................................................................................................................... 109

7.1 TUNER AGC................................................................................................................................. 109

7.2 GEOMETRY.................................................................................................................................. 110

7.3 SCREEN VOLTAGE ALIGNMENT............................................................................................... 114

7.4 COLOUR TEMPERATURE ALIGNMENT .................................................................................... 118

8 BLOCK DIAGRAM .............................................................................................................................. 120

9 INTERNAL PINNING........................................................................................................................... 121

10 APPLICATION EXAMPLE ( DEMO-BOARD ).................................................................................... 128

11 REFERENCES..................................................................................................................................... 129

12 INDEX .................................................................................................................................................. 131

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

1 INTRODUCTION

This report gives hardware/software application information concerning the TDA937x PS N2 family. The TDA937x PS N2 series have both microprocessor and videoprocessor functions integrated in one

single chip and this device is intended for economy TV applications with 90º and 110º picture tubes. Several features are implemented and control of TDA937x functions/features is carried out using the supported I

The microprocessor, which uses an enhanced 80c51-microprocessor core (12MHz clock) has OTP ROM and built in RAM and it caters for:

The videoprocessor includes all the functions necessary for TV processing such as:

C bus and embedded software.

- Closed Caption decoding (subtitle system in USA for people with hearing impediments).

- OSD generation

- Data Capture decoding of either Line 21 Data Services (525 Timing) or Euro-Caption (625 Timing)

- IF video processing and sound (FM + QSS).

- Sync and geometry processing.

- PAL/NTSC colour decoder.

- RGB generation and processing of signals.

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The device is encapsulated in a SDIP64 package (Shrink Dual In-line, 64 pin SOT274-1) and uses both BIMOS and CMOS technologies.

The TDA937X family has been designed in order to have a low external component count for application and a single layer PCB technology can be used.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

2 DEVICE INFORMATION

The TDA937X family offers complete control and small signal video processing needed for TV applications in one device; it includes a microprocessor and a videoprocessor, both being encapsulated in a SDIP64 (Shrink Dual In-line, 64 pins) package. The microprocessor block diagram is shown in chapter 8.

A summary of the functions/features of the microprocessor is:

• Combined 55K x 8 bit OTP Micro-controller Program ROM and 4.5K x 16 bit OTP Character ROM.

• 0.25K x 8 bit Main Data RAM ( Mov address space).

• 2.25K x 8 bit Auxiliary Data RAM (Movx address space).

• Additional 16 bit Timer with 8 bit pre-scaler.

• 4 bit software A/D convert with 4 multiplexed inputs.

• Low resolution PWMs for VST.

• Byte level I2C up to 400KHz.

• Watchdog Timer with 16-bit pre-scaler.

• Three power saving modes : Stand-by, Idle and Power-Down.

• 13 I/O for SDIP64 via individual addressable controls.

• Programmable micro-controller I/O for Push-Pull, Open Drain, Quasi-Bidirectional & highImpedance.

• OSD graphics engine with up to 48 characters in width by 16 rows.

• Closed Caption style organized as 34 characters by 16 rows.

• 256 displayable characters.

• Globally selectable character matrix: 12 x 10, 12 x 13, 12 x 16 and 16 x 18 (h x v).

• Globally selectable horizontal character spacing (up to 4 pixels).

• Globally selectable vertical character spacing (up to 7 TV lines).

• 16 DRCS at up to 16 x 18 character matrix.

• 16 Foreground and 16 Background display colours selectable from a palette of 64.

• Enhanced display features including shadowing, underlining, overlining, italics and smoothing.

• Cursor Function.

• Contrast Reduction.

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The videoprocessor block diagram, which is subdivided into four subsections, is shown in chapter 8 A summary of the functions/features of the

IF video & sound:

− Multi-standard vision IF circuit with alignment free PLL demodulator and IF frequency selection by I

− Internal time constant for IF AGC circuit which can be selected via I

− The FM PLL sound demodulator can be switched between 4.5/5.5/6.0/6.5 MHz frequencies with the I

bus. At these frequencies extra internal selectivity can be selected under critical reception conditions by selecting the internal bandpass filter with the I

− Types available with FM demodulator or with QSS sound output as an input for a stereo decoder..

Filters/Switches & colour decoder:

− CVBS switching between the CVBS from the front end (IF) and CVBS from SCART which can also be used as an Y/C input.

− Integrated chroma trap, chroma bandpass (switchable center frequency with I

− Integrated luminance delay line with adjustable delay time.

− Peaking function including depeaking and a variable positive/negative overshoot ratio .

− Integrated baseband delay line (for NTSC systems can be applied as comb filter).

− ACL implemented for deviating standards having large chroma/burst ratios (>3).

videoprocessor are:

C bus.

C) and cloche filters

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

ACL function switched via I

− PAL/NTSC colour decoder with fully automatic colour search system including LATAM colour decoding for PAL M and PAL N signals.

− Only one 12MHz crystal required for all internal timing e.g. in the microprocessor, Close Caption decoder, OSD and in the video processor IF frequency, sound carrier, colour decoder and horizontal frequency

HV sync & geometry:

− Horizontal synchronization with 2 control loops and alignment free horizontal oscillator

− Vertical count down circuit

− Vertical driver optimized for DC coupled vertical output stages

− Horizontal and vertical geometry processing

− Horizontal and vertical zoom function for 16 : 9 applications

− Horizontal parallelogram and bow correction for large screen picture tubes

Low stress by innovative slow start/stop of H

−

energy Only 3.3V 65mA needed for start up which simplifies the stand-by power supply

−

C bus.

implying a gradual build-up of the EHT and deflection

OUT

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YUV/RGB processing & control:

− Picture improvement features as:

− dynamic skin tone

− black stretching

− contrast reduction possibility during mixed mode of OSD signals

− Linear RGB/YUV/ Y P

bus.

− CC or OSD signals are internally supplied from the CC decoder.

− Independent adjustable colour temperature for high/low light calibration.

− Beam current limiting, peak white limiting and soft clipper.

with fast blanking where the synchronisation on Y signals is possible via I2C

B PR

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

3 PINNING CONFIGURATION

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P1.6/SCL

P1.7/SDA

P2.0/TPWM P3.0/ADC0/PWM0 P3.1/ADC1/PWM1 P3.2/ADC2/PWM2

P3.3/ADC3/PWM3

VSSC/P

P0.5 P0.6

VSSA

I.C.

VP2

DECDIG

PH2LF PH1LF

GND3

DECBG

AVL/EWD

VDRB VDRA

IFIN1 IFIN2

IREF

VSC

AGCOUT

AUDEEM/SIFIN1

DECSDEM/SIFIN2

GND2

SNDPLL/SIFAGC

AVL/SNDIF/

REFO

11 12

14 15 16

22 23 24 25 26

28 29 30 31 32

1 2 3 4 5 6 7 8 9

LEADER

TDA937X PS N2

64P1.3/T1

P1.2/INT0 P1.1/T0

P1.0/INT1

62 61

VDDP RESET

XTALOUT

XTALIN

OSCGND

57 56

VDDC VPE

55 54

VDDA

BO GO

51 50

BLKIN BCLIN

B2/UIN/PbIN

48 47

G2/YIN

R2/VIN/PrIN

INSSW2

AUDOUT C

43 42

CVBS/Y GND1

41 40

CVBS1

VP1 IFVO/SVO

38 37

PLLIF EHTO

AUDEXT/QSSO

35 34

FBISO HOUT

Figure 1: Pinning configuration

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

IC version FM PLL version QSS version East-west Y/N CMB1, 0 bits Pin 20 Pin 28 Pin 29 Pin 31 Pin 32 Pin 35

Table 1: Pin functions for various modes of operation Note

1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF input. This function is selected by means of SIF bit in subaddress 28H.

SNDIF REFO AVL/SNDIF REFO REFO

NY N Y

00 01/10/11 00 01/10/11 00 01/10/11 00 01/10/11

AVL EWD AVL EWD

AUDEEM SIFIN1

DECSDEM SIFIN2

SNDPLL SIFAGC

AUDEXT AUDEXT QSSO AUDEXT QSSO

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

4 DEVELOPMENT TOOLS

To develop with the TDA937XPS/N2 family, the tools, listed below, need to be adapted/upgraded. To order the necessary upgrades, please contact your local marketing representative.

Emulator

Depending on the emulator brand used, the following adaptations are necessary:

HITEX

Currently, Hitex can supply a probe, namely PxTDA93xx-N2, for the TDA935X/6X/8XPS/N2 family, which is also suitable for emulating the TDA937XPS/N2 family, as well. This probe includes all the adapters for the µprocessor bond-outs (SAA5512) and video processor bond-out. (KN10161 QSS/FM).

However, existing UOC-N1 customers can upgrade their system, as well, for emulating the TDA937XPS/N2 devices, as described below. The HITEX with the existing PXSAA55xx probe for emulation of the TDA935X/6X/8X N1 consists of the following PCBs:

1. Main probe PCB, ref. 7313-903-0027-2 or ref. 7313-903-0027-3

2. QFP120 Daughter board PCB, ref. 7313-903-0033-2

3. UOC Interface board, ref. 7313-903-0007-2.

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In order to emulate the TDA937XPS/N2 family devices, the above boards have to be replaced as below:

1. Main probe PCB ref. 7313-903-0027-3 (Only in case version is ref. 7313-903-0027-2)

2. QFP120 Daughter board ref. 7313-903-0264-1 (replaces ref. 7313-903-0033-2)

3. UOC interface board ref. 7313-903-0317-1 (replaces ref. 7313-903-0007-2)

The new Daughter board (ref. 7313-903-2641) plugs into the main probe PCB (ref. 7313-903-0027-3) via an array of connectors, SK1...SK8. This board can accommodate the new υprocessor bond-outs (SAA5512). The new UOC interface board can accommodate the new video processor bond-out. (KN10161 QSS/FM).

BL-MTS Systems Applications Group Southampton supplies the necessary µprocessor, video processor bond-outs for emulation and replacement boards. The new set of boards supports the internal reset feature of the TDA937XPS/N2 family. Before using the probe, a set of jumpers on the Daughter board needs to be set as described below:

J1: HI J2: HI J3: OPEN (not used) J4: OPEN (not used)

A brochure with information about the new probe heads and bondouts is attached to this document. More details can be found in the Application Note PxTDA93xx-N2 available at our Support area on the Semiconductor Internet Site http://www.semiconductors.com.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

ASHLING ULTRA 51

Ashling announced that they would no longer support the existing CTS51 system. They offer full support for the TDA937XPS/N2 with their new Ultra-51 Ashling system. The system is supplied with and adapter (AD-SAA55L+) to use for accommodating the microprocessor bond-out. An additional adapter, ref. 7313-903-03171, is needed for the video-processor bond-out and it can be requested from BL-MTS Systems Applications Group Southampton. Information about the new probe head can be found in the attached brochure.

Display Development Studio (DDS)

The DDS is needed to generate the proper character sets and the matching with the type number of the device.

The new version DDS 2.2 supports the new UOC–N2. PAT/PROMT tool is out of date; it is recommended to use the new PROMPT tool, which is included within DDS 2.2 .It can be downloaded from our Support area on the Semiconductor Internet Site http://www.semiconductors.com.

This Support area is located at http://download.semiconductors.com/protected/video/. To apply for access, please complete the electronic form located at our Support Area:

Application Note

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http://downloads.semiconductors.com/unregistered/

GTV development tool

GTV release 2.0 supports the TDA937XPS/N2 family. Older releases are not suitable for the these devices.

Bench programmer

For programming the TDA937XPS/N2 the bench programmer must be a recent version. These versions can be easily recognized because they have a blue PCB. Some of older bench programmer versions (with green PCB) cannot be used with the TDA937XPS/N2 PS/N1 devices, until a FPGA(s) upgrade is implemented.

Please contact the BL-MTS Systems Applications Group Southampton for more details.

TV demoboard and WIC software

For evaluation, a TV demoboard plus the latest WIC software is available for the TDA937XPS/N2 version

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

5 I

C CONTROL VIDEO PROCESSOR PART

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FUNCTION SUBADDR DATA BYTE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0

Horizontal parallelogram 06 0 0 A5 A4 A3 A2 A1 A0 20 Horizontal Bow 07 0 0 A5A4A3A2 A1 A020 Hue 08 0 0 A5A4A3A2 A1 A000 Horizontal shift (HS) 09 0 0 A5 A4 A3 A2 A1 A0 20 EW width (EW) EW parabola/width (PW) EW upper corner parabola EW lower corner parabola EW trapezium (TC) Vertical slope (VS) 0F 0 0 A5 A4 A 3 A2 A1 A0 20 Vertical amplit ude (V A) 10 0 0 A5 A4 A3 A2 A1 A0 20 S-correction (SC) 11 0 0 A5 A4 A3 A2 A1 A0 20 Vertical shift (VSH) 12 0 0 A5A4A3A2 A1 A020 Vertical zoom (VX) Black level off-set R 14 0 0 A5A4A3A2 A1 A020 Black level off-set G 15 0 0 A5A4A3A2 A1 A020 White point R 16 0 0 A5 A4 A3 A2 A1 A0 20 White point G 17 0 0 A5 A4 A3 A2 A1 A 0 20 White point B 18 0 0 A5 A4 A3 A2 A1 A0 20 Peaking 19 0 0 A5A4A3A2 A1 A020 Luminance delay time 1A 0000YD3YD2YD1YD000 Brightness 1B 0 0 A5 A4 A3 A2 A1 A0 20 Saturation 1C 0 0 A5 A4 A3 A2 A1 A0 20 Contrast 1D 0 0 A5 A4 A3 A2 A1 A0 20 AGC take-over 1E 0 0 A5A4A3A2 A1 A020 Volume control 1F 0 0 A5A4A3A2 A1 A020 Colour decoder 0 20 CM3 CM2 CM1 CM0 MAT MUS ACL CB 00 Colour decoder 1 21 00000PSNSBPSFCO00 AV-switch 0 22 0 0 SVO CMB1 CMB0 INA INB 0 00 AV-switch 1 23 000000 0RGBL00 Synchronisation 0 24 0 HP2 FOA FOB P OC STB VIM VID 00 Synchronisation 1 25 0 0 FSL OSO FORF FORS DL NCIN 00 Deflection 26 0 AFN DFL XDT SBL AVG EVG HCO Vision IF 0 27 0 IFB IFC VSW 0 AFW IFS STM 00 Vision IF 1 28 SIF 0 0 IFLH 0 AGC1 AGC0 FFI 00 Sound 0 29 AGN SM1 FMWS 0 SM0 0 FMB FMA 00 Control 0 2A 0 IE2 RBL AKB CL3 CL2 CL1 CL0 00 Control 1 2B 0 0 VSD SOY 0 YUV1 YUV0 HBL Sound 1 2C 0 0 ADX 0 0 AVL Features 0 2D 0000DSK0 0BKS00 Features 1 2E 0 BPB RPO1 RPO0 0 0 0 0 00

(1)

0A 0 0 A5 A4 A3 A2 A1 A0 20 0B 0 0 A5 A4 A3 A2 A1 A0 20 0C 0 0 A5 A4 A3 A2 A1 A0 20 0D 0 0 A5 A4 A3 A2 A1 A0 20 0E 0 0 A5 A4 A3 A2 A1 A0 20

13 0 0 A5 A4 A3 A2 A1 A0 20

(2)

QSS 0 00

POR

Value

(1)

Table 2: I2C input bits NOTE:

1. These functions are only available in versions that have the East-West drive output.

2. The AVL function is only available in versions which have no East-West drive output or when the subcarrier output is used for the connection of the AVL capacitor (via the bits CMB1, 0 in subaddress 22

hex

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

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DATA BYTEFUNCTION SUBADDR

Output status bytes

(HEX)

00 POR IFI LOCK SL CD3 CD2 CD1 CD0 01 XPR NDF FSI IVW WBC HBC BCF IN2 02 SUP X X QSS AFA AFB FMW FML

D7 D6 D5 D4 D3 D2 D1 D0

Table 3: I2C output bits

The TDA937X PS N2 uses an internal I²C-bus to read and write all its functions:

• Write slave address: 8A

• Read slave address: 8B

: A6 A5 A4 A3 A2 A1 A0 R/W: 1 0 0 0 1 0 1 0

HEX

: A6 A5 A4 A3 A2 A1 A0 R/W: 1 0 0 0 1 0 1 1

HEX

For I²C-bus write-transmissions the TDA937X PS N2 has automatic sub-address increment, so multiple data bytes can be sent in one transmission.

Acknowledge acknowledge acknowledge from slave from slave from slave

Sub addressStart Slave address A c k Ack Data Byte Ack Stop

R/W first sub-address multiple data bytes, = = destination of each acknowledged write first data byte by slave

Reading the three status bytes is done without sub-addressing. After receiving the I²C-bus read address, the TDA937X PS N2 always starts with status byte 0.

No acknowledge acknowledge acknowledge from master from slave from master (just clock pulse)

Start Slave addres s

Ack Ack

Status byte 0

Status byte 2

Nack

Stop

R/W = Read 1, 2 or 3 status bytes read

I²C-bus start-up procedure.

The TDA937X PS N2 has many alignment-free internal circuits that are calibrated with the frequency of the reference Xtal oscillator. To ensure correct start-up after the 3.3 Volt is applied, a start-up routine is available which should be included in the software to run as first block. We strongly advice to use this routine to prevent problems with initialising

1. Write all sub addresses from 00

slow start when register 2E

2. Keep reading I

C-bus status bytes till SUP = 1 (+ 8 Volt present)

HEX

to 2E

. When STB is written 1, the horizontal out will begin with

HEX

is written, else the video processor will remain in stand-by.

Note: When the +8 Volt is supplied via the EHT flyback transformer, this has only sense when the device is set in operational mode (STB = 1)

Before the horizontal drive output can become active, all sub-address bytes 00

HEX

to 2E

must be loaded.

HEX

Registers or register bits, not available or defined in certain versions, must be loaded with zero’s for (future) compatibility. Only when the +8 Volt supply is present, the oscillator is calibrated. Non-successful calibration forces SUP to 0 irrespective the + 8 Volt supply to indicate a failure.

Each time before the sub-address bytes are refreshed, the status bytes must be read. If POR=1 then the start-up routine and step 1, 2 must be executed to restart the IC. Not following this procedure may result in undesired conditions after power-up or a power dip (e.g. incorrect horizontal line frequency).

Philips Semiconductors Version 1.0

TDA937X PS N2

TV-processor + µP + CC

Software monitoring or external I2C bus control is possible via the SCL, SDA pins at pins 2 and 3 respectively.

Software monitoring (I ports 1.6/1.7 (SCL, SDA) as open drain and having pull up resistors on these pins. When programming the TXT21.1 (I Monitoring the I Drv_InitUOC() function in the UOC BOOT Library has been called.

External I2C bus control (e.g. with WIC software) of a programmed device is possible via the SCL, SDA pins only when communication between microprocessor and videoprocessor is disabled by customer software. Similarly, customer software can be implemented whereby required registers for alignment etc. can be changed (e.g. Factory Service Mode).

C Port0) then the I2C data can be enabled/disabled on these pins.

C data) between microprocessor and videoprocessor can be done by programming

C data is only possible after the software initialisation is completed therefore when the

Application Note

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Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

5.1 INPUT CONTROL BITS

Reg 06 D0..5 HP HOR. PARALLELOGRAM

CORRECTION

Corrects when the vertical lines are not orthogonal on the horizontal lines.

Reg 07 D0..5 HB HOR. BOW CORRECTION Corrects when the top and bottom of the vertical lines are slightly bent from the middle to left or right. This

can be used with black flatline cathode ray tubes to have optimum adjustment of vertical lines.

Reg 08 D0..5 HUE HUE The hue control is active when the NTSC colour system is received

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Reg 09 D0..5 HS HORIZONTAL SHIFT Adjusts the horizontal position of the picture on the screen.

Reg 0A D0..5 EW E-W WIDTH Adjusts the picture width. When all higher order terms (BCP, PW, TC, UCP) are aligned, the geometry

corrections will remain correct when changing the EW register for horizontal zoom.

Reg 0B D0..5 PW E-W PARABOLA WIDTH Adjusts the parabola correction.

Reg 0C D0..5 UCP E-W UPPER CORNER

PARABOLA Adjusts the upper curve of the vertical lines. Set UCP in neutral position before starting alignment.

Reg 0D D0..5 BCP E-W BOTTOM CORNER

PARABOLA Adjusts the bottom curve of the vertical lines. Set BCP in neutral position before starting alignment.

Reg 0E D0..5 TC E-W TRAPEZIUM COR. Adjusts the position of the vertical lines at the sides: can be bend inwards or outwards. The vertical lines

remain straight. Set in neutral position before starting alignment.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 0F D0..5 VS VERTICAL SLOPE Adjusts the vertical slope. This alignment is meant to compensate for spread on the value of the external

sawtooth capacitor (major) and spread on the internal reference current source (minor). This is the first vertical alignment to execute in order to adjust the internal levels to exact nominal value. These nominal values are important to ensure that all derived correction waveforms (vertical S and horizontal geo) are correct. Use SBL (service blanking) for correct alignment. See also chapter geometry alignments.

Reg 10 D0..5 VA VERTICAL AMPLITUDE Adjusts vertical amplitude. Adjustment does affect all horizontal geometry corrections and also the vertical

S-correction. Before using VA, first align VS and VSH. Do not use for vertical zoom because overscan is not blanked!

Reg 11 D0..5 SC VERTICAL S-CORRECTION Adjusts the vertical S-correction.

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Reg 12 D0..5 VSH VERTICAL SHIFT Adjusts the vertical shift. This alignment is meant to compensate for vertical offsets like DC offset vertical

amplifier (major), mechanical offset picture tube gun (major) and internal offsets (minor). In this way, exact landing in the vertical middle of the screen is ensured when the vertical deflection current outputs are zero. This alignment must be carried out after alignment of VS and is important to ensure that all derived correction waveforms (vertical S and horizontal geo) are correct. See also chapter geometry alignments.

Reg 13 D0..5 VX VERTICAL ZOOM/EXPAND This bit can be used to shrink the vertical amplitude (compressed 16:9 format on 4:3 tube) or expand the

vertical amplitude (4:3 format on 16:9 tube). The vertical amplitude adjustment is 1 % per step, the neutral position is chosen such (19 height), suitable for displaying compressed 16:9 format on 4:3 tube. When zooming larger than 100 %, vertical overscan larger than 106 % will be blanked to prevent picture tube damage. It is important to set VX in neutral position before starting alignment!

Reg 14 D0..5 BLOR BLK LEVEL OFFSET RED

Reg 15 D0..5 BLOG BLK LEVEL OFFSET GREEN Adjustment of an offset in the red and /or green channel to realise another colour temperature setting for

low lights as for high lights.

HEX

, 25

) that VX = 00 gives 25 % picture height reduction (75% picture

DEC

Reg 16..18 D0..5 WPR, G, B WHITE POINT RGB Adjustment of the white point setting for colour temperature at high light in order to compensate for the

phosphor efficiencies of different CRTs.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 19 D0..5 PEAK PEAKING The peaking on the Y signal can be adjusted with this 6 bit register Reg 1B D0..5 BRI BRIGHTNESS Reg 1C D0..5 SAT SATURATION Reg 1D D0..5 CON CONTRAST

Reg 1A D0..3 YD0..3 Y-DELAY Adjusts the Y delay in order to achieve correct Y and chroma timing

Reg 1E D5..0 AGC TAKE OVER AGC TAKE OVER POINT Reg 1F D5..0 VOLUME CONTROL VOLUME CONTROL

Application Note

AN01045

Reg 20 D0 CB CHROMA BANDPASS

CENTRE FREQUENCY To compensate for the roll-off at higher frequency in the SAW filter / IF part, the centre frequency of the

chroma bandpass can be shifted upwards.

0 = Centre frequency at Fsc (chroma subcarrier frequency) 1 = Centre frequency at 1.1 x Fsc (in principle used for internal mode only)

Reg 20 D1 ACL AUTOMATIC COLOUR

LIMITING For signals with very large chroma/burst ratio this ACL can be enabled to maintain correct colour saturation.

ACL has no influence on colour sensitivity (e.g. colour loss in VCR feature mode). It is not recommended to use the ACL function when SECAM is identified.

0 = ACL function not enabled (for standard burst/chroma transmissions) 1 = ACL function enabled (for non-standard burst/chroma ratio)

Reg 20 D2 MUS MATRIX USA Selects between the two built-in NTSC matrices.

0 = Japanese NTSC matrix 1 = USA NTSC matrix

Reg 20 D3 MAT MATRIX SELECTION Forces PAL matrix, even when NTSC is detected.

When RGB-2 input is used, PAL matrix should be selected for correct colour reproduction (MAT = 0) because the RGB -> YUV conversion is complementary to the PAL matrix.

0 = matrix adapted to standard (PAL matrix or by MUS selected NTSC matrix) 1 = PAL matrix

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 20 D4..7 CM0..3 COLOUR DECODER MODE These bits select one of the automatic modes or forces to one of the standards.

CM3 CM2 CM1 CM0 Colour decoder mode Subcarr. freq.

0 0 0 0 PAL/NTSC A 0 0 0 1 Spare 001 0PAL A 001 1NTSC A 0 1 0 0 Spare 0 1 0 1 PAL/NTSC (auto) B 011 0PAL B 011 1NTSC B 1 0 0 0 PAL/NTSC(auto) ABCD 1 0 0 1 PAL/NTSC(auto) C 101 0PAL C 101 1NTSC C 1 1 0 0 PAL/NTSC (auto tri-normal) BCD 1 1 0 1 PAL/NTSC (auto) D 111 0PAL D 111 1NTSC D

Table 4: Automatic colour standard manager settings

Application Note

AN01045

Frequencies:

- A: 4.433619 MHz

- B: 3.582056 MHz (PAL N)

- C: 3.575611 MHz (PAL M)

- D: 3.579545 MHz (NTSC M)

Reg 21 D0 FCO FORCED COLOUR ON With this bit the colour killer function can be disabled to ensure maximum colour sensitivity under abnormal

conditions e.g. VCR trick modes. Only active when one single colour system is forced.

0 = normal colour killer function 1 = no colour killing (in forced single colour system mode only)

Reg 21 D1 BPS BYPASS CHROMA DELAY

LINE When active then the U, V signals bypass the built-in base band chroma delay line (e.g. for NTSC or

PALplus) and are internally amplified by 6 dB to correct the levels.

0 = Baseband chroma delay line active 1 = Bypass baseband chroma delay line

Reg 21 D2 PSNS PAL SENSITIVITY NOISY

SIGNALS With this bit the colour killer sensitivity level for PAL can be increased for noisy signal conditions. This

feature is intended for the ASIAN countries.

0 = Normal PAL sensitivity, killing level typical 26 dBuV 1 = Increased PAL sensitivity, killing level typical 21 dBuV

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 22 D0, 1 INA, INB INPUT SELECTION Selects CVBS/YC video inputs.

INA INB Selected signal

0 0 CVBS1 0 1 CVBS2/Y 11Y/C

Table 5: Video input selection

Reg 22 D3, 4 CMB0, 1 COMB PIN FUNCTION

CMB1 CMB0 Function

00 0 1 Output voltage 2.3 Volt + subcarrier 1 0 Output voltage 0 Volt 1 1 Output voltage 4.5 volt

Table 6: Comb filter pin function selection

AVL / SNIF active (depends on SIF bit)

Application Note

AN01045

Reg 22 D5 SVO SELECTED VIDEO OUT With this bit it is possible to realise a monitor out function on pin 38.

When SVO = 0, pin 38 delivers the CVBS

out (including sound carrier) from IF.

INT

When SVO = 1, the signal, selected by the CVBS switch is routed to pin 38. At the same time, inside the IF the CVBS

out is muted by forcing VSW = 1.

INT

To realise the monitor out function, both SVO and INA, B must be used.

SVO INA INB Signal on pin 38 Level pk - pk

0 X X CVBS 100

Internal CVBS pin 40 (not CVBS

out + intercarrier sound from IF

INT

from IF!!)

2.5 V

2.0 V

1 0 1 External CVBS pin 42 2.0 V 110Y (pin 42) + C (pin 43) 2.0 V

Table 7: Selected video out options and corresponding video output levels

The level difference is related to technical differences between IF output and needed headroom in the

CVBS switch block.

Intercarrier sound only in case of mono FM versions

Note that in this condition CVBS

out from IF is muted (VSW is forced to 1 for SVO = 1).

INT

When in this condition another CVBS signal (e.g. from a satellite tuner) is fed to the internal CVBS input pin

40, this signal will be available on pin 38.

To have CVBS

out from IF available on pin 38, SVO must be set to 0!!

INT

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 23 D0 RGBL RGB OUTPUTS LOW When this bit is set high, the RGB outputs are below 1.5V. This can be applied at start-up and switch-off for

picture blanking.

0 = normal operation 1 = RGB outputs blanked, black current loop disabled.

Reg 24 D0 VID VIDEO IDENT COUPLING With this bit it is possible to activate a coupling between video ident (IFI) and PHI-1 loop. If this coupling is

active and no video is present (IFI = 0), the PHI-1 loop is switched to very slow. This assures a stable OSD display under noisy conditions e.g. during search tuning or when no antenna input is connected (tuner noise). 0 = Video ident (IFI) switches PHI-1 loop on/off

1 = No influence of the video ident (IFI) on the PHI-1 loop

Reg 24 D1 VIM VIDEO IDENT MODE

Application Note

AN01045

The IF ident circuit (output IFI) can be connected to the internal CVBS input (CVBS selection switch to the selected video input for display. (see also VID reg 24 D0)

0 = Video ident circuit coupled to CVBS1 1 = Video ident coupled to selected CVBS or Y/C (see INA, INB)

Reg 24 D2 STB STAND BY When set to 1, the horizontal drive is initialised via slow start. Note that after power-up the horizontal drive

only will be released when POR = 0 and all I the 3.3 Volt supply is present. In this way, the horizontal drive will be initialised via slow start and the + 8 Volt supply can be derived from the flyback transformer. When STB is set to 0, the horizontal drive is stopped via slow stop and the RGB outputs are set for 1 mA discharge current of the picture tube (measured via the black current loop). When no picture tube discharge via RGB drive is needed (e.g. applications with EHT bleeder) it is possible to force black switch-off by setting RBL = 1 together with STB = 0

0 = device in stand-by 1 = device operational

Reg 24 D3 POC PHI ONE CONTROL When this bit is switched to high, the PHI-1 loop is switched off completely.

In this mode very stable OSD or TEXT can be displayed, independent of the selected source. This is useful for e.g. installation menu’s, blue mute, ea. It is also useful to measure the free running frequency using in this condition.

INT

C registers are written. It is possible to set STB to 1 when only

) or after the input

INT

When forcing POC = 1, immediately SL is forced 0. This has the following consequences:

- AFC information is disabled

- Vertical divider switches immediately to mode, set by FORF/FORS

- SL cannot be used to detect a valid CVBS signal on the selected input, IFI can be used for this purpose For stable OSD during search tuning, it is better to use VID in stead of POC, see below:

0 = Synchronisation active 1 = Synchronisation not active

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 24 D4, 5 FOA, FOB FORCED PHI ONE TIME

CONSTANT These two bits determine the speed of the phi-1-loop. It can be forced to slow and fast or set it in the

automatic mode. In auto mode a noise detector circuit can switch to slow time constant, when the signal has too much noise.

Application Note

AN01045

FOA FOB PHI –1 loop mode

0 0 Auto, PHI-1 gating in slow mode 0 1 Slow, always gating (only for test purposes.) 1 0 Slow/fast depends on noise detector, always gating 1 1 Fast, no gating

Table 8: PHI-1 loop speed settings

Note:

Suggested use of these bits: Normal off-air reception conditions or cable:

- Use FOA/FOB = 0 0 for program numbers, VCR reception via antenna possible

- Use FOA/FOB = 1 1 for external input (VCR, DVD) Difficult off-air reception conditions (Weak signal and/or interference):

- Use FOA/FOB = 1 0 for program nr. (optimal off-air reception due to gating)

- Use FOA/FOB = 1 1 for special program nr. (program 0) for VCR reception via antenna

- Use FOA/FOB = 1 1 for external input (VCR, DVD)

Reg 24 D6 HP2 HORIZONTAL REFERENCE

Not suitable for weak video recorder signals, because of active ph-1 gating in slow mode. Use FOA,

FOB=1,1 instead.

OSD FROM PHI-2 Determines where the horizontal reference for OSD positioning is taken.

0 = Ref. from PHI-1 (needed when HB and HP (see geo) are used) 1 = Ref. from PHI-2 (For problems with OSD, no HB, HP possible)

Reg 25 D0 NCIN NO VERTICAL

COINCIDENCE Vertical divider mode: This forces the vertical divider immediately to the search window, to speed up vertical

catching at channel change. It saves the time for the vertical divider to switch back from standard mode to narrow window and from narrow window to search window, which takes at least 6 fields.

For optimal performance, NCIN should be set back to 0 when SL becomes 1 (sync lock, indicating a valid input signal is detected) after forcing the vertical divider to the search window.

0 = Normal operation of the vertical divider 1 = Vertical divider switched to search window

Reg 25 D1 DL DE-INTERLACE

0 = Interlace 1 = De-interlace

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 25 D2, 3 FORS/FORF FORCED FIELD

FREQUENCY This forces the vertical divider in a 60 Hz mode or automatic. In auto mode it can be given a preference for

50 or 60 Hz (useful for multi-system situations when video signals are only 50 or 60 Hz) or to keep the last detected field frequency.

FORF FORS Vertical frequency

0 0 Auto, 60 Hz if not locked 0 1 60 Hz forced 1 0 Auto, keep last detected frequency 1 1 Auto, 50 Hz if not locked

Table 9: Vertical frequency selection options

Note:

60 Hz is immediately forced after writing FORF, FORS, so when a 50 Hz signal is present, it will start

rolling.

This mode is useful for areas where both 50 and 60 Hz signals can be received but due to bad reception condition the signal can be lost for a short moment. In that case, vertical catching is fast and screen disturbance remains limited, because the vertical divider does not change the vertical frequency.

Application Note

AN01045

Reg 25 D4 OSO OVERSCAN SWITCH OFF Enable switch-off in vertical overscan. When switching to stand-by, the vertical deflection is kept in overscan

position at the top of the screen while during switch-off the picture tube is discharged with a fixed current so the white drive is less visible

0 = Switch-off undefined 1 = Enable switch-off in vertical overscan function

Reg 25 D5 FSL FIXED VERTICAL SLICING

LEVEL

Forces the slicing level during vertical synchronisation to 60 % amplitude of the sync pulse (measured from black level). Can solve problems with decoders, which insert a wrong and varying black level during vertical synchronisation. Normal, the slicing level during vertical (measured from black level) is 35% at strong signal and 60% at noisy signals (S/N < 20 dB), switched by the built-in noise detector.

0 = Automatic vertical slicing level 1 = Vertical slicing level fixed to 60% of sync amplitude

Reg 26 D0 HCO HOR. COMPENSATION EHT tracking mode. Selects to modulate only vertical or vertical and East-West with the voltage on pin 36.

EHT tracking compensates picture size variations due to beam current variation. HCO = 0 is useful when East-West and vertical require different gain for the compensation. Vertical compensation can then be done via the IC, while the East/West compensation is realised outside the IC with a different gain.

0 = EHT tracking only on vertical 1 = EHT tracking on both vertical and East-West

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 26 D1 EVG ENABLE VERTICAL GUARD

Application Note

AN01045

With this bit set high, a vertical guard failure will immediately blank RGB tube. To use this function, a vertical guard pulse has to be connected to pin 50 (BLKLIN / Vertical guard). When no vertical guard pulse is connected to pin 50, EVG must be set to zero to prevent unwanted blanking of RGB

Reg 26 D2 AVG ADJUSTMENT VG2

When this bit is set high, the vertical deflection remains running and a black bar is visible at the top of the screen. The beam current measurement is done during the black bar. The AVG bit can be used for Vg2 alignment.

Readout of the WBC and HBC bits via OSD in the lower half of the screen can also be used.

Reg 26 D3 SBL SERVICE BLANKING This bit blanks the bottom half of the picture, starting exactly in the middle of the vertical scan (deflection

currents are zero). This bit is intended to align the vertical parameter VS in order to compensate for component tolerances. See also the chapter about geometry alignment.

OUT

0 = Only vertical guard detection (output bit NDF) 1 = Detection (output bit NDF) and protection by blanking RGB

VOLTAGE

0 = Normal operation 1 = Vg2 adjustment (WBC and HBC bits in output byte 01 can be read)

0 = No service blanking 1 = Service blanking active

to avoid damage to the picture

OUT

Reg 26 D4 XDT X-RAY DETECTION This bit selects whether at triggering of the X-ray protection (voltage on pin 36 higher than 3.9 Volt) besides

setting XPR = 1 the device switches automatically off via the slow stop procedure with RGB drive for picture tube discharge or that only the XPR bit is set and latched.

0 = XPR + automatic switch-off 1 = XPR only

Reg 26 D5 DFL DISABLE FLASH PROTECT. The flash protection function on the PHI-2 pin 16 can be disabled using this bit. In this way, unwanted

switch-off from H-out by triggering due to disturbance can be prevented when this function is not used. This increases the robustness (H-out remains running) under conditions like ESD, flash, etc. at the cost of higher stress for line transistor etc.

0 = Flash protection enabled 1 = Flash protection disabled

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 26 D6 AFN AFC NOT ACTIVE The AFC information is updated every vertical retrace. Under weak signal conditions, this updating can

cause some disturbance of the AM sound output. By setting AFN = 1 the AFC updating can be disabled to minimise the disturbance. Advice for use:

- When a PLL tuner is used and the transmitter is stable, switch-off the AFC when receiving AM sound.

- When transmitter drift is expected, enable very short the AFC once every five minutes (two fields is

enough) to retune

0 = AFC normal active, updated every vertical retrace 1 = AFC circuit switched off

Reg 27 D0 STM SEARCH TUNING MODE Can make the coincidence detector less sensitive, to avoid that search tuning systems stop at very weak

signals (output bit SL).

0 = Normal operation 1 = Reduced dynamic sensitivity of coincidence detector (approx. 5 dB)

Note: this function is effective in static signal conditions

Application Note

AN01045

Reg 27 D1 IFS IF SENSITIVITY When switched to an external source, the cross talk of noise on the internal signal to the external signal can

be reduced. This function is mainly intended for no-antenna input conditions.

0 = Normal sensitivity 1 = Maximum gain reduced by 20 dB (sensitivity in practice 12dB less)

Reg 27 D2 AFW AFC WINDOW AFC window around IF centre frequency: (to optimise search-tuning speed, see also output bits AFA and

AFB).

0 = Nominal window, about 100 kHz wide 1 = Enlarged window, about 300 kHz wide

Reg 27 D4 VSW VIDEO MUTE SWITCH When this bit is set to high, it is possible to use the internal CVBS input pin 40 (CVBS1

external CVBS signal.

0 = Normal operation 1 = IF video signal switched off (pin 27 and 38 are forced to ground level)

Reg 27 D5..7 IFB, IFC FREQUENCY SELECTION

) to supply an

INT

IFB IFC IF frequency

0 0 58.75 MHz 0 1 45.75 MHz 1 0 38.90 MHz 1 1 38.00 MHz

Table 10: IF frequency options

These frequencies are suitable for all market areas. Any adaptation on frequency response should be done via the SAW filter.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 28 D0 FFI FAST FILTER IFPLL For RF-transmitter input signals with large phase modulation. (Not suitable for overmodulation, that requires

a slow filter)

0= normal time constant for standard transmitter signals 1= fast time constant for special market areas

The function can be used for both positive and negative modulated signals. The standard loopfilter of 390E/100nF is recommended for both settings of FFI.

Use FFI = 1 only:

- For TV sets for special market areas. Set FFI = 1 during IC-initialisation

- After sale service. Set FFI = 1 via service mode in case of specific field problems. See also application info on the IF-PLL loopfilter pin 37 in the IF Chapter.

Reg 28 D1, 2 AGC0, 1 AGC TIME CONSTANT With previous IC versions an external IF-AGC capacitor was used. The standard value then was 2.2uF that

is now equivalent to the “norm” mode, see table on next page. The AGC speed can be adjusted with AGC1, AGC0 for:

Application Note

AN01045

AGC1, 0 AGC speed Equivalent AGC

capacitor

0 0 0.7 x norm 3.1uF Slow AGC action, reserved if required in the field 0 1 Norm 2.2uF Standard recommended setting, optimal for both

positive and negative modulation

1 0 3 x norm Faster AGC for negative modulation as to

improve airplane flutter performance

1 1 6 x norm Fastest AGC for negative modulation as to

improve airplane flutter performance

Table 11: AGC speed settings

Reg 28 D4 IFLH IF LOCK HOLD Special bit for AV mode. Prevents IF video disturbance in case LOCK becomes zero at high modulation

depth. With IFLH it’s possible to make the IF-PLL calibration under control of IFI and not of LOCK anymore.

0 = standard, auto calibration under control of LOCK 1 = calibration under software control, see below.

Recommended: If VIM = 0 than define IFLH := IFI. If VIM = 1 and in STB mode set VIM=0, so than IFLH := IFI which is same as above If VIM = 1 and in AV mode: set IFLH=1 for no calibration at all. The IC automatically calibrates after poweron or after change of IFB and IFC. Some risk: after a flash the PLL might need re-c alibration as to avoid PLL-out lock. This r e-calibration will not occur unless also a power on reset is active.

Function

Reg 28 D7 SIF SOUND CARRIER IF INPUT

0 = No SIF input, pin can be used for combfilter or AVL 1 = SIF input/output available when CMB0/1 = 00 This allows insertion of external sound pass

filters, also separate SIF signal from a other source can be applied.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 29 D0..2 FMB, FMA FM SOUND CARRIER

SELECTION

FMB FMA Frequency

0 0 5.5 MHz 0 1 6.0 MHz 1 0 4.5 MHz 1 1 6.5 MHz

Table 12: Sound carrier selection

Reg 29 D3, 6 SM0, 1 SOUND MUTE

SM1 SM0 Mute at de-emphasis pin 28

0 1 Sound enhancer ( digital acquisition pulse limiter ) 1 0 Mute on 1 1 Mute off

Table 13: Sound mute options

The sound enhance option improves the sound noise behaviour under weak signal conditions. The acquisition pulses are real time automatically muted. Recommended setting:

01 for no mute condition (when e.g. SL=1 and IFI = 1)

10 for mute condition (when e.g. SL = 0 or IFI = 0) Note: Mute on (SM1, 0 10) sets AVL (if present) in high gain mode (15dB) for fast settling time during channel switching.

Application Note

AN01045

Reg 29 D5 FMWS FM SEARCH WINDOW

WIDTH

0 = Standard acquisition window for narrow band PLL (+ and -225kHz)

1 = Wide acquisition window for narrow band PLL (+ and -450kHz) for signals with large FM swing.

The wide window setting allows more overmodulation of the soundcarrier with FM signals.

Reg 29 D7 AGN GAIN FM DEMODULATOR Enables +6dB extra gain in the FM demodulator. To be used for 25kHz deviation NTSC video standard or

for specific customer needs.

0 = normal operation

1 = gain + 6dB Note: THD figures are higher in +6dB condition.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 2A D0..3 CL0..3 CATHODE DRIVE LEVEL This can be used to adapt the black/white drive of the RGB outputs to match the required drive level for the

picture tube. The table gives approximated values.

CL3 CL2 CL1 CL0 Variation Cathode Drive Level

0 0 0 0 50 V 1 0 0 0 74 V 1 1 1 1 95 V

Table 14: Cathode drive level Conditions:

- Nominal CVBS input signal (1 V pk-pk at CVBS input 40 or 42)

- Nominal settings for contrast, WPA and no peaking

- Black stretch switched off

- Gain of output stage such that no clipping occurs

- Beam current limiting not active

- Tolerance on given values: +/- 3 V.

BL-WH BL-WH BL-WH

Application Note

AN01045

Reg 2A D4 AKB AUTO KINE BIASING With this bit, the automatic black current stabilisation loop can be switched off. This can be used for LCD

application and other applications without picture tubes.

0 = Automatic black-current stabilisation (ABS) loop enabled

1 = ABS loop disabled (suitable for LCD applications)

Reg 2A D5 RBL RGB BLANKING Controls blanking of the RGB outputs. Can be used to keep the picture black at start-up of the set until the

CCC loop is stabilised and the cathode emission is high enough to display a decent picture. Setting RBL = 1 before switching to Stand-By prevents the RGB outputs going high and discharging the picture tube with a white flash.

Can also be used for blanking RGB outputs when black current loop is disabled (AKB = 1) for LCD applications.

0 = Normal picture visible

1 = RGB

Reg 2A D6 IE2 RGB INSERTION ENABLE Enable fast blanking (pin 45) of YUV/RGB-2 input.

0 = Second fast blanking disabled

1 = Normal fast blanking function

(pins 51, 52, 53) blanked

OUT

(FAST BLANKING.)

Reg 2B D0 HBL HOR. BLANKING MODE Widens the horizontal blanking for well defined edges using underscan (e.g displaying 4:3 picture on 16:9

picture tube)

0 = Normal horizontal blanking, related to horizontal flyback pulse width

1 = Wider blanking (coupled to PHI-1)

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 2B D1 YUV0, 1 RGB/YUV INPUT SELECTION

FOR PIN 46, 47, 48

YUV1 YUV0 Mode

0 0 RGB input activated 0 1 Spare 1 0 YUV activated 11YPbPr

Table 15: RGB/YUV input selection modes Note: For the RGB input the synchronisation has to be fed to CVBS on pin 42.

Reg 2B D4 SOY SYNC ON Y

Reg 2B D5 VSD VERTICAL SCAN

DISABLE

To be used for Vg2 alignment. Setting the bit =1 sets the vertical deflection to zero (line in the middle of the

screen).

The black level can be adjusted via the brightness control to the required DC level so that the correct cut-off

levels can be made at the CRT cathodes.

The Vg2 can then be adjusted so that a visible line is just shown. For more accurate Vg2 alignment the beam current can be set to 12-20 µA using the read-out bits HBC

(above / below) and WBC (beam current between 12-20 µA).

These bits are only valid when VSD = 1.

0 = Normal vertical deflection

1 = Vg2 alignment mode, No vertical deflection, HBC and WBC (valid for black levels >2.5V at the

RGB outputs)

Application Note

AN01045

Reg 2C D1 QSS MODE QSS AMPLIFIER Switches the QSS amplifier on and off

0 = QSS amp not active

1 = QSS amp active

Reg 2C D2 AVL AUTOMATIC VOLUME

LEVELING 0 = AVL not active 1 = AVL active and regulates high audio levels as e.g. from TV commercials

Reg 2C D5 ADX AUDIO EXTERN Switch between internal and external sound

ADX Audio selection

0 Internal audio signal 1 External audio signal

Table 16 Audio selection options

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 2D D0 BKS BLACK STRETCH This function stretches offsets in black of non-standard signals to black level

0 = Black stretch off 1 = Black stretch on (to be switched off for WPA adjust)

Reg 2D D3 DSK DYNAMIC SKIN TONE Enables dynamic skin tone function.

0 = off 1 = on

Reg 2E D4, 5 RPO0, 1 RATIO PRE _OVERSHOOT

RPO1 RPO0 Setting

001:1 0 1 1:1.25 1 0 1:1.5 1 1 1:1.8

Table 17: Ratio pre- and overshoot

Application Note

AN01045

Reg 2E D6 BPB BANDPASS FILTER BYPASS Bypasses the internal bandpass filter.

0 = bandpass filter switched on (default) 1 = bandpass filter bypassed

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

5.2 OUTPUT CONTROL BITS

Reg 00 D0..3 CD0..3 COLOUR DETECTION Shows the colour standard that is identified

CD3 CD2 CD1 CD0 Colour standard Subcarr. Freq

0 0 0 0 no colour standard identified 0001 NTSC A 0010 PAL A 0011 NTSC B 0100 PAL B 0101 NTSC C 0110 PAL C 0111 NTSC D 1000 PAL D

Table 18: Detected colour standard

Application Note

AN01045

Frequencies:

- A: 4.433619 MHz

- B: 3.582056 MHz (PAL N)

- C: 3.575611 MHz (PAL M)

- D: 3.579545 MHz (NTSC M)

Reg 00 D4 SL SYNC LOCK Horizontal lock indication:

0 = Not locked 1 = PHI-1 loop locked to the incoming video signal

Reg 00 D5 LOCK IF-PLL LOCK The lock bit becomes one when the IF-PLL is in-lock, independent upon video contents. This means the bit

can also be used to identify sound carrier signals.

0 = PLL not locked 1 = PLL locked

Note: AFC information is only valid when LOCK=1, see related bit, IFLH

Reg 00 D6 IFI VIDEO IF IDENT Detects video at IF or selected source (see also VIM bit). This is a stand-alone detector that recognises

video signals, containing line frequent components.

0 = No video signal identified 1 = Video signal identified

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 00 D7 POR POWER ON RESET Power on reset: Indicates detection of a power failure of the 3.3 Volt supply (including switch-off of the TV

set). It remains high until the status bytes have been read successfully to enable also to detect short power failures. When a failure is detected, the internal data is not reliable any more and should be refreshed. During normal operation the POR status should be read continuously, before sending any input data. During start-up, the µprocessor part should read the IC status until the POR bit is low, immediately followed by the start-up procedure.

0 = Device operational 1 = Power failure detected

Reg 01 D0 IN2 RGB/YUV INPUT2 STATUS Reflects the level on the fast blanking input pin 45.

Level is only checked during vertical retrace to enable differentiation between OSD insertion (IN2 remains

0) and full RGB/YUV sources (IN2 becomes 1) 0 = Pin 45 low (< 0.4V), no insertion 1 = Pin 45 above insertion level (>0.9V, RGB/YUV

inserted when IE2=1)

Application Note

AN01045

Reg 01 D1 BCF BLACK CURRENT LOOP

FALSE

Reflects the condition of the black current loop. Can be used at start-up or for regular check during normal operation to indicate RGB stage malfunctioning.

0 = Black current loop is stabilised 1 = Black current loop is not stabilised

Reg 01 D2 HBC HELP ABOVE/BELOW

BCL WINDOW

Valid when VSD = 1 (no vertical deflection). Can be used together with WBC (Window Beam Current loop) for factory alignment of the Vg2. Reading HBC indicates which direction to turn the Vg2 potentiometer to bring the beam current in the window of 12 - 20 µA (see also WBC below).

Note that HBC switches from low to high at the moment the beam current is in the window of 12 - 20 µA (and does not toggle in the middle of the window!)

0 = below 12 µA 1 = above 12 µA

Reg 01 D3 WBC BCL WINDOW Valid when VSD = 1 (no vertical deflection). Can be used together with HBC (Helper Beam Current loop) for

factory alignment of the Vg2. Reading WBC indicates whether the beam current is in the window of 12 - 20 µA while the bit HBC

indicates whether the current is above or below the window (see also HBC above)

0 = outside window 1 = inside window (beam current 12 - 20 µA)

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 01 D4 IVW IN VERTICAL WINDOW Condition vertical divider window:

0 = No standard video signal detected 1 = Standard video signal detected, 522-528 or 622-628 lines/frame, vertical divider in narrow window or standard mode

Reg 01 D5 FSI FIELD SYNC INFORMATION Field frequency indication of the selected CVBS signal

0 = 50 Hz 1 = 60 Hz

Reg 01 D6 NDF NO VERTICAL DEFLECTION This bit is set to 1 when the vertical guard pulse at pin 50 (BLKIN / Vertical guard) is wrong.

0 = Vertical deflection OK (correct guard pulse present) 1 = Failure detected in the vertical output stage (incorrect guard pulse present)

Application Note

AN01045

Reg 01 D7 XPR X-RAY PROTECTION This bit is set to 1 when an overvoltage is detected (voltage on pin 36 EHT / XPR > 3.9 Volt). When XDT is

set to 0, the horizontal drive is stopped via slow stop including RGB drive for 1 mA discharge current measured via the black current input. The bit is latched when the voltage on pin 36 > 3.9 Volt and can only be set to zero when the status bytes are read after the voltage on pin 36 has dropped below 3.9 Volt. The microprocessor part should monitor XPR and when XPR = 1 the bit STB must be set to 0. When no problem seems present, the set can be restarted by setting STB = 1. Setting STB = 0 after XPR = 1 is essential because immediate writing STB = 1 will not release the horizontal drive.

0 = No over-voltage detected 1 = Over-voltage detected on EHT input pin 36

Reg 02 D0 FML FM PLL LOCK

0 = No lock 1 = Indicates that the FM PLL is in lock

Reg 02 D1 FMW FM PLL IN WINDOW

0= Indicates the PLL VCO carrier is tuned within the catching range 1= Out of window

A valid sound carrier is found when FML=1 and FMW=0. Note: For search tuning algorithms, the sound carrier detection have to take place in a certain order to

prevent that 4.43 MHz colour carrier can be detected as 4.5 sound carrier. Recommended sequence order is: 5.5 MHz, 6.0 MHz, 6.5 MHz, and 4.5 MHz.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Reg 02 D2, 3 AFA, AFB AFC OUTPUTS

AFA 0 = Outside window (see AFW bit)

1 = Inside window

AFB 0 = Below reference, increase tuner frequency

1 = Above reference, decrease tuner frequency

AFC output information is available for search tuning. An automatic AFC loop is achieved together with the microprocessor and tuner. Because of the alignment free IF, AFC alignment is not required, the PLL is calibrated fully automatically. The figure below gives the AFC bit status in relation to the incoming IFfrequency.

38.9MHz

above reference

outside window RF too high

IF too low

25kHz

100kHz

below reference

outside window RF too low

IF too high

Application Note

AN01045

AFB

reference

AFA

normal window

AFA

large window

300kHz

Figure 2: AFC output bits

AFC read-out:

- The applied IF-frequency is correct when in-window, AFA bit is "1" and AFB is (close to) altering.

- AFC information can be read-out continuously but is updated during the vertical retrace. Therefore a

minimal wait of 20ms is required between changing the tuner frequency and reading-out AFA/B.

- AFC information is only available and valid when LOCK=1. This is inherent to the alignment free

concept.

Note:

- -AFC is valid when LOCK=1. This however does not guarantee that a picture carrier is found. E.g. the

- PLL can also lock to a sound carrier. For this reason it’s advised to check also the sync lock bit SL.

- -AFC remains valid in full OSD mode when POC=1 (than SL=0 but that is a don’t care for AFC)

- -AFC remains valid in stand-by mode when STB=0 (than SL=0 but that is a don’t care for AFC) and is

useful for TV-VCR application.

- -AFA bit is forced to zero during automatic AFC calibration (takes place after signal loss). This prevents

“false” AFA=1 read outs and optimizes the search tuning.

AFC accuracy:

- High AFC resolution of 25kHz for both AFA and AFB (indicated by the gray area)

- The AFA window position has a fixed relation to AFB. This ensures the window width of 100 and 300kHz.

Search tuning:

- Have AFW=1 for large window. This allows larger frequency steps and faster search tuning.

- Wait for LOCK and (SL or IFI) =1 before reading AFC information.

- Increment RF frequency until AFA=1. Tune in small frequency steps until AFB just toggles.

- For non-search tuning (normal TV) operation it’s recommended to select the normal window, have

AFW=0.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Fine-tuning:

The digital AFC information provides an accurate AFC loop. Fine-tuning is possible in an open AFC loop. Especially with PLL-tuners it’s easy to add a frequency offset via the microprocessor while ignoring the AFC output bits.

Reg 02 D4 QSS QSS/FM VERSION This can be used to verify whether the device is a QSS or FM intercarrier type.

0 = FM intercarrier 1 = QSS

Reg 02 D7 SUP + 8 VOLT SUPPLY PRESENT Indicates whether the + 8 Volt supply is present.

When low power start-up is used with only 3.3 Volt supply present, the device will be first full operational when this bit reads 1 (and the + 8 Volt supply is present). When during normal operation the + 8 volt drops below the detection level (about 6.2 Volts, 0.2 Volts hysteresis) the horizontal drive is switched off. When the +8 Volt supply rises again above detection level (about 6.4 Volts), the horizontal drive is automatically switched on via slow start. In this way, the device recovers automatically when a short power dip on the +8 Volt is present. When the +8 Volt is derived from the EHT flyback transformer, a drop in the + 8 volt supply can disable the + 8 Volt supply because the horizontal drive is switched off. To restart the horizontal drive in this condition, first STB must be set to 0 and then to 1 again.

0 = no + 8 Volt supply present 1 = + 8 volt supply present

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6 APPLICATION INFORMATION

Microprocessor General In this chapter, especially the hardware design aspects of the Micro-Controller pins are covered. For the programming aspects please refer to the Micro-Controller SFR registers of the embedded Micro-Controller part as defined in the specification.

* I/O ports

Pin 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 62, 63, 64

The I/O pins of the µprocessor can be configured in many ways. All port functions can be individually programmed by use of the SFR registers. Each port pin can be individually programmed in four output configurations. About detail please refer Table 1 and Table 2.

Open drain

Application Note

AN01045

In this mode, the port can function as in- and output. It requires an external pull-up resistor. The maximum allowable supply voltage for this pull-up resistor is + 5 Volt. So in this mode, it is possible to interface a 5 Volt environment like I2C with 3.3 Volt supply of the MicroController part.

Push-Pull

The push-pull mode can be used for output only. As well sinking as sourcing is active, which leads to steep slopes. The levels are 0 and VddP, the supply voltage of the output pins on pin 61, usually 3.3 Volt.

Quasi-bidirectional

This mode is a combination of open drain and push-pull. Normally the port is configured as open drain and it needs a pull-up resistor to the same supply voltage as VddP (usual 3.3 Volt). Only during a low to high transition, the port is switched to push-pull operation for one clock cycle (166 ns) to speed up the rising edge. This is the default mode of all I/O pins after a reset.

Note: This mode cannot be used with pull-up resistors to + 5 Volt! High impedance

This mode can be used for input only operation of the port. Note: To minimise power consumption in stand-by, it is best to program all port pins in high impedance

mode when entering Stand-By mode.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Extra functions of port pins

A number of port pins have extra functionality. This extra functionality can be programmed via the SFR registers of the Micro-Controller. In the table below, the available extra functions are listed.

Application Note

AN01045

[ Table 1 ] TDA935XPS/6XPS/8XPS - SDIP64 Package

Port Pin 8mA

sink

current P1.3 1 Tim. 1 P1.6 2 SCL P1.7 3 SDA P2.0 4 x P3.0 5 x x P3.1 6 x x P3.2 7 x x P3.3 8 x x P0.5 10 x P0.6 11 x P1.0 62 Int. 1 P1.1 63 Tim. 0 P1.2 64 Int. 0

Below, a more detailed description of the extra functions is given.

- 8 mA sink current (Port 0.5, 0.6 / Pin 10, 11)

These pins have the same functionality as the general I/O pins (same 4 modes) but in addition, their current sink capacity is 8 mA in stead of 4 mA. These pins can be used for direct drive of LED’s.

I bus

PWM

14 bits

PWM 6 bits

ADC

8 bits

Int. Timer

external

input

C port (Port 1.6, 1.7 / Pin 2, 3)

- I

Two output pins can be programmed as SDA (pin 3, port 1.7) and SCL (pin 2, port 1.6). The I master. The pins can be connected via pull-up resistors to the standard 5 Volt supply, commonly used for

C provided the output is configured as open drain.

- 14 bits PWM (Port 2.0 / Pin 4), 6 bits PWM (Port 3.0..3.3 / Pin 5..8)

The Pulse Width Modulated outputs can be used to generate programmable DC voltage. This DC voltage can be used for e.g. DC volume control or as DC tuning voltage for a Voltage Synthesized Tuner. The output is a square wave with a fixed frequency and a programmable duty cycle. The duty cycle can be varied from 0 to 100 %. Transformation of the square wave to a DC voltage is achieved by applying an integrator network. In its simplest form this can be a series resistor with a capacitor to ground. Standard the output range of the PWM cannot exceed the supply voltage of VddP (3.3 Volt). When higher voltages are needed, the port can be switched to open drain mode with a pull-up resistor to +5 Volt. Finally it is possible to drive a transistor with in the collector a resistor to a higher supply voltage. Because the transistor inverts the square wave at the base, the duty cycle is reversed, which has to be taken into account in the software. Note that the stability of the DC voltage is pending on the stability of the supply voltage. It is best to have a high ohmic load connected to these DC voltages or at least a constant load.

The 14 bits PWM is suitable for Voltage Synthesised Tuning because of its resolution. The frequency is

23.44 kHz (repetition rate is 42.66 µs), in 16383 steps (14 bit) the average high time can be programmed

C is multi

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

from 0 to 100 %. (an interleaving technique is used to achieve this high resolution, so not all high times are equal).

The 6 bit PWM is suitable for general DC control like volume. The frequency is 46.88 kHz (repetition rate

21.33 µs), in 63 steps (6 bit) the high time can be programmed from 0 to 100 %.

- ADC input (Port 3.0..3.3 / Pin 5..8)

The Analogue to Digital Convertor uses successive approximation to determine the digital value of the offered DC signal at the input. The resolution is 8 bits over a voltage range of 0 to 3.3 Volts, which gives 3.3 / 256 = 13 mV per step. However, the port configuration is such, that the input range from VddP - 0.75 Volts to VddP cannot be used. This is related to the threshold voltage of a protection transistor, needed to have the pin tolerant for +5 Volt in open drain mode. So the practical input range is 0 to 2.55 volts (worst case 0 to 2.25 volts with 3.0 Volt supply) with digital output from 00 hex to C0 hex. The inputs can be used for scanning keyboards with resistor ladder network and to determine levels at the SCART status input.

- Interrupt 0, 1 (Port 1.2 / Pin 64, Port 1.0 / Pin 62)

Application Note

AN01045

The external interrupt pins can be activated by level or edge. When programmed for level, the interrupt is active low. When programmed for edge, interrupt 0 will only react on the negative edges of the signal while interrupt 1 will react on both positive and negative edges. The interrupt inputs can also be programmed as gating input to enable the timer/counter. When activated, a high level enables the timer/counter to count, a low level stops the counting. INT0 controls the gating of Timer/counter 0 and INT1 controls the gating of Timer/counter 1.

- Timer external input 0, 1 (Port 1.1 / pin 63, Port 1.3 / Pin 1)

When configured as timer, as input the X-tal oscillator frequency divided by 12 is used. For the specified 12Mhz X-tal this means an input clock of 1 MHz. When the internal timers are configured as counter, the counter content is increased on every negative edge of the signal of the external timer input on pin 63 or pin 1.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.1 MICROPROCESSOR

Pins 58, 59, 57 XTALIN/XTALOUT/OSCGND 12 MHz crystal oscillator, ground

The crystal oscillator which operates at 12MHz supplies reference signal to different internal circuit blocks one of them being the DCO (digital colour oscillator). The specified Cl of the external crystal is valid for both series or parallel resonance as indicated on next page; the TDA937X PS N2 crystal oscillator uses the third configuration.

(1) series resonance

(2) parallel resonance

Figure 3: Crystal configuration

Application Note

AN01045

2Cl 2Cl

(3) parallel resonance

The crystal is placed between pins 58 and 59 and the external capacitors Cx1, Cx2 are connected between pins 58, 59 and the oscillator ground at pin 57. It is very important to connect only these two capacitors to this ground pin and to leave the oscillator ground pin floating; therefore do not connect pin 57 to the ground plane.

Example:

Saronix crystal (part no. = 9922 520 00169) has specified Cl=20pF. With Ci=Co = 7pF in Philips demoboard then Cx1=Cx2=33pF in order to have colour symmetry. Also low profile / SMD Saronix Xtals are available for miniature, LCD application etc.

12MHz reference

Ci Co

276K

Cx1

Cx2

Figure 4: Basic crystal oscillator application

Depending upon PCB layout Ci, Co can be different; then Cx1, Cx2 has to be optimised to have a symmetric colour catching. Avoid large ground planes in the vicinity of the crystal. The values of Cx1=Cx2 in application should be between 12pF and 56pF, this places a restriction on the value of Cl which the crystal manufacturer specifies. For Ci=Co = 7pF then Cl is restricted between the values 13pF and 30pF approximately.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The crystal resistance should be less than 100E. The colour catching range is internally defined and is not dependent upon the motional capacitance as is the case with present analogue colour decoders. The frequency tolerance should be typical +/-30ppm; larger tolerance is allowed but this leads to more spread in colour assymmetry.

Pin 60 Reset Power On Reset (POR)

The reset pin is coupled to the internal reset circuitry as indicated in the microprocessor block diagram. A Power On Reset (POR) of the microprocessor occurs when VddA (3.3V at pin 54) dips below approximately 2.5V and in order to realise this there is a internal direct hardwire communication between both microprocessor and videoprocessor.

Also an external reset circuit in application can be implemented if necessary but is not required. An example of an external reset circuit is given in the application diagram. To prevent false I supply should be switched-off during reset. In this way, data corruption is prevented.

C messages to the non-volatile memory during rise or fall of the supply, also the memory

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.2 IF PART

Pin 23, 24 IFIN1, IFIN2 IF video input

The IF input frequency range is 32 - 60 MHz. The IF input impedance is 2 kΩ in parallel with 3 pF.

This matches the required load for commonly used SAW filters. DC coupling is allowed, therefore no series capacitors between SAW filter and IF input are necessary. For maximum IF performance (also for asymmetric tuners) keep the signal path from tuner to the IF input pins as short and symmetrical as possible.

The table below gives an example of possible SAW filters.

Type Mode Standard Remarks (sound shelf and IF frequency)

K2955M Intercarrier B/G, D/K -20dB, IF=38.9 K2960M Intercarrier B/G, D/K -14dB, IF=38.9 K2962M Intercarrier B/G -15dB, IF=38.9

K1984M Intercarrier B/G -14dB, IF=38.9 M1970M Intercarrier M/N -14dB, IF=45.75, for FCC EIA/IS-31 M1865D Intercarrier M/N K3953M K9456M

G3962M G9353M K9354M QSS – Sound B/G, I, D/K, L Broad single bandpass

Table 19: Siemens Matsushita SAW filter Combinations (all SIP5K packages)

QSS - Video QSS - Sound

QSS - Video QSS – Sound

B/G, D/K, L/L’ B/G, I, D/K/L or L’NICAM

B/G B/G-Nicam

-13dB, IF=45.75, for FCC EIA/IS-31, SIP5D Double Nyquist Slope (38.9 and 33.9) Pin 1= L’, pin 2= B/G, I, D/K, L This SAW filter needs ASYM tuner! IF=38.9 Single bandpass

Application Note

AN01045

Pin 27 AGCOUT Tuner AGC output

This output pin is used to control the tuner gain for varying RF signal conditions. The tuner AGC pin is an open collector output, which is acting as a variable current source to ground. An external pull-up resistor determines the slope of the tuner output voltage swing and therefore the maximum IF-input amplitude variation, called slip. Suggested pull-up resistor is 1k2Ω, with R = 180Ω in series with the pin. The exact resistor value depends on the tuner voltage control range. Once the tuner AGC is active the IF input signal level is constant within the slip. The level on which the tuner becomes active (Tuner take over point) can be adjusted by I²C bus. With a pull-up resistor of 1k2Ω the slip is about 4 dB.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Tilt

Application Note

AN01045

AGC voltage

100% white

one field

Figure 5: Positive modulated signal with top white reference pulse

The time constant of the tuner AGC can be defined separately from the gain (pull-up resistor) setting. Stability of the loop becomes difficult when the loop gain is too high (pull-up resistor >> 1k2Ω). Special attention on stability is required for reception of positive modulated signals (VITS line at 100% and video about 50%).

Notice that when the IF-part is muted via VSW = 1, than the tuner output pin is pulled to ground level for minimum tuner gain. After switching on again, the tuner AGC capacitor must re-charge (and also the tuner gain). The time constant is determined by the capacitor value and pull-up resistor value.

IF-AGC actions:

Optimal IF performance is achieved with gating signals derived from the horizontal oscillator. They become automatically active once the coincidence detector SL = 1. In external mode the top white AGC remains available only, because in external mode the sync part is locked to the AV signal.

Reference

pulse

Video output

signal

Input mode

Always available Activated when SL = 1

Internal (RF mode) Top white AGC Black clamp AGC AGC line gating External, Decoder mode Top white AGC - -

Table 20: Gating signals in the two input modes AGC speed

The AGC speed can be adjusted with AGC1, AGC0, see section I2C.

Pin 37 PLLIF PLL loopfilter

The standard loopfilter configuration is R = 390Ω and C = 100 nF in series to ground. The loopfilter bandwidth is 60 kHz and is chosen optimal for fast catching as well as sufficient video suppression to obtain optimal sound performance.

The loopfilter time constant can be changed by I description of the function, chapter picture improvement.

Note:

For special market areas with large phase modulation we recommend:

Keep FFI=0 (off) Change loopfilter R=390E -> 1k5 (2k2 maximum)

C=100 nF -> 47nF (33 nF minimum)

Drawback: higher loopfilter bandwidth is less optimal for sound performance (video -> sound)

Gating signals

C bus function FFI (Fast filter IF-PLL). See for detailed

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 38 IFVO / SVO IF video out / selected

video out

The level of the video output signal:

B/G

Video amplitude is typical 2.5 [Vpp]

top sync (fixed by AGC) 2 [V]

Selected CVBS out 2V [Vpp] (When SVO=1) Although the video output impedance is low it is recommended to avoid high frequency current in the output

due to for instance sound trap filters. This can be achieved by means of an emitter follower at the video output with a 1kΩ resistor in series with the base. This pin includes a double function. When SVO = 1 than the selected CVBS signal becomes available for a SCART monitor function. See table below. Some remarks as regards performance issues related to pin 38.

Beat of 2.9 MHz:

In some applications a 2.9 MHz beat becomes present at the video output pin. The mechanism is that the 3rd Xtal harmonic (3 x 12 MHz) is 36 MHz is injected to the IF input path. Demodulated at 38.9 MHz results in a beat of 2.9 MHz. Attention points to minimize this effect:

- Symmetrical path between tuner, SAW filter and IF input pins. This gives optimal common mode rejection.

- Avoid radiation of I/O ports into IF-input.

- Remove capacitor of decoupling digital supply 3.3V pin 15.

- Please see section “Oscillator, supply, decoupling, grounding and supply startup/shutdown”.

Application Note

AN01045

Cross talk INT->EXT aspects:

- Avoid PCB tracks with video signals being close to the AV input. (voltage cross talk)

- Avoid high video currents in supply lines and or ground close to IC.

- Decouple collector of emitter follower(s)

- Use minimal current in emitter follower(s)

At no antenna signal condition the video noise peak-peak level (approx. 4 Vpp) is higher than the normal video amplitude (2.5 Vpp). Depending upon application this might give extra cross talk and line jitter. This noise level can be reduced by means of I²C bus IFS = 1. This reduces the maximum IF-gain by 20 dB. In practice overall sensitivity reduction will only be 12 dB due to the combination of tuner and IF stage.

Switch-off IF part:

- Switch off the IF-part by means of I²C bus command VSW = 1.

In this condition the video output pin voltage is 0V and tuner AGC output is forced low for minimal tuner gain.

Note: after switching on again, the tuner AGC capacitor must charge again. The capacitor value and pull-up resistor defines the time constant. CVBS1 input pin 40 can be used as extra input pin. (This is only possible when VSW = 1 else cross links between IF and sync part will remain active)

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.3 FM SOUND

Pin 20, 32 AVL Automatic volume

leveling

The Automatic volume Leveling feature is available in specific IC versions and can be switched on/off via AVL bit (reg 2C D2).

• For 90ÛYHUVLRQVZLWKRXW(:GULYH7KH$9/FDSDFLWRUVKRXOGEHFRQQHFWHGWRSLQ20.

• For 110ÛYHUVLRQVZLWK(:SLQ32 can be selected to apply the AVL capacitor using CMB0, 1 bits (reg

22 D4, 3). Other features (2 used

SIF, Combfilter reference output) that make use of this pin can not be

Application Note

AN01045

7KHUHFRPPHQGHGFDSDFLWRUYDOXHLV

settling, AVL hold time (dynamic sound range) and harmonic distortion.

• A small AVL capacitor value gives fast volume settling but reduces the dynamic sound range and

performance on harmonic distortion for mainly low audio frequencies.

• A large AVL capacitor value gives maximal AVL performance but increases the volume settling time.

The active control range of the AVL pin is 1V for maximum gain and 5V for minimal gain. During channel switching it is recommended to enable sound mute (via SM0/1).

After releasing mute the AVL is set in maximum gain, this ensures a fast settling of the volume level. Noise peaks will not disturb the AVL function during channel switching.

The AVL circuit works properly for an AVL input signal range of approx. 100-1000 mV "boost range" and is 20 dB. Within this "boost range" any desired stabilised output level can be adjusted by means of the volume control. An external AVL capacitor acts as "memory" and integrates the audio peak signal. The charge (or attack) current is 1 mA, the discharge (or release) current is 200 nA. The time constant is defined by the AVL capacitor. The DC voltage (1-5V) across the AVL capacitor controls a gain stage that stabilises the audio output level.

Because the discharge current is very small, any leakage of the AVL pin to ground must be avoided. Therefore a capacitor of a decent quality should be use at the AVL pin.

Specifications:

Gain at maximum boost + 6 dB (relative to 500 mV Gain at minimum boost -14 dB (relative to 500 mV Control voltage at maximum boost 1 V Control voltage at minimum boost 5 V Charge (attack) current 1 mA Discharge (decay) current 200 nA Charge/discharge current ratio 5000

)WR )LWVRSWLPDOYDOXHLVDFRPSURPLVHEHWZHHQIDVWYROXPH

. This is called the

rms

in)

rms

in)

rms

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 31 SNDPLL Sound PLL Loop filter

The filter components mentioned below can be used for all sound standards for optimal sound performance. (Cs + R) // Cp

Application Note

AN01045

Bandwidth

[kHz] Cs R Cp Damping

3dB

150

1.2 nF

3.9 kΩ

330 pF 0.5

Table 21: Loopfilter component values Apply these components close to the pin to minimize external disturbances.

Pin 32 AVL/REFO/SNDIF AVL/Combfilter output/

SIF INPUT

This pin 32 has three functions that can be selected using the CMB0/1 and SIF bits. I. Automatic volume leveling (AVL) function II. 2

SIF input

III. Combfilter reference output carrier IV. Switching output.

I. AVL see pin 20. II. The 2

SIF input provides direct access to the FM demodulator input.

This option is available when CMB0/1 = 00 and SIF = 1. Set FMA/B for sound carrier frequency selection.

• Sensitivity of the 2

SIF input is 1 mV

• Input impedance is 50kΩ

• The pin voltage must be in between 0 - 4V maximum.

• This pin needs a DC path to ground, apply always 470Ω to 1kΩ at this pin when using this feature.

2nd SIF

270 470

100

CVBS

Pin 38

IFVO

SIF application

The 2

Figure 6: 2

SIF input is intended for special applications only, as e.g.:

- For fine tuning sound performance for very extreme market areas.

- The intercarrier signal from pin 38 can be used to apply to the external sound pass filter. For PAL

BG/DK applications these external filters can be placed in parallel.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

III. and IV.

Application Note

AN01045

The reference output signal is only available when CMB0, 1 = 01. For the other CMB0, 1 settings this pin is a switch output. See also I

Pin 35 AUDEXT External audio input

An external sound source can be fed into this pin via a coupling capacitor.

• Maximum input voltage is 2 V

• The input impedance is 25kΩ.

The coupling capacitor for a corner frequency for instance 10 Hz is:

& [

Pin 29 DECSDEM Sound decoupling

This pin requires a capacitor connected to ground. This pin serves as a low pass filter needed for the DC feedback loop.

The de-emphasis pin determines the low pass crossover frequency. This decoupling pin determines the high pass crossover frequency.

The pin output impedance is typical 500Ω so with the following formula you can calculate the capacitor value:

[+][NΩ  )

C chapter.

rms

) [

The following highpass crossover frequencies are valid:

FMA/FMB FM sound standard [MHz] Decoupling capacitor High pass frequency

01 4.5  ) 106 Hz 00/10/11 5.5/6.0/6.5  ) 53 Hz 01 4.5  ) 64 Hz 00/10/11 5.5/6.0/6.5  ) 32 Hz

Table 22: Sound decoupling capacitor value for different frequencies and standards The corner frequency for standard 4.5 MHz is two times bigger. This is due to the circuit design and is

depended of the setting of the AGN bit. The loop gain is twice as much when +6 dB amplifier is inserted for NTSC.

Note: Capacitor values larger than 32 uF lead to long settling times before FM sound is available. (>3-4s after 8V supply is applied).

[&[7KHVORSHLVG%RFWDYH

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 28 AUDEEM Audio de-emphasis I. De-emphasis time constant

The de-emphasis output pin requires a capacitor to ground that defines the de-emphasis time constant.

Example:

De-emphasis time constant is 54µs for a standard PAL signal. The pin output impedance is 15kΩ typical, the capacitor becomes C = 54µs/15kΩ= 3.6 nF -> 3.9 nF.

The corner frequency f = 2700 Hz, the slope is –6 dB / octave. The pin should not be loaded with high impedance as it effects the time constant.

For BTSC applications a capacitor of 33 pF is recommended. (flat freq. Response up to 100 kHz).

The corner frequency for standard 4.5 MHz is two times bigger. This is due to the circuit design and is related to the gain difference of the 0/ +6 dB switch in the de-emphasis signal path.

Application Note

AN01045

Sound output

[mV ]

Volume

+ 9 dB

1400

1000

500

0 dB

- 71 dB

100

0.3

0.14

0.1

10 100 1k

Figure 7: Frequency characteristic de-emphasis output

II. Audio output level

MAX sound volume

De emphasis level

- 6 dB/oc t

+ 6 dB/o ct

f 1 f 2

MIN sound volum e

=mute level

- 6 dB/oc t

10k

C=3n9

T=54µs

100k

C=33p for

C=33p for BTS C ste reo

BTS C ste reo

f [Hz ]

Video standard or function (Nominal frequency deviation)

Output level [mV (AGN = 0) nominal condition

Output level [mV

rms

(AGN = 1) +6 dB

PAL (50 kHz) 500 Not recommended NTSC (25 kHz) 250 500

Table 23: Nominal output levels de-emphasis pin

rms

]

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The signal must always be buffered to avoid influence of the de-emphasis time constant. To fulfill the SCART requirement (500 mV at 27 kHz FM swing) this signal must be amplified by 6 dB. Both requirements can be fulfilled at the same time when the buffer is configured as an amplifier.

III. Sound mute

The DC output level is 3.2V, also during mute. The setting of SM1, 0 = 10 is to mute this output pin.

In normal operation we recommend setting SM1, 0 = 01, because this setting limits spike noise in weak signal conditions. This due to the fact that in this case the acquisition help pulses of the narrow band PLL becomes active to prevent unlocking of the sound PLL.

Pin 44 AUDOUT Volume controlled

output

This output pin delivers the internal as well as external volume controlled audio signal. The nominal gain is +9 dB and –7 dB, which gives a total control range of 80 dB. The output signal range is 0.14 – 1400 mV The bandwidth is >100 kHz, the DC level is 3V and the output impedance is 500Ω. The output is automatically muted in standby mode (STB = 0).

Application Note

AN01045

rms

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.4 QSS SOUND

Pin 20 AVL, E W AVL/EW drive

The AVL feature is only available in QSS versions without EW. See also Chapter: Pinning configuration, Pin functions for various modes and the FM sound chapter.

Pin 28, 29 SIFIN1, SIFIN2 SIF input

The IF input frequency range is 32-60 MHz. The IF input impedance is 2kΩ in parallel with 3 pF.

This matches the required load for commonly used SAW filters. DC coupling is allowed, no series capacitors between SAW filter and IF input are necessary. For optimal IF-performance (even for asymmetric tuners) it is advised to:

- Make the signal path from tuner to the IF-input pins as short and symmetrical as possible.

- Make sure that the supply line is clean of the pre-amplifier used. Supply ripple will be AM demodulated.

- To prevent overloading these input pins, check:

Tuner AGC alignment Type of SAW filter

Application Note

AN01045

Using QSS, better sound performance can be achieved compared to intercarrier applications. This is mainly due to the extra selectivity of the SIF SAW filter and the lower soundcarrier suppression, see example below.

PC SC

-10 dB

-6dB

VIDEO

SOUND

K2960M

SAW

-6dB

VIDEO

K3953M

SAW

SOUND G9353M SAW

-14 dB

-0dB

-6dB

PC SC

-6dB

PC SC

-24 dB

PC/SC r a tio : 1 8d B

-10 dB

PC/SC r a tio : 4 d B

Figure 8: SAW filter losses

Conclusion, with QSS the soundcarrier level is 14 dB higher compared to intercarrier SAW filter with e.g. 14d B sound shelf.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 31 SIFAGC SIF AGC

The optimal AGC capacitor value is 2.2 µF and achieves an optimal compromise between AGC speed and AM frequency behavior. A smaller capacitor value for AM sound will increase the low corner frequency (the harmonic distortion will not be affected, since the AGC is an average detector).

The AGC time constant is automatically adapted for positive and negative modulation. For negative modulation the AGC time constant is 10 times faster. For maximum stability the AGC capacitor must have a short connection to ground.

Pin 32 REFO Combfilter output

This pin has multiple functions, which can be used in one application.

I. Combfilter reference output carrier II. Switching output.

I. and II.

Application Note

AN01045

The reference output signal is only available when CMB0, 1 = 01. For the other CMB0, 1 settings this pin is a switch output. See also I

Pin 35 QSSO/AUDEXT QSS output/External audio input I. QSS output

Provides both FM as AM modulated carriers. The signal level is controlled by the SIF AGC and kept constant at 100 mV buffer this pin, this prevent attenuation of the QSS signal. A high pass filter can be used to increase sound performance. Recommended component values are C = 330 pF and R = 1K.

II. External audio input

When CMB0, 1 = 00, this pin is an external audio input. The input level can be maximum 500 V modulation.

Pin 44 Controlled audio out

See FM chapter.

C chapter.

. This signal can be applied to an external (stereo) decoder. It is recommended to

rms

for 54%

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.5 THE NARROW BAND PLL

The new PLL concept used in the TDA937X n2 as in the previous series TDA935X/6X/8X both n1 as n2 is introduced to simplify the application for sound modulation and is designed to be used without external bandpass filter components. The TDA935X/6X/7X/8X n2 versions are also featured with an internal bandpass filter (Q=16) for selectivity. For extreme market conditions additional external filers can still be applied using the 2

The NBPLL (Narrow Band PLL) has a limited locking range centred on the sound carrier selected with I bits FMA, FMB. The NBPLL loop selectivity is determined by the external loopfilter component values, that also defines other parameters such as S/N ratio and THD. The chosen loopfilter component values are always a compromise between the mentioned parameters.

The status of the NBPLL is digitally controlled and secures a holding range of ±225 kHz, this can be enlarged to ±450 kHz for highly modulated carriers using FMWS. The in/out window status can be monitored via FMW output bit. When an out of window condition is detected the NBPLL generates acquisition pulses to speed up the locking process.

SIF input.

Application Note

AN01045

The locking status can be monitored via the FML output bit.

Sound performance of the narrowband PLL

See below the S/N characteristic graphs that show the sound performance of the narrowband PLL. As seen clearly in the first graph, the narrowband PLL is capable to meet at least 30 dB at PC/SC = 25 dB. The measurement is carried out in the demoboard application designed by SLE, under the following conditions:

- RF level 60 dBuV

- RF frequency 471.250 MHz

- Picture content: Colour bar

- PAL BG 10% rest-carrier

- 1 kHz tone 27 kHz deviation 0 dB reference

- SAW filter K2955M (-20 dB soundshelf)

- Selective S/N measurement between 22 Hz – 22 kHz

- Equipment: Rohde & Schwarz SFM, SAF, UPA

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Figure 9: Sound performance narrowband PLL

Limitations of the narrowband PLL

- Limitations to highly modulated soundcarrier When the average measured VCO frequency is more than the window borders, acquisition help is activated resulting in soundcrackling. Before this event, THD increases (the edges of the FM demodulated frequency spectrum are being cut away), see the picture below:

Cs=4n7F, Rs=3k9, Cp=820pF

THD [%]

+225kHz

Figure 10: Distortion versus increasing soundcarrier modulation

- Acquisition help pulses When the acquisition pulses are operating, the sound impression can be described as soundcrackling. Tiny pulses are added onto the loopfilter signal to obtain faster catch behaviour. Because of the significant amount of gain further up in the chain (> 50 dB), these small pulses transform to large spikes at the volume controlled output pin.

FMWS = 1

Frequency

Cs=1n2F, Rs=3k9, Cp=330pF

The volume level of these spikes can be decreased using the automute (SM1, 0 = 01) function. With FMWS = 1 (large window), less spikes are being generated.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.6 FILTERS, SWITCHES AND COLOUR DECODER

A complete multi-standard colour decoder is implemented whereby all world standards can be decoded. The following colour identification algorithm is implemented

Application Note

AN01045

IDN IDP PSNS Xtal

freq

0 0 x x kill kill kill 0 1 0/1 x Kill / PAL kill kill / PAL 1 1 0 x x NTSC NTSC kill 1 1 x ABC PAL NTSC PAL 2 1 1 x D NTSC NTSC PAL 2

Table 24: Colour identification algorithm internal implementation

In order to maintain correct colour identification (i.e. poor VCRs, reflections, etc.) the above algorithm is implemented where all possible combinations of IDN and IDP are covered. IDN and IDP are the internal identification signals from the NTSC and PAL identification circuits respectively. This information goes to the ASM (automatic system manager) and depending upon the CM3..0 settings the colour system is set. For multistandard and trinorma applications it is advised to use the automode (CM3..0 = 1000).

The colour killer sensitivity level for PAL can be increased for noisy signal conditions using PSNS reg 21D2.

0 = Normal PAL sensitivity, killing level typical 26dBuV 1 = Increased PAL sensitivity, killing level typical 21 dBuV

This feature is intended for the ASIAN countries.

Note 1: PAL ident when IDN low in automode/forced PAL is only possible when PSNS=1 Note 2: In automode: PAL ident when XTAL freq A,B,C detected, NTSC ident when XTAL freq D

(3.579545 MHz) detected. In this way misidentification of NTSC as PAL is avoided.

Auto mode Forced

NTSC

Forced

PAL

Notes

Pin 38 IFVO/SVO CVBS output

IFVO has a 2.2Vpp signal and after buffering, sound trap application and attenuation (for 1Vpp) it is supplied to the CVBS1 input (pin 40). CVBS1, CVBS or Y/C input selection is via INA, INB as indicated in table below.

INA INB Selected signal

0 0 CVBS1 (from front end, IF) 0 1 CVBS2 (from SCART) 1 1 Y/C (SVHS or cinch)

Table 25: Video input selection

CVBS or Y/C selection is independent of internal/external audio selection which uses the I For example this is useful for combfilter applications where Y/C can selected together with internal audio; also switching between two sound sources while receiving CVBS signal from IF (i.e. 2 here the 2

sound source is coupled to external audio after bandpass filtering in application.

C bit ADX

language selection),

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The basic application with combfilter is shown below; also refer to application example at end of report for application without combfilter. For black/white or SECAM transmissions (detected by the CD3..0 I transparent mode via OUTSEL by setting I For PAL/NTSC colour detection (via CD3..0 I by setting I

C bit CMB1 0 = 0 1

C bit CMB 1 0 = 1 0

C bits), the TDA9181 is set to combfilter mode via OUTSEL

The OUTSEL switching signal can also be assigned to a user-defined port of the TDA937X/ if an extra port is available; in this case the interface circuitry between REFO and OUTSEL is not necessary. The INPSEL, SYS1 and SYS2 switching signals can be assigned to user defined output ports of the TDA937X.

Sound

Buffer

Trap

1nF

Buffer

220nF

1nF

Y/CVBS

Chroma

14 Y

attn.

Fsc

CVBS1 (1Vpp)

10nF

TDA9181

combfilter

ext

C bits), the TDA9181 is set in

Application Note

AN01045

Y/CVBS

CVBS1

Y/CVBS

Chroma

select

INA INB

To internal

circuits

Chroma/CVBS

To internal circuits

Sandcastle/Clamppulse

INPSEL

From TDA937x

user defined ports

SYS1 SYS2

12K

OUTSEL

33p

100K

AVL/REFO/SNDIF 47K

CMB1 CMB0

Figure 11: Combfilter application

+ 4.5V

REFO from Filters/Switches (4.4 / 3.6 MHz)

SIF

TDA937x

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pins 40, 42 CVBS1, CVBS/Y CVBS inputs

CVBS1 and CVBS/Y are advised to be 1Vpp (inclusive sync. amplitude). The IF video output (pin 38, IFOUT/SVO) is attenuated and ac coupled to ensure a 1Vpp CVBS signal. The noise detector will becomes active for 100mVrms noise and for CVBS1 = 1Vpp this occurs at a S/N=20dB. The PHI1 loop switches to slow mode at a S/N=20dB to ensure stable sync performance for noisy transmissions (less line phase jitter). The CVBS1 and CVBS/Y source impedance’s should be low (100E typical) so as to have optimal sync separator sensitivity and therefore proper compressed sync performance All CVBS input clamps have a top sync clamp current of 100uA. The internal clamp principle is shown below.

Application Note

AN01045

100

-1

CVBS input TDA937X

220nF

3.4V

Figure 12: CVBS input clamping principle

The top sync of the CVBS is clamped to 3.3V by means of a 100uA current. During line scan (64us) the input capacitor is discharged with a fixed current of 4uA and for charge balance, the current during clamping must be [64 / 4] * 4uA = 64uA (sync pulse width = 4uS) During vertical equalisation, the charge balance is different and the clamping current becomes [64 / 60] * 4 = 4.26uA.

The value of coupling capacitor is a compromise between fast clamping action and minimum CVBS line sag and optimum vertical sync performance. A typical coupling capacitor of 220nF is advised. The minimum value is 47nF. For large source impedance in the CVBS application it is advised to use a buffer. CVBS1 (pin 40) can be used also as a CVBS external input; in this case the IF video must be switched off

C bus bit VSW.

via I

Pin 44 Chroma Chroma input

The supplied chroma input burst amplitude should be nominally 300mVpp (75% colour bar). The input is internally connected to 1.3V

via 82K.

The external AC coupling capacitor with 82K forms a high pass filter. The advised coupling capacitor is 1nF.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.7 HORIZONTAL AND VERTICAL SYNC GEOMETRY

Pin 16 PH2LF PHI-2 control loop

Loopfilter: The loopfilter is intended for stabilising the position of the picture horizontally on the picture tube. This filter is a first order filter. This pin requires a capacitor value between 1-10nF (C), the recommended value is

2.2nF. The corresponding loopgain is than reduced to 0dB for 3kHz. A value up to 10nF is allowed to make

the loop slower. To avoid disturbances in the loop, the capacitor should be connected to ground pin 18 as short as possible.

Loopgain: The static loopgain (K) is 150 us/us, this implies that phase variations (dt0) due to storage time variations

) are reduced by this factor of 150. This is valid only when a capacitor is connected to the PHI-2 pin. Any

(dt

resistor connected externally reduces the loopgain. For R=10MΩ -> K=75, and for R=1MΩ -> K=15. Shift control range:

Application Note

AN01045

The picture can be centred on screen by means of the horizontal shift (HS) via I²C bus. The range is +/-2 us. The delay between the positive going Hout (line transistor switches off then) and start burstkey pulse (ref PHI-2) must be typical XV6HHILJXUHEHORZ

CVBS

Hout

Sandcastle

≤ 17µ

Figure 13: PHI-2 timing signal

The horizontal shift range is chosen large enough to compensate for centring errors with a variety of picture tubes. Under normal conditions it is therefore possible, that active video can be shifted in the retrace period, (resulting in a folded picture at the side). (see figure 14 on the next page)

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

HS=31

foldover

HS=00

HS=63

Application Note

AN01045

foldover

Horizontal deflection current

scan

Figure 14: Horizontal shift

Dynamic phase compensation: The flyback pulse width may not vary on beam current variations because it can not be compensated by the PHI-2 loop. The phase shift error on screen will be half the flyback pulse width variation. If this demand can not be reached in the line output stage an external compensation circuit might help to overcome such phase variations. A current, related to the EHT voltage, can be fed back to the PHI-2 pin via a resistor, R.

+ 8V

Flash protection

+/- 6

stat

dyn

shift

Phi-2 filter

C 4n7

flybackflyback

EHT info voltage

Figure 15: PHI-2 pin application

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Two parameters are important:

Application Note

AN01045

- Static sensitivity: 0.33 ms/mA This static shift (I

- Dynamic sensitivity: 7.6 ms/V Dynamic phase compensation [ms] = 7.6 * I

) can be compensated with HS

stat

dyn

* t / C

In order to maintain sufficient loopgain (K) it is recommended to have R as high as possible, >1MΩ. The polarity of the voltage on the PHI-2 filter is chosen such, that normal used circuits to measure the EHT voltage decrease for the beamcurrent limiting function can directly be used. In other words, the EHT info voltage should drop when the EHT voltage drops.

Flash protection: A flash protection becomes active when this pin is forced > 6V. The horizontal drive is switched-off immediately. Once the voltage is < 6V the horizontal drive is switched-on again via the slow start procedure. To avoid reaction on glitches or spikes, the minimum time the voltage has to remain above 6 Volt is 1 µs before action is taken. To prevent switch-off from the horizontal drive by disturbance on pin 16 when this function is not used, the flash protection can be disabled by setting DFL = 1 A series resistor of 1kOhm is required for current limitation. See also XPR function for overvoltage protection.

PHI-2 switched off: The PHI-2 loop is switched off when the PHI-2 pin is forced externally to 1V. This is for analysis purpose only.

Pin 17 PH1LF PHI-1 control loop,

The function of PHI-1 control loop is to synchronise the internal reference with the incoming CVBS signal. The loopfilter connected to pin 17 is suitable for various signal conditions like strong/weak and VCR signal. This is achieved by switching the loopfilter time constant by changing the PHI-1 output current. Via I²C bus FOA/B, different time constants can be chosen, including an automatic mode that gives optimal performance under varying conditions.

Most commonly used settings for FOA/FOB are:

FOA/FOB PHI-1 time constant PHI-1 gating Suitable for:

0 0 Fast/slow 1 0 Fast/slow

(1)

, “auto” Yes, in slow only Off air reception + VCR via RF

(1)

Yes Off air reception only, high noise immunity (gating)

(2)

(compromise)

1 1 Fast no Special program number “0” for VCR via RF

External input, optimal for VCR

Table 26: PHI-1 time constant settings

(1) Fast or slow depends on whether the noise detector is activated (2) Not suitable for weak VCR signals via RF (this due to the active gating in slow mode)

Normal off-air reception conditions or cable:

− Use FOA/FOB = 0 0 for RF reception on all program numbers, VCR reception via RF possible on all channels

− Use FOA/FOB = 1 1 for external input (VCR, laser disc)

Difficult off-air reception conditions (weak signal and/or interference):

− Use FOA/FOB = 1 0 for RF reception on program numbers (optimal off-air reception due to gating)

− Use FOA/FOB = 1 1 for special program number (program 0) for VCR reception via RF

− Use FOA/FOB = 1 1 for external input (VCR, laser disc)

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

To avoid disturbances in the loop, the filter should be connected to the ground pin 18 as closely as possible. The recommended values for the loop filter are:

C = 4n7 (min 2.2 nF), R = 18 kOhm (max 27 kOhm), C = 1µF.

The PHI-1 loop can be switched off by the I²C bus function POC. When POC = 1, a valid incoming signal can only be detected reading IFI (SL is not available). IFI should be connected to the selected video source for this purpose. It is of course also possible to use an external ident circuit.

When VID = 0, IFI controls the PHI-1 time constant switching between normal (IFI = 1, valid signal detected), and very slow (IFI = 0, no valid signal detected). In this way, stable OSD is obtained when no signal is present. This mode is preferred during search tuning.

VCR performance (especially trick modes) must be checked in the fast PHI-1 mode; FOA/FOB = 1 1. VCR head jump tests (with 16 us phase jumps) must be tested with these jumps during vertical retrace and not during vertical scan. The sync processing includes special features as increased PHI-1 current during vertical retrace that ensures fast settling.

Note that in “auto” mode (FOA/FOB = 0 0) the VCR normal play mode with head jumps during vertical retrace is displayed correctly.

Application Note

AN01045

Pin 33 HOUT Horizontal drive

This open collector output is meant to drive the horizontal deflection stage. The output is active low, i.e. the line transistor should conduct during the low period of the output.

The different conditions of the horizontal drive output are:

- Soft start: - After power-on and all registers are loaded

- When switching-on from stand by using STB

- After release of flash protection on pin 16 (PHI-2)

- Running: - Normal condition, 45% off / 55% on duty cycle (45% high, 55% low)

- Soft stop: - When switching-off to stand by using STB

- After activation overvoltage protection XPR (pin 36)

- When the voltage at the 8 Volt supply pins 14 and 39 drops below 6.2 Volt

- Disabled: - When the 3.3 voltage drops below 2.65 Volt at supply pins 54, 56 and 61.

- Direct stop: - Forcing pin 16 (PHI-2) high activates the flash protection For optimal sync stability it is recommended to have the output current as small as possible. This can be

achieved by a small series resistor (100 Ohm) and a low output amplitude e.g. <3V. An extra emitter follower on the output can also be used.

Soft start:

In the N2, the start-up has been refined to further lower the stress and enable application of large picture tubes with DAF (Dynamic Astigmatism Focus).

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

100

Ton (%)

Soft

Application Note

AN01045

1045

TIME (MS)

57 73

50 100

150

Figure 16: H-out Start-up

The growth of the on-time of the H-out from 0 to 100 % is divided in three parts:

1. Extra slow increase from 0 to 12 %, lasting 57 msec.

2. The purpose is to further lower the stress of the rectifiers on the secondary side of the Fly Back Transformer (FBT). This is important for applications with high secondary power.

3. Normal increase from 12 to 75 % lasting 73 msec., comparable to N1

4. Very slow increase from 75 to 100% lasting 1045 msec.

5. This last part is related to enable the use of large picture tubes with DAF. These tubes tend to flash when the EHT rise from around 75% to 100% is too fast. It has been proven in High End concepts that by slowing down the EHT build-up in this region this flash problem does not occur.

The “off time” of the line output transistor is identical to the “off time” in normal operation. The starting frequency during switch on is therefore about 2 times higher than the normal value. The “on time” is slowly increased to the nominal value, the total start-up time becomes now 1175 msec.

Running: Normal condition, 45% off / 55% on duty cycle (45% high, 55% low)

Soft stop:

During soft stop, the sequence is reversed. T-off remains 28.8 µs (output level high) while the T-on (output level is low) decreases from 35.2 µs to 0 µs in 43 ms. The H-out frequency increases from 15.625 kHz to 35 kHz.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Switch off

55% 45%

Application Note

AN01045

28,8µs

1 mA picture tube discharge

during 38 ms

43 ms

28,8µs28,8µs

Figure 17: Soft stop timing

Because the RGB outputs are set high during soft stop, the EHT capacitor of the picture tube is discharged to below half the nominal EHT voltage. To archive this, the RGB amplifier must be able to return in a 1 mA “Iblack” measurement current. For example the Philips TDA6107 RGB amplifier can handle this function. Note: The voltages, derived from the FBT by flyback rectification, also drop to half the nominal value. So choose scan rectification for supply voltages, which need to be kept nominal as long as possible during switch-off (e.g. vertical deflection).

The internal I device. So only supplying 3.3 Volt, the I

C registers and the H-out circuitry are fully functional when only 3.3 Volt is supplied to the

C registers of the video processor can be written and the H-out can be switched on. From stand-by, only 3.3 Volt is needed to switch-on the H-drive pulses. This makes it possible to switch the power supply from stand-by mode to normal mode. It also enables to supply the 8 Volts of the device from a scan rectified winding of the FBT. Note: When using 3.3 Volt supply only during start-up, the external pull-up at pin 33 (connected after the 100 Ω series resistor) should be connected also to the 3.3 Volt. In the design of the driver stage, this low voltage should be taken into account. See for soft stop, when the voltage at the 8 Volt supply pins 14 and 39 drops under the 6.2 Volt, the description below at: “8 volt can be monitored”.

The TDA937X has three supply pins for 3.3 volts. The functions are:

- Pin 54: Analogue supply (Oscillator, ADC, digital logic TV processor)

- Pin 56: Digital supply to µ-processor core

- Pin 61: Supply to all output ports of the µ-processor

When the 3.3 Volt supply voltage drops shortly (spike) below 2.65 Volts, the POR bit is set to 1. The POR bit is latched, so the next status read will always return POR = 1, irrespective the duration of the power dip. At the same moment, the H-out is immediately stopped. (To start-up again, the µprocessor has to read the status bytes until POR = 0. Then all I

C registers have to be written (preferably setting STB = 0), because

they can be corrupted. Then the set can be started up again writing STB = 1) The TDA937X has also two supply pins for 8 volts. The functions are:

- Pin 14: Second supply TV processor

- Pin 39: Main supply TV processor

The +8 Volt can be monitored by the SUP bit, SUP becomes 1 when the supply voltage rises above 6.4 Volt and becomes 0 when the supply voltage drops below 6.2 Volt. Below 6.2 Volt H-out is stopped and the RGB outputs are blanked (remain below 2.5 volts).

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 34 FBISO Sandcastle output/flyback input

Pin 34 is a combined input/output pin. The pin provides a three level sandcastle pulse (see figure on next page). In this signal both burstkey pulse and vertical blanking pulse are always available, the line blanking pulse is only present when the external flyback pulse is fed to this pin. The line flyback pulse, fed to this pin, is used for two functions:

- Input signal for the PHI-2 loop.

- RGB line blanking. (Without flyback pulse blanking occurs only during the burstkey pulse) Because of the combined input/output function, the connected circuit should be carefully designed for optimal performance:

Flyback pulse

The selection of the flyback pulse is important. Please note that the flyback pulse width may not vary on beam current variations because they can not be compensated by the PHI-2 loop. See further description of pin 16. On the next page a suitable application is given for the flyback pulse generation.

Application Note

AN01045

line

transistor

main

flyback

BV2

tuning

flyback

4K7

4n7

150V

To other applications (options)

speedup

8V2

27K

buffer

flyback input/

parasitic

sandcastle outp

Figure 18: Flyback input circuit

A capacitive divider in parallel to the line transistor is used to derive a flyback pulse with a height of about 150 Volts peak. In this way we ensure steep edges for optimal jitter performance and optimal blanking width for the RGB outputs. This pulse is limited to 8.2 Volts (V

) via a resistor of 4.7 kOhm and a zenerdiode of 8.2 Volt to the ground

peak

of the TDA937X. In the layout, care should be taken that the 30 mA peak current through the diode does not disturb the IC application (EMC). The input current on pin 36 during flyback must be between 100 and 300 µA. The internal clamping level V Volts, the series resistor R

to pin 34 should be between 52 kOhm and 17 kOhm. For optimal reserve, 200

of pin 34 during flyback is 3 Volts. With a limited flyback pulse of 8.2

clamp

µA is recommended, which leads to a value of 27 kOhm.

5.3V

2.7V

Vpeak

Limited flyback pulse

Scan

Clamped f lyback

RGB bl anki ng

Vertical ret race

V blanki ng

3V Clamping level

Sandcastle at pin

rise

Figure 19: Sandcastle pulse

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The slicing level for horizontal blanking of the RGB outputs lies about 300 mV lower than the clamping level of 3 Volts. Care should be taken that at the slicing level the steep edges of the clamped flyback pulse are not degraded by parasitic capacitance C picture improvement TDA 9178) and the layout. Measured values in applications of this parasitic capacitance range from 20 pF to 60 pF. With 27 kOhm in series, this leads to an extra delay of 500 nS to 1000 nS before RGB blanking starts. Placing a speed-up capacitor Cspeedup in parallel with Rs can compensate the influence of this parasitic capacitance. The correct value is:

of pin 34 itself, devices connected to the sandcastle (e.g.

parasitic

Application Note

AN01045

speedup

= C

C The value of C

parasitic

* V

clamp

/ (V

peak

- V

clamp

)

can be determined by measuring the rise time t

of the sandcastle front porch on pin

rise

34.

= - t

total

/ { Rs * ln (1 - V

rise

clamp

/ V

peak

)} with C

total

= C

parasitic

+ C

measuring probe

An advantage of the high slicing level for horizontal blanking is that the steepness of the trailing edge of the sandcastle pulse is not critical.

An series resistor of 270 Ohm at pin 34 improves the EMC behaviour and should be placed as close to the pin as possible.

Loading the sandcastle output If long tracks are connected to the sandcastle output, we advise to use a buffer (see Figure on previous page).

Philips Semiconductors Version 1.0

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6.8 GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION

Pin 20 AVL, EWD EW drive, Automatic Volume Levelling The AVL is available in several IC versions and can be switched on/off via the AVL bit.

For 90 degrees versions without E/W drive, the AVL capacitor should be connected to pin 20. For 110 degrees versions with E/W, pin 32 can be selected using CMB0, CMB1 to apply the AVL capacitor.

For the AVL function see chapter SOUND. The EW drive is a current output. The output is single-ended and is fed directly to the EW-input pin 5 of the

TDA8358J. The figure below gives the EW output configuration.

Application Note

AN01045

SUP

600E

Pin20

EW =

VREF

0-1200uA

1-5V

sup

Horizontal Deflection

Modulator

= U

scan

Figure 20: EW output configuration

The DC voltage on pin 20 is determined by the East-West driver stage input and may range from 1 to 5 Volts. To prevent distortion, the voltage must always be > 1 Volt. For the TDA 8358J, the reference voltage level (V

) has a value of 2.5 Volts and is internally set by the

ref

East-West stage. It is recommended to minimise the EW-output current by means of the EW-width setting.

A minimum EW-current implies a minimum EW-voltage in the line deflection, Uew. Doing so results in a minimum power supply voltage; Ub = Uscan + Uew

The minimum EW-current is 0mA and can not be negative. This implies that for the EW-current a margin has to be taken into account for negative current corrections as EHT tracking and trapezium. This margin can be made with the EW-width setting.

Note that for 16:9 displays another optimum is necessary to enable zoom functionality. For a correct EHT tracking (compensation of picture height and width for variation of the EHT voltage due to

beam current loading), the tracking must be the same on vertical and EW. The tracking on vertical is +/-5% (internally fixed) and should also be +/-5% on EW. This EW tracking is determined by Rew. When we simplify the deflection to a linear system, with picture width direct proportional to the voltage over the deflection yoke, following formulas give the relations.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Uscan = Usup - Uew (Uew = Iew * Rew + VDC pin 15)

δUscan = - δUew = - δIew * Rew δUscan -δIew

 = Rew * 

(both sides divided by Uscan)

Uscan Uscan

According the device specification:

dIew = 100µA for dUscan / Uscan = 5% Rew

can be determined now by:

Uscan

Rew = 5% *  = 500 * Uscan 100µA

Rew = 500 Ω/V * Uscan (

Example: for a horizontal scan: Uscan = 150V -> Rew = 500 * 150 = 75kΩ. If Rew < 75kΩ this will decrease the gain and results in less EW correction w.r.t. vertical

If Rew > 75kΩ this will increase the gain and results in more EW correction w.r.t. vertical In practice the picture width will increase more than the increase of the voltage over the deflection yoke, due

to the applied S correction. This gain factor can vary from 1.3 to almost 2, pending on the flatness of the tube face and the required S correction. Therefore Rew has to be tuned to the specific application.

It is also possible to use an external circuit to correct the horizontal width for EHT changes. In this case, HCO should be set to 0. Note that the EHT tracking for horizontal non linear corrections (parabola, corner parabola, trapezium) always remains active. Only the EHT tracking for picture width is switched off.

See further the section regarding EW geometry adjustments.

Pin 22,21 VRDA, VRDB Vertical drive

The vertical drive has a current output. The output is balanced which ensures a good common mode behaviour with temperature and makes the output signal less sensitive for disturbances. The figure on the next page gives the vertical drive signals with the vertical output stage TDA8358J.

for same tracking on vertical and EW)

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

drive-

100

TDA8358J

INA

Application Note

AN01045

drive+

1nF

100

CV1

2.2k

CV2

2.2k

1nF

INB

Figure 21: Vertical drive application

2 (p-p)

2 (bias)

637.5

400 uA

165.2

1 (p-p)

1 (bias)

637.5

400 uA

162.5

Figure 22: Vertical Driver Current

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

i (dif)(p-p)

drive+

i (dif)(bias)

i (dif)(p-p)

drive-

i (dif)(bias)

Figure 23: Vertical drive signals with TDA8358J

The output voltage is determined by the input resistor R

out

= i

out pp

* R

= 475µApp * 2.2kΩ = 1.045V

CV1,2

and the output current.

CV1,2

1403 mV

880 mV

358 mV

1403 mV

880 mV

358 mV

Important for the TDA937X is that the voltage at the driver pins does not exceed 4V. The value for R

and the input capacitors of 1nF must be connected closely to pin 1 and 2 of the TDA8357J /

CV1,2

= 2kΩ to 2.2kΩ and is determined by the TDA8357J / TDA8358J / TDA8359J.

CV1,2

TDA8358J / TDA8359J for optimal EMC behaviour. The series resistors of 100Ω and the HF blocking capacitors of 1nF also improve the EMC behaviour.

Pin 26 VSC Vertical sawtooth capacitor

This pin requires a capacitor to ground of 100nF +/- 5%. Short connection to the ground pin 18 of the TDA937X is required. Important: For this capacitor, a type with good temperature behaviour, long term stability and low leakage must be chosen. Change of the capacitance value due to temperature and/or ageing leads to a proportional change in vertical amplitude. Tolerance of the external capacitor can be compensated by means of the vertical slope adjustment of I²C bus function VS. The charge current can be fine tuned with +/- 20%.

The optimal sawtooth amplitude is 3.0 V and is determined by the external capacitor and charge current. For R = 39kΩ at pin 20, the vertical slope VS = 1F and field frequency = 50Hz, the charge current is 16 µA. For 60Hz the charge current is increased by 19%. The sawtooth bottom-level is 2.3V.

The vertical retrace time is determined by the discharge current of 1mA and lasts about 5 horizontal lines.

Spurious signals on the sawtooth:

Because the sawtooth signal at this pin represents the deflection current, every disturbance influences the deflection. Notice that 3.0 V

ramp amplitude corresponds to approx. 300 lines. Thus dV

=10mV/line in

ramp

one field. Due to interlacing this figure becomes 5mV/line over 2 fields. Or, 1mV disturbance on the sawtooth means 1/5 = 20% interlace error. Thus, for proper interlacing special attention is required on grounding from components, related to the vertical sawtooth and the connection to the inputs from the vertical deflection driver.

Philips Semiconductors Version 1.0

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Pin 25 IREF Reference current

This pin requires a resistor to ground. The optimal reference current is 100µA, which is determined by this resistor. The voltage on this pin is 3.9 Volts, which leads to the recommended resistor value of 3.9V / 100µA = 39kΩ +/- 2%. A short connection of this resistor to the ground pin 18 of the IC is recommended for EMC behaviour. Important: Like the vertical sawtooth capacitor, also for this resistor a type with good temperature behaviour and long term stability must be chosen. Change of the resistance value due to temperature and/or ageing leads to a proportional change in vertical amplitude and E/W geometry settings.

The 100µA reference current should not be changed because the geometry processor is optimised for this current. Furthermore the output current of vertical drive and EW are proportional to this current.

Pin 36 EHTO EHT tracking, Overvoltage protection

The input range for EHT tracking is 1.2 - 2.8V, for a compensation of +/-5% on vertical and/or EW. The tracking on EW can be switched on/off by HCO, see paragraph above. The nominal voltage of pin 36 for no compensation is 2V.

The EHT feedback signal must be filtered in order to prevent disturbances in vertical and/or EW deflection. A compromise has to be determined for tracking speed on normal EHT variation and ripple immunity. The overvoltage protection is activated when the voltage on pin 36 exceeds 3.9V typical. To prevent false triggering by glitches or spikes, the voltage must at least remain 1 µs above 3.9 Volt to activate the function. The result is: XPR is set to 1 (and latched) and can be read by the µprocessor

Application Note

AN01045

The following procedure is executed:

- The vertical deflection is set to the top of the screen (2 ms) When OSO = 0, the vertical scan will continue from the top of the screen When OSO = 1, the vertical drive will remain at the top of the screen

- The horizontal output is disabled after slow stop (43 ms)

- At the same time the RGB drive discharges the picture tube with 1 mA (38 ms)

- The device is set in stand-by mode. To restart the H-out, write first STB = 0 and then STB = 1.

This function is normally used in USA to switch-off the set when an external detection circuit measures a too high EHT level. It is also a safe way to switch-off the set when fault conditions are detected. The function can also be used to switch-off the set using an early warning detector when the supply voltage starts dropping due to switch-off using the mains switch. In that case, care must be taken that the 3.3 Volt supply and the 8 Volt supply remain long enough above reset level (2.65 Volt and 6.2 Volt respectively) to complete the switch-off procedure (45 ms). When the vertical deflection has to be kept at the top of the screen (OSO = 1) also the vertical deflection supply should remain high enough. When the function is not used, the switch-off procedure can be disabled by setting XDT = 1. Under this condition, XPR is still set so the µprocessor part can take the appropriate action when needed.

The 16:9/ 4:3 zoom function

Special linear zoom facilities on both Vertical and East-West gives the possibility to adapt the picture size for both 16:9 and 4:3 screens, see figure on next page. When zoom is used, the geometry remains correct in both vertical and horizontal direction. By programming the vertical slope, VS, subtitles at the bottom part of the picture can be made visible while the picture position at the top of the screen remains fixed (subtitle mode).

Philips Semiconductors Version 1.0

Shift up/down, V-size co nstant

Move up bottom, top re mains

TDA937X PS N2 TV-processor + µP + CC

Scale factor for H or V Vert. adjust with VX (1% /step) Hor. Adjust with EW (0.55% / step)

133% (4/3) 58 Preset + 18 100% (1) 25 Preset 75% (3/4) 0 Preset - 14

Table 27: H/V settings for aspect ratio’s 16:9 and 4:3

Application Note

AN01045

pictur e 16:9

picture 4:3

subtitle

V : 75%

H : 133%

H : 133% V : 133%

Zoom compress

Zoom expand

subtitle

Zoom expand

Vertical scroll

Vscroll

Shift up/down, V-size co nstant

Vslope

Subtitle mode

picture 16:9

subtitle

Subtitle

Vertical scroll

subtitle mode

H : 133% V : 133%

Zoom expand

subtitle

Move up bottom, top re mains

Vscroll

Vslope

Figure 24: Expand and compress mode behaviour

subtitle

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.9 YUV / RGB PROCESSING AND CONTROL

Pin 45 INSSW2 Insertion input

Application Note

AN01045

The voltage on pin 45 and the I

C bit IE2 determine whether YUV

The following tables indicate the selection process.

C bit YUV=0

BLKIN pin 45 I²C function Selected sources: BLKIN< 0.4V IE2= * Internal YUV signals

0.9V<BLKIN< 3V IE2 = 0 Internal YUV signals

0.9V<BLKIN<3V IE2 = 1 R2;G2;B2 signals

Table 28

C bit YUV=1

BLKIN pin 45 I²C function Selected sources: BLKIN < 0.4V IE2= * Internal YUV signals

0.9V<BLKIN< 3V IE2 = 0 Internal YUV signals

0.9V<BLKIN<3V IE2 = 1 external YUV signals

Table 29

The YUV

signals are always selected whenever V

INT

PIN45

bit IE2. RGB2 / YPbPr / YUV signals are selected when V

> 0.9V with either full or fast insertion being possible.

PIN45

or RGB2 / YPbPr / YUV is selected.

INT

< 0.4V and is independent of the status of the I2C

Full insertion uses the IN2 status to set the IE2 bit; since IN2 status is updated every field blanking period during the red measuring line period. Full insertion then occurs in the following field. Fast insertion can be used for OSD applications (note IE2 = 1); also OSD can be displayed in mixed or full mode (mixed mode, then OSD information also present at insertion pin; for full mode, then DC voltage >

0.9V on insertion pin). Here the OSD is immediately displayed and the IN2 status bit is not of importance. The insertion pin should be driven from a source impedance which is < 560E A resistance can be put continuously on pin 45 to ground (100K to ground); pin 45 will rise above 0.9V;

using only the IE2 I

C busbit then it is possible is used to toggle between YUV

and RGB2/YPbPr mode

INT

via software.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pins 46, 47, 48 RGB2 / YPbPr / YUV inputs

Application Note

AN01045

External selection of the RGB2 / YPbPr / YUV inputs is done via I following table on the next page.

YUV1 YUV0 MODE

0 0 RGB2 input selected 0 1 Spare 1 0 YUV input selected 1 1 YPbPr input selected

Table 30: YUV mode settings For RGB2 selection, the nominal input RGB amplitudes is 700mV, for synchronisation a signal must be

connected to the relevant CVBS/Y input and I For YUV selection the nominal input signals for a colour bar with 100% saturation

Y = 1.4 Vpp (1 V U = -(B-Y) = 1.78 Vpp V = -(R-Y) = 1.4 Vpp

For YPbPr selection the nominal input signals for a colour bar with 100% saturation

Y = 1.0 Vpp Pb = = 0.7 Vpp Pr = = 0.7 Vpp

C bit SOY = 0

C bits YUV1, YUV0 according to the

black-white

)

The external RGB2 / YPbPr / YUV signals must be AC coupled. The RGB2 / YPbPr / YUV signals are clamped to approximately 2V during burstkey period. The coupling capacitors are a compromise between fast clamping minimum line sag and capacitors of 10nF or greater can be used. The source impedance of the RGB2 / YPbPr / YUV signals should be minimised for correct clamping operation. For the RGB2 / YPbPr / YUV signals then saturation control acts on the UV signals and black stretch, white stretch and transfer ratio features act on the Y signal. It is advised to minimise the track length to the RGB2 / YPbPr / YUV input pins. Adequate ground shielding of the RGB2 / YPbPr / YUV signal tracks is advised for good interference immunity. For YPbPr / YUV modes, the Y signal at pin 47 is internally coupled to the sync circuits and microprocessor

when I

C bit SOY = 1

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 49 BCL Beam Current Limiting

For protection of both CRT and LOT against large beam currents, then the average beam current is monitored as shown in circuit below.

Application Note

AN01045

EHT tracking for horizontal and verti ca l (2V-0.8V)

LOT

I-Beam

1-1.5mA

10K

EHT

0.5-1nF

47nF

6K8

+8V

120K

220K

2n2

27K

100K

220

+8V

control current

Imax=4mA

3.3V

PWL

3.9V

overvoltage

protection(XPR)

Contrast

Bright

Figure 25: Basic BCL application

The EHT impedance of 1M and CRT tube 0.5nF is matched with 6K8 and 47nF on the overwind of the LOT in application so as to have a similar waveform of the EHT information to allow proper BCL action. The steepness of the waveform on the 47nF can be increased by choosing a higher voltage source than 8V and larger resistance than 6K8 (note I

flows through 6K8 to CRT capacitor).

BEAM

High frequency ringing can be filtered to ground via the 47nF capacitor. The transistor integrator gives fast attack and slow decay times for average beam currents between 1mA to

1.5mA. Furthermore the transistor allows a simpler application with the EHT compensation to pin 36. The average beam current in the CRT is thus controlled by the external changing voltage on the 3.3uF capacitor (at pin 49) which originates in the overwind of the LOT; the external voltage on pin 49 first acts on the contrast and then eventually on the brightness.

The peak white limiting control is implemented internally and the maximum PWL discharge current that can flow internally is 4mA; the PWL current discharges the external 3u3 capacitor at pin 49 in order to reduce contrast/brightness dependent upon the input CVBS peak signal. The internal charge current at the pin is approximately 30uA.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

The detection level of the PWL is on the Y signal and begins at a level of Y= 0.7V contrast ( note that Y = 1V

BLACK-WHITE

also equivalent to 1Vpp or 0.7V

BLACK-WHITE

CVBS input signal).

BLACK-WHITE

for maximum

When contrast is decreased for example by 6 dB, the operation level of the PWL will also begin to operate for 6dB extra input Y signal. To prevent the PWL acting on short video input peaks (e.g. subtitling) or high frequency video, the PWL only operates when the duration of the peak exceeds 2 µs. The soft clipper takes care of the short peaks/high frequency input, while the PWL acts on the input video peaks which have longer duration. The soft Clipper operation and PWL detection occurs simultaneously. The PWL / soft Clipper characteristic curve is indicated below.

4.0

3.0

RGBout

(Vb-w)

Soft

2.0

clipper

1.0

60 80

08Hex

PWL setting

100

YIN(IRE)

120 130

Figure 26: PWL / Soft clipper characteristic

BCL limiting of the OSD signals internally coupled from the microprocessor to the videoprocessor is present.

Finally it is advised to have a short return loop to ground for the external BCL capacitor because of the high input impedance of the pin to prevent interference or coupling from other signals and for PWL current of 4mA. A capacitor value of > 3.3uF is recommended.

EHT compensation:

The DC information at the bottom of the EHT winding contains information about the EHT voltage. When the EHT voltage decreases, due to high beam currents, picture width and height increases. With lower EHT accelerator voltage, electrons travel longer in the deflection fields. This involves more deflection. It can be compensated dynamically via the picture width (EW for 110

tubes) and vertical drive

(bit HCO=1).

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The EHT information is fed via a filter to the UOC EHT-tracking pin 36. Internally this signal modulates the current of the E/W output and of the vertical drive outputs. The time constant of the filter determines the dynamic behaviour of the EW compensation. For a correct compensation, the tracking in horizontal (EW) and vertical direction should be the same. The tracking sensitivity for vertical is set internally in the UOC to

6.25 be made the same. For each deflection system the EHT tracking has to be carefully sorted out by trial, because it depends on the used EHT transformer and picture tube capacitance. For 90 for the deflection with the EHT information.

Pin 50 BLKIN Black Current input

This pin has functions for beam current measurement and control and vertical guard detection and blanking.

It receives beam current information from the CRT and controls it to 8uA and 40uA on alternate fields for the 2 point loop during the measurement. It is important to limit the current into the pin outside the measurement times to less than 250uA; this can be achieved by introducing a series resistance and clamping zener at the CRT PCB. Since the black current is high ohmic, some filtering can be added by having a capacitor close to the pin (<1nF).

input voltage at the EHT tracking pin 36. For 110o tubes the horizontal tracking sensitivity should

Volt

tubes the horizontal increase of deflection can be compensated by modulating the supply voltage

Vertical Guard input

Application Note

AN01045

The amount of filtering should not interfere with the measuring times (50% => 75% of measurement lines).The input signal for vertical guard should be less than 900usec wide for both 50Hz and 60Hz systems in order not to interfere with the measurement pulses.

The position of the measurement pulses are:

50Hz lines 17 - 20 (odd field) and lines 329-332 (even field) are visible 60Hz lines 17 - 20 (odd field) and lines 279-282 (even field) are visible

A pulse amplitude of >3.75V is required since the detection level is typical 3.45V. Since capacitance on pin is usually present for extra filtering, then the source impedance of the vertical guard pulse must be low in order to prevent excessive integration, especially on the falling edge. If no pulse is detected and the pulse is too wide (>900usecs) then the information is coupled through to the RGB blanking via the I2C busbit EVG.

A basic application of the pin is shown below including application with the CRT and vertical guard pulse.

Vertical guard voltage pulse

BLKIN

I-beam current

from CRT

Figure 27: Black current input basic application with vertical guard

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pins 51, 52, 53 RGB outputs

The RGB outputs drive the video output stages from pins 51, 52 and 53 respectively. For nominal input signals (i.e. CVBS/S-VHS, -(B-Y)/-(R-Y), OSD inputs) and for nominal control settings, the RGB output signal amplitudes are typically 2V BLACK-WHITE.

The DC level of the complete RGB signals, at RGB outputs, can be varied by varying VG2. The DC gain of the video output amplifiers should be then chosen so that the DC level at RGB outputs during measurement is approximately 2.5V when the VG2 DC control setting and cathode DC voltage are in their nominal operating region. Over the complete range of VG2 the cathode voltage should be above the cut-off of the CRT in order to avoid extra leakage during leakage measurement.

G2 MIN

G2 NOM

Application Note

AN01045

DC level at R

output

3.5 V

2.5 V

1.5 V

G2 MAX

0 V

Figure 28: RGB measuring pulses

It is advised to minimise the capacitive load of the output pins, therefore resistors (100Ω) are recommended in series with the RGB outputs (pin 51,52 and 53.) The output impedance of the RGB outputs is typically 330 ohms per channel with a maximum output current of typical 5mA ( peak white). In the RGB processing, the RGB signals are controlled on

- contrast,

- brightness

- whitepoint adjustment (separate RGB amplitude adjustment per channel)

- cathode drive level (simultaneous RGB amplitude adjustment)

Via the I²C bus commands (CONTRAST, BRIGHTNESS, WHITE-POINT RGB) these functions can be controlled. The contrast can be changed over a 18dB gain range by means of the I²C bus command (CONTRAST: 00 -

-> 63). Nominal contrast setting is realised with an I²C bus setting CONTRAST = 32. The brightness can be changed , over a of DC-level of ± 0.7V at the RGB

(w.r.t to nominal). by means

OUTPUT

of the I²C bus command (BRIGHTNESS: 00 -> 63). The white-point adjustment can be done separately for high- and low light.

White-point adjustment for high-light, a +/-3dB gain per channel (w.r.t to nominal RGB

OUTPUT

black/white amplitude) is possible via the I²C bus commands (WHITE POINT RGB: 00 -> 63). Nominal high-light adjustment settings are realised with I²C bus settings WHITE POINT RGB = 32. White-point adjustment for low-light, is possible for the red and green channels. The black levels can be changed by +/-160mV (w.r.t to nominal RG

black level) via the I²C bus commands (BLOR/BLOG: 00

OUTPUT

-> 63). Nominal low-light adjustment settings are realised with I²C bus settings BLOR/BLOG = 32.

Philips Semiconductors Version 1.0

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RGB output stages

Looking at the RGB output signals in the figure below several DC-levels can be seen. The DC-levels of the H- and V-blanking are 0.5V below nominal black level of the video signal. At the end of the vertical blanking (line 17,18,19,20) the measuring pulses for Continuous Cathode Calibration (CCC) loop or two point black current stabilisation can be observed. These measuring pulses have three DC-levels:

-A DC-level of -0.1V with respect to nominal black level during the leakage measurement (LO). This level is chosen so that it lies close to the black level in order to have an accurate measurement close to the cut off voltage of the picture tube.

-A pulse of +0,25V with respect to nominal black level, corresponding with a cathode current of 8µA

-A pulse of +0,50V above nominal black level which corresponds with a cathode current of 40µA. The pulse-levels of +0.25V and +0.50V can only be measured on alternating fields. The RGB blanking level tracks with the DC level of the black current measurement pulses. The total video signal (except the measuring pulses for the CCC-loop) can be blanked by activating the I (RGB blanking).

LO LR LG LB

+0.25V

Application Note

AN01045

C function RBL

-0.5V

-0.1V

Blanking

DC-levels of R-output during the black current measurement pulse

+0.38V

-0.1V

Blanking

DC-levels of R-output during the cathode drive current measurement pulse

Nominal Black level

Figure 29: DC-levels at RGB outputs

The Continuous Cathode Calibration (CCC) loop (or two point stabilisation loop) is an auto-tuning loop which stabilises the black level (offset) as well as the cathode drive level (gain) of each gun of the CRT sequentially and independently on alternating fields. The benefit of the CCC-loop can be explained by the figure below.

Philips Semiconductors Version 1.0

cathode drive current

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

no stabilisation

-no offset compensation

-gain spread

gain spread

offset

one point stabilisation two point stabilisation

gain spread

black current

measurement pulse

-gain spread

black current

measurement pulse

Figure 30: CCC-loop correction mechanisms

This figure shows the cathode current (I

) as function of one of the three video output signals (in this case

the red output) of the one chip. In case of no stabilisation, the transfer characteristic changes as function of temperature and ageing of the tube. This results in an offset and gain error (see above figure A).One point stabilisation corrects for offset variations and a two point stabilisation corrects for both offset and gain spreads as illustrated in figure C above.

The CCC-loop can be divided into two loops:

-a black level stabilisation loop (offset compensation)

-a cathode drive stabilisation loop (gain compensation) For the principal of the black current stabilisation loop please refer to application note AN95043 of the

TDA8375.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

TDA937X

Application Note

AN01045

Rfeedback

input

Rdrive

Rcutoff

10Kohm

Vref.

TDA61XX

RGB

40uA

drive correction

offset correction

fieldswitch

51,52,53

RGB-outputs

LR,LG,LB

8uA

Black current

Figure 31: Basic application of the CCC-loop with the TDA610X

Above the basic application of the CCC-loop with RGB amplifiers is given. In the figure the main two loops of black level stabilisation and cathode drive stabilisation are shown. The two loops are being stabilised on alternating fields by means of a field switch. The leakage measurement is carried out every field.

The main difference between the two loops is: During black level stabilisation internal black level clamps ensure that the DC-levels at RGB-outputs

are independently and sequentially changed so that alway s 8µA flows to the black current input (pin 50). During the 3L measurement pulses for the black current offset levels. The black current offset correction signals are stored in an internal capacitor.

During the cathode drive current stabilisation, internal multipliers ensure that the cathode drive level for the three guns of the CRT are independently and sequentially stabilised so that 40µA feedback current flows to the black current input during the 3L measurement pulses for the drive levels. The correction for the drive signals are stored in an internal capacitor.

The drive levels at the three cathodes of the tube are always adjusted by the CCC-loop such that the feedback current is 40µA. This means that the gain of the RGB-amplifier, e.g. TDA610X family, is NOT determining the drive level to the CRT anymore. In order to change the cathode levels at the picture tube

C bits are added CL3..0.

four I

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The table below shows the corresponding drive levels:

CL3 CL2 CL1 CL0 Variation Cathode Drive Level

0 0 0 0 50V 0 1 1 1 75V 1 1 1 1 95V

Table 31: Cathode drive levels

Changing the cathode level at the picture tube is achieved in the following way: The CL0123 bits vary the amplitude of the RGB channels together with the internal measurement pulses generated in a programmable pulse generator. During the 3 measurement lines (LR,LG,LB) these pulse levels are inserted on the RGB video signals. Cathode drive level can be adjusted between 50-95V by changing the CL0123 bits. The CL0123 bits are adjustable in 15 steps and each step result in 3.5V change at the cathode.

BL-Wh BL-Wh BL-Wh

TDA935X

Application Note

AN01045

Rfeedback

WPA -RGB

L0,1,2,3

RGB

Programmable

measuring pulse level generator

LR,LG,LB

40uA

drive correction

offset correction

fieldswitch

51,52,53

RGB-outputs

LR,LG,LB

8uA

Black current

input

Rdrive

Rcutoff

10Kohm

Vref.

TDA61XX

Figure 32: Main blocks of the CCC-loop

The drive correction signals (Dr, Dg, Db) will change the gain of the multipliers such that internal generated measurement pulse give a drive current measurement pulse at the cathode of the CRT corresponding with a current of 40µA. This 40µA current will be feedback to the black current input. The drive correction signals(Dr,Dg,Db) will be stored internally so that, after the 3 measurementpulses(LR,LG,LB), the actual RGB-video signals will have the same multiplication factor as determined during the drive current measurement pulses. The same procedure takes place during black current measurement except now the measurement pulses are adapted such that a 8µA cathode current is measured by adding the offset correction signals (Br, Bg , Bb) to the RGB-signals. By means of the field switch the programmable measurement pulse level generator switches the internal measurement pulse level corresponding with a 40µA cathode to a internal level corresponding with a 8µA cathode current.

Changing the WPR/WPG/WPB registers works on the same way as changing the CL0123 bits except for these three registers act on each individual RGB signal where the CL0123 bits act on all three RGB-signals together. So when changing the registers the internal generated measurement pulses are adapted at the input of the CCC-multiplier. The CCC-loop adjust itself so that the black current measurement pulses at the black current input are constant (8µA and 40µA).

Philips Semiconductors Version 1.0

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Start up behaviour of the CCC-loop

After H-out is released the RGB-outputs can be blanked (see RBL and RGBL bits). When the CCC-loop is active, the 250mV and 500mV measuring pulses are present at the RGB-outputs. The picture tube is warmed up via the 250mV and 500mV measuring pulses but due to the fact that the tube is cold the corresponding 8µA and 40µA pulses are not present at the black current input so the gain as well as the offset is set to maximum by the CCC-loop. This means that the amplitude of the 3 measuring pulses is maximum at the RGB outputs (with RBL=1, the actual scan reminds at blanking level). By means of these pulse the tube is warmed up. At the moment that the tube is warm the CCC-loop starts to measure 8µA and 40µA at the black current input pin and at that moment BCF becomes “0” which will be followed by releasing the RGB-outputs.

For applications without a picture tube the CCC-loop can be switched off by means of the I

AKB (Auto Kine Biasing).

Fixed beam current discharge:

When the set is switched off or switched to stand-by by setting STB = 0, the RGB outputs are set for a fixed beam current of 1 mA to discharge the picture tube (during switch-off) in a controlled way. During the switch-off-period the vertical deflection can be placed in an overscan position by setting the OSO–bit to “1” so that the discharge is not visible on the screen. In this case the switch off procedure is as follows:

Application Note

AN01045

C control bit

- The vertical deflection is immediately directed to the top of the screen (within max. 2 ms fly-back time)

- The RGB outputs are set for a beam current of 1 mA (measured via the black current input)

- OSO = 1 (the vertical deflection stays in the overscan position)

- OSO = 0 (the vertical deflection operates normal) The advantage of the fixed beam current switch-off is:

− No bleeder resistor for discharge needed (cost)

− The delta discharge voltage is controlled. It is advised to keep the delta discharge voltage below

500V/ms for better EMC behaviour.

The discharge current of 1mA is controlled by the black current loop and it is possible to discharge with higher current by connecting a current divider on black current loop. Over the series resistor (10KΩ) at the black current input diodes should be placed in order to make the discharge current of 1mA possible via the black current input. Without this diodes the voltage drop over the series resistor is too high (voltage drop: 1mA X 10KΩ =10V) so the fixed beam current switch-off function will not perform correctly. The 1mA discharge current is during 38ms after switch-off is detected. During this time the supply voltage of the IC should not drop down below 6.7V. This level is indicated with the SUP-bit. When the supply voltage drops below 6.4V than the SUP-bit become “0”.

When the set is switched off then a supply sense circuit has to be made in order to trigger the “fixed beam current switch -off “ function . For this triggering it is best to monitor when the scan supply voltage for the horizontal deflection stage starts to decrease (or another supply which start to decrease very fast after switch off). The output signal of the scan supply sense circuit has to be applied to the (EHTO-pin) and XDT has to be set to 0 to enable the switch-off. Under normal operation the output signal of this circuit has to be below the 1V.

An example of a scan supply sense circuit is given on the next page.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

V scan supply horizontal deflection

Application Note

AN01045

2µ2

47K

15K

+5V

330K

2.4V

to EHTO pin

Figure 33: Scan supply sense circuit

This circuit detects when the scan supply voltage starts to decrease and can generate a signal for the fixed beam current discharge function. It is important that the +5V in this circuit remains stable during the slow stop procedure SUP It is important that the 8V does not dip under 6.7V (SUP generated) during the slow switch off duration of 38ms; the RGB outputs will remain high then once the 8V supply is above 6.7V When a bleeder resistor is used to discharge the picture tube than it is not needed to use the fixed beam current discharge function. In this case the RGB output can be blanked by making RBL bit “1” during the switch off

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.10 PICTURE IMPROVEMENT FEATURES

FFI function

This feature improves IF video performance for excessive phase modulation that might occur in some market areas (i.e. India). For normal modulation, the standard loop filter is applied. For phase modulation (FM modulation of the IF carrier) and over modulation, the requirements of the IF PLL loop filter are contradictory. Phase modulation requires the loop response to be fast in order to follow the phase modulation while over modulation requires a slow response in order that there is no reaction to temporary phase inversions (180 phase jumps) in carrier when the modulation depth exceeds 100% When the I2C busbit FFI = 1, the IF PLL time constant remains normal for low carrier level, while for high carrier levels the IF PLL time constant is increased. In this way a better compromise between phase modulation and over modulation is achieved as shown below.

Note: When the I2C busbit FFI = 1, this had NO influence on search tuning speed.

Application Note

AN01045

High carrier amplitude :

Adapted PLL time constant Better for phase modulation (FM)

Low carrier amplitude : Normal PLL time constant

Better for over modulation

FFI = 1 :PLL time constant automatically adapted to carrier level

Better behaviour for phase modulation (FM) and over modulation

Figure 34: FFI principle

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Peaking function, ratio pre-shoot / overshoot:

A block diagram is shown to indicate the principle.

Application Note

AN01045

Y-signal

summing

peaking

Max.

peaking

stage

Min.

RP1.0

Ratio preshoot overshoot

Vout

Vin

peaking function

Figure 35: Peaking operation principle

The peaking function can be made asymmetric in black direction via the I2C busbits RP1, RP0 as indicated in the following table.

RPO1 RPO0 Ratio Preshoot Overshoot

0 0 1 : 1 0 1 1 : 1.25 1 0 1 : 1.5 1 1 1 : 1.8

Table 32

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

The peaking control gives peaking in both directions (i.e. pos. / neg. peaking) as indicated in peaking control curve as below.

Application Note

AN01045

-20

10 20 30

DAC (HEX)

Figure 36: Peaking control curve

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TDA937X PS N2 TV-processor + µP + CC

Black Stretch:

The black stretcher is a peak detector which detects the incoming luminance signal between 0 and 50IRE. It operates in a window defined for 50Hz and 60Hz systems as follows: The window is at 3us after begin line scan and ends 3us before end line scan; it continues for

- 300 lines beginning at line 131 to 431 for 50Hz systems

- 256 lines beginning at line 131 to 387 for 60Hz systems. As the amount of black in the video increases then the black stretcher is eventually switched off (this is for approximately 10% black in the total signal. The incoming peak level (towards black) of the Y signal (0 – 50IRE) is internally stored in a capacitor with an attack/delay time constant of approximately 200ms and depending upon the difference of the blanking level and the stored grey level, is the Y signal stretched towards black according to the black level characteristic shown below.

Application Note

AN01045

OUTPUT (IRE)

Max. black

level shift

at 15% of

peak white

100

-20

(Y-signal)

20 40 60

INPUT (IRE) 100

Figure 37: Transfer characteristic of black stretch.

The black stretch performance can be judged by having a black pluge with grey background. Switching on and off the black pluge results in black stretching in the grey signal and also the attack/decay time constants can be measured at the RGB outputs.

Note: The size of the black pluge must be small enough so that the black stretcher stays operating; if the black pluge exceeds approximately 5% of the total video signal, the black stretcher switches off.

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TDA937X PS N2 TV-processor + µP + CC

Dynamic skin control

Since the human eye is very sensitive to skin tone, then this features allows dynamic skin tone correction of colours/hues in the skin tone region. The U and V signals are detected in a window around the skin tone region and within this window correction shifts the skin colour to a correction angle in the UV plane as shown in the dynamic skin control characteristic shown below. The amount of correction is dependent upon the amplitudes of the incoming YUV signals and a correction angle of 45º (+/- 22.5º) degrees is valid for a signal amplitude of 75% and having a colour saturation of 50%. In principle tones at the outer parts of the detection window and near the skin tone point will be hardly corrected and tones in between this will be corrected most will be corrected most; also for small or high saturated colours then correction is also less (for 50% saturated colours, correction is most). The feature can be switched on/off via the I2C busbit DSK.

Application Note

AN01045

red

fully sa tu r a te d co lou rs

I-axis

yellow

Figure 38: Dynamic skin control

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Application Note

AN01045

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

6.11 SUPPLY, GROUNDING AND DECOUPLING

Pin 54, 56, 61 VddA / VddC / VddP 3.3 Volt Supplies

The TDA937X PS N2 has three supply pins for 3.3 volts. The functions are:

− Pin 54 (VddA) : Analog supply (Oscillator, ADC, digital logic TV processor)

− Pin 56 (VddC) : Digital supply to µprocessor core

− Pin 61 (VddP) : Supply to all output ports of the µprocessor

In the demo board there is separate decoupling for all the 3.3V supply pins. It is possible to combine the VddC and VddP decoupling for PCB layout optimisation. It is advised to have separate decoupling for VddA. The decoupling capacitors should be positioned as close to the pins as possible and grounded to the ground plane under the IC.

Application Note

AN01045

During normal operation as in stand-by, all 3.3 Volt supply pins must be supplied. Note that when 3.3 Volt is supplied, also the I out can be activated to start-up.

A low cost 3.3 V regulator circuit is shown at end of chapter where the 3.3 V is derived from an existing 5 V supply

Pin 14, 39 VP2 / VP1 8 Volt supplies

This voltage supplies the analog part of the video processor. The current consumption is divided equally between the two pins. Short supply decoupling is important for both pins, for pin 14 with external capacitor to ground pin 18, for pin

39 with external capacitor to ground pin 41. Take care that at switch-on of the +8 Volt supply the rise time at

both pins is about equal. In stand-by condition the 8V IC-supply can be switched off as to save energy. When the 3.3 Volt supply is present, still all I up. This enables to supply the +8 Volts from scan rectification of a winding of the FBT. The +8 Volt can be monitored by the SUP bit, SUP becomes 1 when the supply voltage rises above 6.5 Volt and becomes 0 when the supply voltage drops below 6.2 Volt. Below 6.2 Volt H-out is stopped and the RGB outputs are blanked (remain below 8V)

Pin 15 DECDIG Digital Decoupling

C registers of the video processor can be written and the H-out can be activated to start-

C registers of the video processor can be written and the H-

This pin decouples the internal digital supply voltage of the video processor and minimises the disturbance to the sensitive analogue parts. For optimal decoupling use a capacitor of 220 nF with minimum track length to VssA (pin 12) which is the main digital ground of the video processor.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Pin 19 DECBG Bandgap decoupling

The bandgap circuit provides a very stable and temperature independent reference voltage. This reference voltage (4.0 V) ensures optimal performance of the analogue video processor part of the TDA937X PS N2 and is used in almost all functional circuit blocks. Short decoupling to ground pin 18 of the external capacitor is important. For best performance, a capacitor value of 2.2 µF in parallel with a high frequent decoupling capacitor (100nF or 22nF) is recommended.

Pin 9, 12, VssC/P , VssA Ground microprocessor Pins 18, 30, 41 GND3 / GND2 / GND1 Ground videoprocessor

The TDA937X N2 PS has 5 ground pins. The functions are:

− Pin 9 (VssC/P) Digital ground µprocessor core and peripherals

− Pin 12 (VssA) Analog ground µprocessor and digital ground TV processor

− Pin 18 (GND3) Analog ground 3 of videoprocessor

− Pin 30 (GND2) Analog ground 2 of videoprocessor

− Pin 41 (GND1) Analog ground of videoprocessor

Application Note

AN01045

In the layout, it is best to design a ground plane underneath the IC and connect all ground pins as short as possible to this ground plane. Note that the ground plane should have a low impedance, no bridge wires or 0 Ohm SMD’s are allowed. Low ohmic connection of all ground pins is very important for performance. A ground plane gives following advantages:

− optimal connection between all ground pins

− easy grounding of peripherals (short connection of single components to ground when SMD’s are used)

− no other signal tracks under the IC (radiation)

− optimal for EMC

For easy routing, it is possible to make an outside connection from the ground plane via pin 55 (VPE). Grounding of this pin has no consequences for operation and in this way a ground is available for supply decoupling of the supply pins 54, 56 and 61.

Note: Do not connect pin 57 (oscillator ground) to the ground plane. See below.

Pin 57 OSCGND Ground oscillator

This ground pin is only intended to use for connecting the two capacitors of the oscillator. This pin should be left floating. No other components should be connected to this pin.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

All Pins Pin protection for ESD

All IC-pins have internal protection diodes, one to supply and one to ground for ESD protection, see Under normal operation and supply-off condition these diodes may not conduct. Otherwise excessive current can flow through these diodes and/or internal circuit parts and the IC will be damaged.

Application Note

AN01045

positive

All ESD protection diodes meet the specification of both Human body and Machine model. Nevertheless for safe operation each pin voltage should remain in between:

For µprocessor related pins:

− Normal IC operation and supply is 3.3V: - 0.7V….+

− No supply (0 V) : - 0.7V….+

For video processor related pins:

- normal IC operation and supply is 8V: - 0.7V….+ 8.7V

- in stand-by condition and supply is 0V: - 0.7V….+ 0.7V

(1) µprocessor I/O pins, configured as open drain, can handle +5 Volt e.g. when connected via pull-up (2) The tuner AGC output pin 27 may have a higher voltage, V

Note:

- When the supply =0V avoid that IC pins are supplied by external connected components.

- Maximum voltage for CVBS/Y input pins is 5.5V. This to avoid parasitic effect at the pin.

(1)

4.0V

0.7V

resistors to the + 5 Volt for I the tuner more easy.

We have had no problems so far when the continuous protection diode current is less than 1mA.

C..

PinX

Figure 39: ESD pin protection

(2)

< Vcc + 1V. This makes the application with

internal pin circuitry

Ground

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

Supply start-up, shutdown, I

C, protections

Application Note

AN01045

The coherence between supply voltage, I

C and the protections is given under the following conditions:

− 3.3 Volt

− 8 Volt when supplied from the main supply

− 8 Volt when supplied from the Flyback Transformer, using Low Voltage Startup

3.3 Volt supply

A POR generation is directly coupled with the VddA 3.3 V supply at pin 54 A POR can be generated from:

- External reset pulse at pin 60

- Internal POR from video processor when VddA dips less than approximately 2.5V.

- Internal POR from uprocessor when VddA is typically 2V (refer to report for exact details)

For further details of POR generation internal architecture see Reference [9] The internal POR generation for the video processor is treated in the following description.

We will cover the 4 different situations as given in the picture below.

3.3

2.65

Supply

3.3 V

POR



* Reset to 0 first status register read after the voltage on 3.3 Volt supply pins is above 2.65 Volt

I2C bus

** When POR = 1, read till POR = 0 and rewrite all I2C registers with STB = 0. Then set STB = 1

STB

Hout

Reset

Condition



Reset

Condition

Slow Start



Reset

Condition

Slow Start



Slow Start

Figure 40: POR generation for internal videoprocessor

1. When the 3.3 supply line rises, the µprocessor has to read continues the POR bit. When it is possible to read (I

C hardware is functional) the POR bit will read 1 as long as the 3.3 Volt supply voltage is below

2.65 Volts. The first read of POR after the moment the 3.3 Volt supply rises above 2.65 Volts will still return POR = 1 but resets POR to 0. The next read will return POR = 0. Once POR = 0, all I

C registers have to be written, preferably keeping the set in stand-by writing STB =

After this initialisation the H-out can be started by writing STB = 1. The H-out will start to run according the slow start procedure

and continues in normal mode.

2. When the 3.3 Volt supply voltage drops shortly (spike) below 2.65 Volts, the POR bit is set to 1. The POR bit is latched, so the next status read will always return POR = 1, irrespective the duration of the power dip. At the same moment, the H-out is immediately stopped. The reason for this action is that the contents of

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

C registers cannot be guaranteed any more once the 3.3 Volt supply voltage drops below 2.65 Volt.

all I To prevent unpredictable behaviour due to wrong I To start-up again, the µprocessor has to read the status bytes until POR = 0. Then all I to be written (preferably setting STB = 0), because they can be corrupted. Then the set can be started up again writing STB = 1.

3. When the 3.3 Volt supply drops below 2.65 Volts, immediately the H-out is stopped and the device is put in reset condition.

C settings, the device is put in reset condition.

Application Note

AN01045

C registers have

4. Once the voltage rises again above 2.65 Volts, the procedure is the same as written under 1.

Note that the 3.3 Volt supply is key for basic operation of the µprocessor part, the digital part (I registers) and the H-out drive circuit. Checking the 3.3 Volt supply reading POR and taking appropriate action when POR =1 has absolute priority over all other matters.

Philips Semiconductors Version 1.0

TDA937X PS N2 TV-processor + µP + CC

8 Volt, when supplied from the main supply

Application Note

AN01045

6.4

6.2

Supply

8 V

SUP

STB

Hout

RGB

Slow Start

Slow Stop

Slow Start

Slow Stop

1 mA disch

Slow Start

Slow Stop

1 mA disch

V pin 16

PHI 2

V pin 36

EHTO

6 V

3.9 V

XPR

* Reset to 0 first status register read after the voltage on pin 36 is below 3.9 Volt



Figure 41: 8 Volt supply from main supply

1. We assume that the 3.3 Volt supply is ok and all I

C registers have been written. When the 8 Volt supply rises, the SUP bit will toggle from 0 to 1 once the level reaches 6.4 Volt. We advice to check this bit to ensure that the power supply is functioning properly. At the moment STB is written 1, the H-out will start according the slow start procedure and continue running in normal mode. Note that it is allowed to write STB = 1 before the 8 Volt is present (only 3.3 Volt present). In that case, the H-out will start according the Low Voltage Start-up procedure including slow start. However, first when the 8 Volt is present, all other circuits will be functional and the CCC loop will start to

100

Philips AN01045 APPLICATION NOTE

Specifications and Main Features

Frequently Asked Questions

User Manual

Figure 1: Pinning configuration

5.1 INPUT CONTROL BITS

5.2 OUTPUT CONTROL BITS

6.5 THE NARROW BAND PLL

6.6 FILTERS, SWITCHES AND COLOUR DECODER

6.7 HORIZONTAL AND VERTICAL SYNC GEOMETRY

6.8 GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION

6.9 YUV / RGB PROCESSING AND CONTROL