Philips 74LVT652PW, 74LVT652DB, 74LVT652D Datasheet

INTEGRATED CIRCUITS

74LVT652

3.3V Octal transceiver/register,
non-inverting (3-State)

Product specification
Supersedes data of 1994 May 20
IC23 Data Handbook

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1998 Feb 19

Philips Semiconductors Product specification

3.3V Octal transceiver/register, non-inverting
(3-State)

FEA TURES

•Independent registers for A and B buses

•Multiplexed real-time and stored data

•3-State outputs

•Output capability: +64mA/–32mA

•TTL input and output switching levels

•Input and output interface capability to systems at 5V supply

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Live insertion/extraction permitted

•No bus current loading when output is tied to 5V bus

•Power-up 3-State

•Power-up reset

•Latch–up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

SYMBOL PARAMETER

t

PLH

t

PHL

C
C
I

CCZ

IN

I/O

Propagation delay
An to Bn or Bn to An

Input capacitance VI = 0V or 3V 4 pF
I/O capacitance Outputs disabled; V
Total supply current Outputs disabled; VCC = 3.6V 0.13 mA

DESCRIPTION

The LVT652 is a high-performance BiCMOS product designed for
V

CC

This device combines low static and dynamic power dissipation with
high speed and high output drive.

The 74LVT652 transceiver/register consists of bus transceiver
circuits with 3-State outputs, D–type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA
bus management.

T

amb

CL = 50pF;
VCC = 3.3V

operation at 3.3V .

CONDITIONS
= 25°C; GND = 0V

= 0V or 3V 10 pF

I/O

74L VT652

) and Select (SAB, SBA) pins are provided for

TYPICAL UNIT

2.8

2.6

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic SOL –40°C to +85°C 74LVT652 D 74LVT652 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74LVT652 DB 74LVT652 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT652 PW 74LVT652PW DH SOT355-1

PIN CONFIGURATION

1

CPAB

2

SAB

3

OEAB

4

A0

5

A1

6

A2

7

A3

8

A4

9

A5

10

A6

11

A7

12

GND

24
23
22
21
20
19
18
17
16
15
14
13

SV00051

V

CC

CPBA
SBA
OEBA
B0
B1
B2
B3
B4
B5
B6
B7

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1, 23

CPAB /

CPBA

2, 22 SAB / SBA

3, 21

4, 5, 6, 7, 8, 9,

10, 11

20, 19, 18, 17,

16, 15, 14, 13

OEAB /

OEBA

A0 – A7 Data inputs/outputs (A side)

B0 – B7 Data inputs/outputs (B side)

12 GND Ground (0V)
24 V

CC

A to B clock input / B to A
clock input

A to B select input / B to A
select input

A to B Output Enable input
(active-High) /
B to A Output Enable input
(active-Low)

Positive supply voltage

1998 Feb 19 853-1748 18987

2

Philips Semiconductors Product specification

3.3V Octal transceiver/register, non-inverting
(3-State)

LOGIC SYMBOL

4567891011

A0 A1 A2 A3 A4 A5 A6 A7

23

CPBA

22

SBA
2 SAB
1CPAB

B0 B1 B2 B3 B4 B5 B6 B7

20 19 18 17 16 15 14 13

3OEAB
21OEBA

SV00052

LOGIC SYMBOL (IEEE/IEC)

21

3
23
22

1

2

4

5

6

7

8

9

10

11

EN1(BA)
EN2(AB)

C4

G5

C6

G7

≥1

∇1

6D 7

17

54D

5

1

≥1

2

74LVT652

20

19

18

17

16

15

14

13

SV00053

LOGIC DIAGRAM

OEBA
OEAB
CPBA

SBA

CPAB

SAB

21

3
23
22

1

2

Detail A;

1 of 8 Channels

4

A0

5

A1

6

A2

7

A3

8

A4

9

A5

10

A6

11

A7

1D

C1

Q

DETAIL A X 7

1D

C1

Q

20

B0

19

B1

18

B2

17

B3

16

B4

15

B5

14

B6

13

B7

SV00054

1998 Feb 19

3

Philips Semiconductors Product specification

OPERATING MODE

3.3V Octal transceiver/register, non-inverting
(3-State)

The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74LVT652.

REAL TIME BUS TRANSFER

BUS B TO BUS A

A A

REAL TIME BUS TRANSFER

BUS A TO BUS B

B B B B

74LVT652

The select pins determine whether data is stored or transferred
through the device in real time.

The output enable pins determine the direction of the data flow.

STORAGE FROM

A, B, OR A AND B

A

TRANSFER STORED DA TA

TO A OR B

A

}

OEABOEBA CPABCPBA SAB SBA

LLXXXL

OEABOEBA CPABCPBA SAB SBA

HHXX LX

}

}

OEABOEBA CPABCPBA SAB SBA

XH↑ XXX
LXX↑ XX
LH↑↑XX

}

OEABOEBA CPABCPBA SAB SBA

H L H | L H | L H H

SV00055

FUNCTION TABLE

INPUTS DATA I/O

OEAB OEBA CPAB CPBA SAB SBA An Bn

L
L

X

H

L
L

L
L

H
H

H L H or L H or L H H Output Output

H = High voltage level
L = Low voltage level
X = Don’t care
↑ = Low-to-High clock transition
* The data output function may be enabled or disabled by various signals at the OEBA

enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.

** If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be

staggered in order to load both registers.

H
H

H
H

X
L

L
L

H
H

H or L

↑
↑

↑

H or L

↑

X
X

X

H or L

H or L

↑

H or L

↑
↑

↑

X

H or L

X
X

X

X

X

X

X

X

**

X

X

X**Unspecified**

X
X

X
L

H

L

H
X

X

Input Input

Input

Output*

Output Input

Input Output

Unspecified**

Output*

Input

Isolation
Store A and B data

Store A, Hold B
Store A in both registers

Hold A, Store B
Store B in both registers

Real time B data to A bus
Stored B data to A bus

Real time A data to B bus
Store A data to B bus

Stored A data to B bus
Stored B data to A bus

and OEAB inputs. Data input functions are always

1998 Feb 19

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Philips Semiconductors Product specification

I

DC output current

mA

SYMBOL

PARAMETER

UNIT

3.3V Octal transceiver/register, non-inverting
(3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

V

I
V

I

OK

OUT

OUT

T

CC

IK

stg

DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage

p

Storage temperature range –65 to +150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

3

1,2

–0.5 to +7.0 V

Output in Off –0.5 to +7.0 V

Output in Low state 128

Output in High state –64

74LVT652

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

V

CC

V

V

V

I

OH

I

OL

∆t/∆v Input transition rise or fall rate; Outputs enabled 10 ns/V

T

amb

DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V

I

High-level input voltage 2.0 V

IH

Input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 32 mA
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 64

Operating free-air temperature range –40 +85 °C

1998 Feb 19

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