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INTEGRATED CIRCUITS
74LVT573
3.3V Octal D-type transparent latch
(3-State)
Product specification
Supersedes data of 1995 Nov 14
IC23 Data Handbook
1998 Feb 19
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Philips Semiconductors Product specification
3.3V Octal D-type transparent latch
(3-State)
FEA TURES
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•3-State output buffers
•Common output enable
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•No bus current loading when output is tied to 5V bus
•Latch-up protection exceeds 500mA per JEDEC Std 17
•Power-up 3-State
•Power-up reset
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
I
CCZ
IN
OUT
Propagation delay
Dn to Qn
Input capacitance VI = 0V or 3.0V 4 pF
Output capacitance Outputs disabled; VO = 0V or 3.0V 8 pF
Total supply current Outputs disabled; VCC = 3.6V .13 mA
DESCRIPTION
The LVT573 is a high-performance BiCMOS product designed for
VCC operation at 3.3V. This device is an octal transparent latch
coupled to eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (E) and Output
Enable (OE
configuration to facilitate PC board layout and allow easy interface
with microprocessors.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the latch operation.
When OE
outputs. When OE
“OFF” state, which means they will neither drive nor load the bus.
T
amb
CL = 50pF; VCC = 3.3V
is Low, the latched or transparent data appears at the
CONDITIONS
= 25°C; GND = 0V
74L VT573
) control gates. The 74LVT573 has a broadside pinout
) controls all eight 3-State buffers
is High, the outputs are in the High-impedance
TYPICAL UNIT
2.5
2.7
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic SOL –40°C to +85°C 74LVT573 D 74LVT573 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT573 DB 74LVT573 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT573 PW 74LVT573PW DH SOT360-1
PIN CONFIGURATION
OE
120
2
D0
3
D1
4
D2
5
D3
D4
6
D5
7
D6
8
D7
9
GND
10
19
18
17
16
15
14
13
12
11
SV00031
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
CC
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE
2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs
19, 18, 17, 16, 15,
14, 13, 12
Q0-Q7 Data outputs
11 E
10 GND Ground (0V)
20 V
CC
Output enable input
(active-Low)
Enable input
(active-High)
Positive supply voltage
1998 Feb 19 853–1750 18988
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Philips Semiconductors Product specification
3.3V Octal D-type transparent latch
(3-State)
LOGIC SYMBOL
23456789
D0 D1 D2 D3 D4 D5 D6 D7
11
E
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
SV00032
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
C1
2
1D
3
4
5
6
7
8
9
74LVT573
19
18
17
16
15
14
13
12
SV00033
FUNCTION TABLE
INPUTS
OE E Dn
L
L
L
L
H
H
H
↓
↓
L
I
h
INTERNAL
REGISTER
L
H
L
H
L L X NC NC Hold
H X X NC Z Disable outputs
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition
OUTPUTS
Q0 – Q7
L
H
L
H
Enable and read register
Latch and read register
LOGIC DIAGRAM
D0
2
D
D1
3
D
D2
4
D
D3
5
D
D4
6
D
D5
7
D
D6
8
D
D7
9
D
11
E
1
OE
1998 Feb 19
E Q
Q0
EQ
19
Q1
EQ
18
Q2
EQ
17
Q3
EQ
16
Q4
EQ
15
Q5
EQ
14
Q6
EQ
13
12
Q7
SV00034
3
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Philips Semiconductors Product specification
3.3V Octal D-type transparent latch
74LVT573
(3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
V
CC
I
IK
V
I
OK
OUT
OUT
T
stg
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage
I
DC output diode current VO < 0 –50 mA
DC output voltage
p
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
–0.5 to +7.0 V
Output in Off or High state –0.5 to +7.0 V
Output in Low state 128
Output in High state –64
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
CC
V
V
V
I
OH
OL
∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V
T
amb
DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V
I
High-level input voltage 2.0 V
IH
Input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 32
Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64
Operating free-air temperature range –40 +85 °C
1998 Feb 19
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