Philips 74LVT534PW, 74LVT534DB, 74LVT534D Datasheet
INTEGRATED CIRCUITS
74LVT534
3.3V Octal D-type flip-flop; inverting
(3-State)
Product specification
Supersedes data of 1996 Aug 13
IC23 Data Handbook
1998 Feb 19
Philips Semiconductors Product specification
74L VT5343.3V Octal D-type flip-flop, inverting (3-State)
FEA TURES
•3-State outputs for bus interfacing
•Common output enable
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•No bus current loading when output is tied to 5V bus
•Power-up 3-State
•Power-up reset
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
CP to Qn
Input capacitance VI = 0V or 3.0V 4 pF
Output capacitance
Total supply current
DESCRIPTION
The LVT534 is a high-performance BiCMOS product designed for
V
operation at 3.3V .
CC
This device is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE
gates. The state of each D input (one set-up time before the
Low-to-High clock transition) is transferred to the corresponding
flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “off” state, which
means they will neither drive nor load the bus.
CONDITIONS
T
= 25°C; GND = 0V
amb
CL = 50pF;
VCC = 3.3V
Outputs disabled;
V
= 0V or 3.0V
I/O
Outputs disabled;
VCC = 3.6V
) control
) controls all eight 3-State buffers
TYPICAL UNIT
3.0
3.5
ns
7 pF
0.13 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic SOL –40°C to +85°C 74LVT534 D 74LVT534 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT534 DB 74LVT534 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT534 PW 74LVT534PW DH SOT360-1
PIN CONFIGURATION
1
OE
2
Q0
3
D0
4
D1
5
1
Q
6
Q2
7
D2
8
D3
9
Q
3
GND
10 11
20
19
18
17
16
15
14
13
12
SA00161
V
Q7
D7
D6
Q
Q5
D5
D4
Q
CP
CC
6
4
LOGIC SYMBOL
11
1
3478
D0 D1 D2 D3
CP
OE
Q0 Q1 Q296Q3
52
13 14 17 18
D4 D5 D6 D7
Q4 Q5 Q6
1512
SA00162
Q7
1916
1998 Feb 19 853-1855 18988
2
Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
13
14
17
18
C1
3
1D
4
7
8
2
5
6
9
12
15
16
19
SA00163
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS
OE CP Dn REGISTER Q0 – Q7
LL↑
L ↑ X NC NC Hold
HH↑
↑
↑XDn
l
h
H
NC
Dn
L
H
L
Z
Z
OPERATING
MODE
Latch and read
register
Disable
outputs
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17, 18
2, 5, 6, 9,
12, 15, 16, 19
11 CP
10 GND Ground (0V)
20 V
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High
clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High
clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= not a Low-to-High clock transition
↑
D0-D7 Data inputs
Q0-Q7 Inverting 3-State outputs
Clock pulse input (active rising
edge)
Positive supply voltage
CC
LOGIC DIAGRAM
D0
11
CP
1
OE
2
D
CP Q
Q0
D1
3
D
CP Q
19
Q1
D2
4
D
CP Q
18
Q2
D3
5
D
CP Q
17
Q3
D4
6
D
CP Q
16
Q4
D5
7
D
CP Q
15
Q5
D6
8
D
CP Q
14
Q6
D7
9
D
CP Q
13
12
Q7
SV00168
1998 Feb 19
3
Philips Semiconductors Product specification
I
DC output current
mA
SYMBOL
PARAMETER
UNIT
I
mA
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
PARAMETER CONDITIONS RATING UNIT
3
1, 2
–0.5 to +7.0 V
3
Output in Off or High state –0.5 to +7.0 V
Output in Low state 128
OUT
T
stg
p
Output in High state –64
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
CC
V
I
V
IH
V
IL
I
OH
OL
∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V
T
amb
DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V
High-level input voltage 2.0 V
Input voltage 0.8 V
High-level output current –32 mA
Low-level output current 32
Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64
Operating free-air temperature range –40 +85 °C
1998 Feb 19
4
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