Philips 74LVT374DB, 74LVT374D, 74LVT374PW Datasheet
INTEGRATED CIRCUITS
74LVT374
3.3V Octal D-type flip-flop; positive-edge
trigger (3-State)
Product specification
Supersedes data of 1996 Feb 08
IC23 Data Handbook
1998 Feb 19
Philips Semiconductors Product specification
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
FEA TURES
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•3-State outputs for bus interfacing
•Common output enable
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•No bus current loading when output is tied to 5V bus
•Power-up 3-State
•Power-up reset
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
CP to Qn
Input capacitance VI = 0V or 3.0V 4 pF
Output capacitance
Total supply current
CL = 50pF;
VCC = 3.3V
Outputs disabled;
V
Outputs disabled;
VCC = 3.6V
DESCRIPTION
The 74LVT374 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74LVT374 is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the clock operation.
When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
T
amb
= 0V or 3.0V
I/O
is Low, the stored data appears at the outputs. When OE
CONDITIONS
= 25°C; GND = 0V
74L VT374
) control
) controls all eight 3-State buffers
TYPICAL UNIT
3.2
3.5
7 pF
0.13 mA
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic SOL –40°C to +85°C 74LVT374 D 74LVT374 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT374 DB 74LVT374 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT374 PW 74LVT374PW DH SOT360-1
PIN CONFIGURATION
1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3 Q4
10 11
GND
20
V
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
12
CP
SA00110
CC
PIN DESCRIPTION
PIN
NUMBER
1 OE Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17,
18
2, 5, 6, 9,
12, 15, 16,
19
11 CP Clock pulse input (active rising edge)
10 GND Ground (0V)
20 V
SYMBOL FUNCTION
D0-D7 Data inputs
Q0-Q7 Data outputs
Positive supply voltage
CC
1998 Feb 19 853-1826 18985
2
Philips Semiconductors Product specification
INTERNAL
OPERATING MODE
Load and read register
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
LOGIC SYMBOL
3 4 7 8 13 14 1817
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SA00111
FUNCTION TABLE
INPUTS
OE CP Dn
L ↑ l L L
L ↑ h H H
L ↑ X NC NC Hold
H X X NC Z Disable outputs
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= not a Low-to-High clock transition
↑
INTERNAL
REGISTER
LOGIC SYMBOL (IEEE/IEC)
OUTPUTS
Q0 – Q7
74LVT374
1
11
32
4 5
7 6
89
13 12
14 15
17 16
18 19
EN
C1
1D
SA00112
LOGIC DIAGRAM
11
CP
1
OE
1998 Feb 19
D0
3 4 7 8 13 14 17 18
D
CP Q
D1
D
CP Q
2 5 6 9 12 15 16 19
Q0
D2
D
CP Q
Q1 Q2 Q3 Q4 Q5 Q6 Q7
D3
D
CP Q
D4
D
CP Q
D5
D
CP Q
D6
D
CP Q
3
D7
D
CP Q
SA00113
Philips Semiconductors Product specification
I
DC output current
mA
SYMBOL
PARAMETER
UNIT
I
mA
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
V
I
V
I
OK
OUT
OUT
T
CC
IK
I
stg
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
PARAMETER CONDITIONS RATING UNIT
3
p
1, 2
–0.5 to +7.0 V
3
Output in Off or High state –0.5 to +7.0 V
Output in Low state 128
Output in High state –64
74LVT374
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
CC
V
I
V
IH
V
IL
I
OH
OL
∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V
T
amb
DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V
High-level input voltage 2.0 V
Input voltage 0.8 V
High-level output current –32 mA
Low-level output current 32
Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64
Operating free-air temperature range –40 +85 °C
1998 Feb 19
4
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