Philips 74LVT240D, 74LVT240PW Datasheet

INTEGRATED CIRCUITS

74LVT240

ABT octal inverting buffer (3-State)

Product specification
Supersedes data of 1994 May 16
IC23 Data Handbook

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1998 Feb 19

Philips Semiconductors Product specification

74L VT2403.3V Octal inverting buffer (3-State)

FEA TURES

•Octal bus interface

•3-State buffers

•Output capability: +64mA/-32mA

•TTL input and output switching levels

•Input and output interface capability to systems at 5V supply

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Power-up 3-State

•Live insertion/extraction permitted

•No bus current loading when output is tied to 5V bus

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model.

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay
nAx to nYx

Input capacitance VI = 0V or 3.0V 4 pF
Output capacitance Outputs disabled; VO = 0V or 3.0V 8 pF
Total supply current Outputs disabled; VCC = 3.6V 0.12 mA

CL = 50pF;
VCC = 3.3V

DESCRIPTION

The LVT240 is a high-performance BiCMOS product designed for
V

operation at 3.3V .

CC

This device is an octal inverting buffer that is ideal for driving bus
lines. The device features two Output Enables (1OE
controlling four of the 3-State outputs.

CONDITIONS

T

= 25°C; GND = 0V

amb

TYPICAL UNIT

2.5

2.6

, 2OE), each

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic SOL –40°C to +85°C 74LVT240 D 74LVT240 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT240 DB 74LVT240 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT240 PW 74LVT240PW DH SOT360-1

PIN CONFIGURATION

1

1OE

1A0

2

2Y

3

3

4

1A1

5

2Y2

6

1A2

7

2Y

1

8

1A3

9

2Y

01Y3

10 11

GND

20

V

CC

19

2OE

18

1Y0

17

2A3

16

1

1Y

15

2A2

14

2

1Y

13

2A1

12

2A0

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

2, 4, 6, 8 1A0 – 1A3 Data inputs
11, 13, 15, 17 2A0 – 2A3 Data inputs
18, 16, 14, 12 1Y0 – 1Y3 Data outputs

9, 7, 5, 3 2Y0 – 2Y3 Data outputs

1, 19 1OE, 2OE Output enables

10 GND Ground (0V)
20 V

CC

Positive supply voltage

SV00006

1998 Feb 19 853-1744 18991

2

Philips Semiconductors Product specification

I

DC output current

mA

74LVT2403.3V Octal inverting buffer (3-State)

LOGIC SYMBOL

1A0

2

1A1

4

1A2

6

1A3

8

1OE

1

2A0

11

2A1

13

2A2

15

2A3

17

2OE

19

FUNCTION TABLE

INPUTS OUTPUTS

nOE nAx nYx

L L H
L H L

H X Z

H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “Off” state

1Y

1Y

1Y

1Y

2Y0

2Y

2Y

2Y

LOGIC SYMBOL (IEEE/IEC)

0

18

1

16

2

14

3

12

9

1

7

2

5

3

3

SV00007

1

EN

2
4
6
8

19

EN

11
13
15
17

18
16
14
12

9
7
5
3

SV00008

ABSOLUTE MAXIMUM RA TINGS

SYMBOL

V

CC

V

I

V

OUT

DC supply voltage –0.5 to +4.6 V
DC input voltage
DC output voltage

PARAMETER CONDITIONS RATING UNIT

3

3

1, 2

–0.5 to +7.0 V

Output in Off or High state –0.5 to +7.0 V

Output in Low state 128

OUT

I

IK

I

OK

T

stg

p

Output in High state –64
DC input diode current VI < 0 –50 mA
DC output diode current VO < 0 –50 mA
Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

1998 Feb 19

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