INTEGRATED CIRCUITS
74LVT16646A
3.3V ABT 16-bit bus transceiver (3-State)
Product specification
Supersedes data of 1994 Jul 25
IC23 Data Handbook
1998 Feb 19
Philips Semiconductors Product specification
74L VT16646A3.3V 16-bit bus transceiver (3-State)
FEA TURES
•16-bit universal bus interface
•3-State buffers
•Output capability: +64mA/-32mA
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•No bus current loading when output is tied to 5V bus
•Power-up reset
•Power-up 3-State
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
C
C
I
CCZ
IN
I/O
Propagation delay
nAx to nBx or nBx to nAx
Input capacitance VI = 0V or 3.0V 3 pF
I/O pin capacitance Outputs disabled; V
Total supply current Outputs disabled; VCC = 3.6V 70 µA
CL = 50pF;
VCC = 3.3V
DESCRIPTION
The 74LVT16646A is a high-performance BiCMOS product
designed for V
This device is a 16-bit transceiver featuring non-inverting 3-State
bus compatible outputs in both send and receive directions. The
control function implementation minimizes external timing
requirements. The device features an Output Enable (OE
easy cascading and a Direction (DIR) input for direction control.
Data on the A or B bus is clocked into the registers on the Low to
High transition of the appropriate clock (CPAB or CPBA). The
select-control (SAB and SBA) inputs can multiplex stored and
real-time (transparent mode data).
CONDITIONS
T
amb
operation at 3.3V .
CC
= 25°C
TYPICAL UNIT
1.9 ns
= 0V or 3.0V 9 pF
I/O
) input for
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74LVT166646A DL VT16646A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74LVT16646A DGG VT16646A DGG SOT364-1
LOGIC SYMBOL (IEEE/IEC)
56
1
54
3
55
2
5
6
8
9
10
12
13
14
G3
3EN1 [BA]
3EN2 [AB]
G6
G7
C4
C5
≥1
∇1
5D 7
17
64D
1
6
≥1
2∇
29
28
31
26
31
27
52
15
51
16
49
17
48
19
47
20
45
21
44
23
43
24
G10
10EN8 [BA]
10EN9 [AB]
G13
G14
C11
C12
≥1
∇8
12D 14
114
13 11D
1
13
≥1
9∇
42
41
40
38
37
36
34
33
SW00157
1998 Feb 19 853-1760 18986
2
Philips Semiconductors Product specification
74LVT16646A3.3V 16-bit bus transceiver (3-State)
PIN CONFIGURATION
1
1DIR
2
1CPAB
1SAB
3
GND
4
1A0
5
1A1
6
7
V
CC
8
1A2
1A3
9
1A4
10
GND
11
1A5
12
1A6
13
1A7
14
2A0
15
16
2A1
2A2
17
GND
18
2A3
19
20
2A4
21
2A5
22
V
CC
23
2A6
24
2A7
GND
25
26
2SAB
27
2CPAB
28
2DIR
SH00026
LOGIC SYMBOL
56
1OE
55
1CPBA
1SBA
54
GND
53
1B0
52
1B1
51
50
V
CC
49
1B2
1B3
48
1B4
47
GND
46
1B5
45
1B6
44
1B7
43
2B0
42
41
2B1
2B2
40
GND
39
2B3
38
37
2B4
36
2B5
35
V
CC
34
2B6
33
2B7
GND
32
31
2SBA
30
2CPBA
29
20E
2
3
1 1DIR
55 1CPBA
54 1SBA
56 1OE
27
26
28 2DIR
30 2CPBA
31 2SBA
29 2OE
5 9 10 12 13 1468
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1CPAB
1SAB
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
52 51 49 48 47 45 44 43
15 16 17 19 20 21 23 24
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
2CPAB
2SAB
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
42 41 40 38 37 36 34 33
SH00027
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 55, 27, 30 1CPAB, 1CPBA, 2CPAB, 2CPBA Clock input A to B / Clock input B to A
3, 54, 26, 31 1SAB, 1SBA, 2SAB, 2SBA Select input A to B / Select input B to A
1, 28 1DIR, 2DIR Direction control inputs
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
56, 29 1OE, 2OE Output enable inputs
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
1998 Feb 19
1A0 - 1A7,
2A0 - 2A7
1B0 - 1B7,
2B0 - 2B7
CC
3
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Positive supply voltage
Philips Semiconductors Product specification
74LVT16646A3.3V 16-bit bus transceiver (3-State)
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74LVT16646A.
REAL TIME BUS TRANSFER
BUS B TO BUS A
ABAB AB
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
}
nOE nDIR nCPAB nCPBA nSAB nSBA
LLXXXL
}
nOE nDIR nCPAB nCPBA nSAB nSBA
LH X X LX
TRANSFER STORED DA TA
TO A OR B
AB
}
nOE nDIR nCPAB nCPBA nSAB nSBA
LH ↑ XXX
LL X ↑ XX
HX ↑↑XX
1998 Feb 19
}
nOE nDIR nCPAB nCPBA nSAB nSBA
L L X H | L X H
L H H | L X H X
SH00028
4