Philips 74lvt16373a DATASHEETS
INTEGRATED CIRCUITS
74LVT16373A
3.3V LVT 16-bit transparent D-type latch
(3-State)
Product specification
Supersedes data of 1994 Dec 15
IC23 Data Handbook
1998 Feb 19
Philips Semiconductors Product specification
74L VT16373A3.3V 16-bit transparent D-type latch (3-State)
FEA TURES
•16-bit transparent latch
•3-State buffers
•Output capability: +64mA/-32mA
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•Power-up reset
•Power-up 3-State
•No bus current loading when output is tied to 5V bus
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
nDx to nQx
Input capacitance VI = 0V or 3.0V 3 pF
Output capacitance Outputs disabled; VO = 0V or 3.0V 9 pF
Total supply current Outputs disabled; VCC = 3.6V 70 µA
CL = 50pF;
VCC = 3.3V
DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product
designed for V
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When enable (E) input is High, the
Q outputs follow the data (D) inputs. When enable is taken Low, the
Q outputs are latched at the levels of the D inputs one setup time
prior to the High-to-Low transition.
CONDITIONS
T
amb
operation at 3.3V .
CC
= 25°C
TYPICAL UNIT
1.9 ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVT16373A DL VT16373A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVT16373A DGG VT16373A DGG SOT362-1
LOGIC SYMBOL
1
1D0 1D1 1D2 1D3
1LE
1OE
1Q0 1Q1 1Q2651Q3
2LE
2OE
2Q0 2Q1 2Q2 2Q3
48
25
24
47 46 44 43
32
36 35 33 32
2D02D21 2D2 2D3
41 40 38 37
1D4 1D5 1D6 1D7
1Q4 1Q5 1Q6
30 29 27 26
2D4 2D5 2D6 2D7
2Q4 2Q5 2Q6 2Q7
1Q7
98
1211
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
1, 24 1OE, 2OE
48, 25 1E, 2E
4, 10, 15, 21, 28, 34, 39, 45 GND Ground (0V)
7, 18, 31, 42 V
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
CC
Data inputs
Data outputs
Output enable
inputs
(active-Low)
Enable inputs
(active-High)
Positive
supply voltage
1413 1716
1998 Feb 19 853-1780 18989
2019 2322
SA00044
2
Philips Semiconductors Product specification
74LVT16373A3.3V 16-bit transparent D-type latch (3-State)
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
4D
1 ∇
2 ∇
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
11
1Q7
12
1Q8
13
2Q1
14
2Q2
16
2Q3
17
2Q4
19
2Q5
20
2Q6
22
2Q7
23
2Q8
SW00010
PIN CONFIGURATION
1
1OE
2
1Q0
1Q1
3
GND
4
1Q2
5
1Q3
6
7
V
CC
8
1Q4
1Q5
9
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
16
2Q2
2Q3
17
18
V
CC
2Q4
19
20
2Q5
21
GND
22
2Q6
23
2Q7
24
2OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SA00043
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
CC
2D4
2D5
GND
2D6
2D7
2LE
LOGIC DIAGRAM
nD0
nLE
nOE
D
E Q
nQ0
nD1
nD2
D
EQ
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
D
EQ
nD3
D
EQ
nD4
D
EQ
nD5
D
EQ
nD6
D
EQ
nD7
D
EQ
SA00046
1998 Feb 19
3
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