Philips 74LVT162374 Datasheet
INTEGRATED CIRCUITS
74LVT162374
3.3V LVT 16-bit edge-triggered D-type
flip-flop with 30 Ω termination resistors
(3-State)
Product specification
IC23 Data Handbook
1999 Sep 23
Philips Semiconductors Product specification
3.3V 16-bit edge-triggered D-type flip-flop
with 30 Ω termination resistors (3-State)
FEA TURES
•16-bit edge-triggered flip-flop
•3-State buffers
•Output capability: +12 mA / -12 mA
•TTL input and output switching levels
•Input and output interface capability to systems at 5 V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•Outputs include series resistance of 30 Ω making external
resistors unnecessary
•Power-up reset
•Power-up 3-State
•No bus current loading when output is tied to 5 V bus
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
74L VT162374
DESCRIPTION
The 74LVT162374 is a high-performance BiCMOS product designed
for V
operation at 3.3 V .
CC
The 74LVT162374 is designed with 30 Ω series resistance in both
the High and Low states of the output. This design reduces line
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
This device is a 16-bit edge-triggered D-type flip-flop featuring
non-inverting 3-State outputs. The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CP), the Q outputs of the flip-flop take on the logic levels set up at
the D inputs.
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
nCP to nQx
Input capacitance VI = 0V or 3.0V 3 pF
Output pin capacitance Outputs disabled; VO = 0V or 3.0V 9 pF
Total supply current Outputs disabled; VCC = 3.6V 70 µA
CL = 50pF;
VCC = 3.3V
CONDITIONS
T
= 25°C
amb
TYPICAL UNIT
2.9 ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDERING CODE DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVT162374 DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVT162374 DGG SOT362-1
1999 Sep 23 853-2173 22407
2
Philips Semiconductors Product specification
3.3V 16-bit edge-triggered D-type flip-flop with
30 Ω termination resistors (3-State)
LOGIC SYMBOL
47 46 44 43
1
1D0 1D1 1D2 1D3
1CP
1OE
1Q0 1Q1 1Q2651Q3
32
36 35 33 32
2D02D21 2D2 2D3
2CP
2OE
2Q0 2Q1 2Q2 2Q3
1413 1716
48
25
24
LOGIC SYMBOL (IEEE/IEC)
1OE
1CP
2OE
2CP
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C1
2EN
C2
1D
2D
41 40 38 37
1D4 1D5 1D6 1D7
1Q4 1Q5 1Q6
30 29 27 26
2D4 2D5 2D6 2D7
2Q4 2Q5 2Q6 2Q7
98
2019 2322
1 ∇
2 ∇
1Q7
1211
SW00018
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
11
1Q7
12
1Q8
13
2Q1
14
2Q2
16
2Q3
17
2Q4
19
2Q5
20
2Q6
22
2Q7
23
2Q8
SW00016
PIN CONFIGURATION
PIN DESCRIPTION
74LVT162374
1
1OE
1Q0
2
!Q1
3
GND
4
1Q2
5
1Q3
6
V
7
CC
1Q4
8
1Q5
9
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
2Q2
16
2Q3
17
V
18
CC
2Q4
19
2Q5
20
GND
21
2Q6
22
2Q7
23
2OE
24
SW00017
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41, 40,
38, 37 36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20,
22, 23
1D0 - 1D7
2D0 - 2D7
1Q0 - 1Q7
2Q0 - 2Q7
1, 24 1OE, 2OE
48, 25 1CP, 2CP
4, 10, 15, 21, 28, 34,
39, 45
7, 18, 31, 42 V
GND Ground (0V)
CC
1CP
48
1D0
47
1D1
46
GND
45
1D2
44
1D3
43
V
42
CC
1D4
41
1D5
40
GND
39
1D6
38
1D7
37
2D0
36
2D1
35
GND
34
2D2
33
2D3
32
V
31
CC
2D4
30
2D5
29
GND
28
2D6
27
2D7
26
2CP
25
Data inputs
Data outputs
Output enable inputs
(active-Low)
Clock pulse inputs (active
rising edge)
Positive supply voltage
1999 Sep 23
3
Philips Semiconductors Product specification
OPERATING MODE
3.3V 16-bit edge-triggered D-type flip-flop with
30 Ω termination resistors (3-State)
LOGIC DIAGRAM
nD0
D
CP Q
nCP
nOE
nD1
D
CP Q
nQ0
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS
nOE nCP nDx REGISTER nQ0 - nQ7
L
L
L ↑ X NC NC Hold
H
H
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= Not a Low-to-High clock transition
↑
↑
↑
↑
↑
l
h
X
nDx
nD2
D
CP Q
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
nDx
H
NC
nD3
D
CP Q
L
nD4
D
CP Q
L
H
Z
Z
nD5
D
CP Q
nD6
Load and read register
Disable outputs
74LVT162374
nD7
D
CP Q
D
CP Q
SW00019
SCHEMATIC OF EACH OUTPUT
V
CC
1999 Sep 23
27 Ω
OUTPUT
27 Ω
SW00503
4
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