Philips 74LVT162373 Datasheet
INTEGRATED CIRCUITS
74LVT162373
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
Product specification
IC23 Data Handbook
1999 Sep 23
Philips Semiconductors Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
FEA TURES
•16-bit transparent latch
•3-State buffers
•Output capability: +12 mA / –12 mA
•TTL input and output switching levels
•Input and output interface capability to systems at 5 V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•Outputs include series resistance of 30 Ω making external
resistors unnecessary
•Power-up reset
•Power-up 3-State
•No bus current loading when output is tied to 5 V bus
•Latch-up protection exceeds 500 mA per JEDEC Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
74L VT162373
DESCRIPTION
The 74LVT162373 is a high-performance BiCMOS product designed
for V
operation at 3.3 V .
CC
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When Latch Enable (LE) input is
High, the Q outputs follow the data (D) inputs. When Latch Enable is
taken Low, the Q outputs are latched at the levels of the D inputs
one setup time prior to the High-to-Low transition.
The 74LVT162373 is designed with 30 Ω series resistance in both
the High and Low states of the output. This design reduces the
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
nDx to nQx
Input capacitance VI = 0 V or 3.0 V 3 pF
Output capacitance Outputs disabled; VO = 0 V or 3.0 V 9 pF
Total supply current Outputs disabled; VCC = 3.6 V 70 µA
CL = 50 pF;
VCC = 3.3 V
CONDITIONS
T
= 25 °C
amb
TYPICAL UNIT
3.0 ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDERING CODE DWG NUMBER
48-Pin Plastic SSOP Type III –40 °C to +85 °C 74LVT162373 DL SOT370-1
48-Pin Plastic TSSOP Type II –40 °C to +85 °C 74LVT162373 DGG SOT362-1
1999 Sep 23 853-2172 22406
2
Philips Semiconductors Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
PIN CONFIGURATION
1
1OE
2
1Q0
1Q1
3
GND
4
1Q2
5
1Q3
6
7
V
CC
8
1Q4
1Q5
9
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
16
2Q2
2Q3
17
18
V
CC
2Q4
19
20
2Q5
21
GND
22
2Q6
23
2Q7
24
2OE
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41,
40, 38, 37, 36, 35,
33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11,
12, 13, 14, 16, 17,
19, 20, 22, 23
1, 24 1OE, 2OE
48, 25 1LE, 2LE
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
GND Ground (0V)
CC
48
1LE
47
1D0
1D1
46
GND
45
1D2
44
43
1D3
42
V
CC
41
1D4
1D5
40
GND
39
1D6
38
1D7
37
2D0
36
2D1
35
GND
34
33
2D2
2D3
32
31
V
CC
2D4
30
29
2D5
28
GND
27
2D6
26
2D7
25
2LE
SA00043
Data inputs
Data outputs
Output Enable inputs
(active-Low)
Latch Enable inputs
(active-High)
Positive supply voltage
LOGIC SYMBOL
47 46 44 43
1
1D0 1D1 1D2 1D3
1LE
1OE
1Q0 1Q1 1Q2651Q3
32
36 35 33 32
2D02D21 2D2 2D3
2LE
2OE
2Q0 2Q1 2Q2 2Q3
1413 1716
48
25
24
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
4D
74LVT162373
41 40 38 37
1D4 1D5 1D6 1D7
1Q4 1Q5 1Q6
30 29 27 26
2D4 2D5 2D6 2D7
2Q4 2Q5 2Q6 2Q7
98
2019 2322
1 ∇
2 ∇
1Q7
1211
SA00044
11
12
13
14
16
17
19
20
22
23
SW00010
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1999 Sep 23
3
Philips Semiconductors Product specification
OPERATING MODE
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
LOGIC DIAGRAM
nD0
D
E Q
nLE
nOE
FUNCTION TABLE
INPUTS
nOE nLE nDx
L
L
L
L
L L X NC NC Hold
H
H
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low LE transition
H
H
↓
↓
L
H
nQ0
nD1
nDx
D
EQ
L
H
l
h
X
nD2
D
EQ
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
INTERNAL
REGISTER
L
H
L
H
NC
nDx
nD3
D
EQ
OUTPUTS
nQ0 – nQ7
L
H
L
H
Z
Z
nD4
D
EQ
nD5
Enable and read register
Latch and read register
Disable outputs
D
EQ
74LVT162373
nD6
D
EQ
nD7
D
EQ
SA00046
SCHEMATIC OF EACH OUTPUT
V
CC
1999 Sep 23
27 Ω
OUTPUT
27 Ω
SW00503
4
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