Philips 74LVCH32373A Datasheet

INTEGRATED CIRCUITS

DATA SH EET

74LVCH32373A

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

Product specification
File under Integrated Circuits, IC24

1999 Nov 24

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

FEATURES

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• MULTIBYTE flow-trough standardpin-out architecture

• Low inductance multiple power and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• Bus hold on data inputs

• Typical output ground bounce voltage:

V

<0.8VatVCC= 3.3 V and T

OLP

• Typical output undershoot voltage:
V

>2VatVCC= 3.3 V and T

OHV

• Power off disables outputs, permitting live insertion

• Packaged in plastic fine-pitch ball grid array package.

DESCRIPTION

The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.

amb

amb

=25°C

=25°C

74LVCH32373A

The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latchand 3-state
outputs for bus oriented applications. One latch enable
(nLE) input and one output enable (nOE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices.

The74LVCH32373A consists of 4 sectionsof eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nDn inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.

When input nLE is LOW the latches store the information
thatwas present at theD-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.

The 74LVCH32373A bus hold data input circuitseliminate
the need for external pull-up resistors to hold unused
inputs.

The inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed

3.3 or 5 V environment.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤2.5 ns.

amb

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

C

I

C

PD

propagation delay

nD

to nQ

n

nLE to nQ

n

n

CL= 50 pF; VCC= 3.3 V 3.0 ns

CL= 50 pF; VCC= 3.3 V 3.4 ns
input capacitance 5.0 pF
power dissipation capacitance

VI= GND to VCC; note 1 26 pF
per buffer

Note

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

= input frequency in MHz;

f

i

2

× fi+ Σ (CL× V

CC

2

× fo) where:

CC

fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts;
Σ (CL× V

2

× fo) = sum of the outputs.

CC

1999 Nov 24 2

Philips Semiconductors Product specification

32-bit transparent D-type latch with

74LVCH32373A

5 V tolerant inputs/outputs; 3-state

FUNCTION TABLE

See note 1.

OPERATING MODE

Enable and read register
(transparent mode)

Latch and read register L L l L L

Latch register and disable
outputs

Note

1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.

OE nLE nD

n

LHLLL
LHHHH

LLhHH
HL l LZ
HLhHZ

INPUTS

n

INTERNAL

LATCHES

OUTPUTS

nQ

n

ORDERING INFORMATION

TYPE NUMBER

74LVCH32373AEC −40 to +85 °C 96 LFBGA96 plastic SOT536-1

PINNING

SYMBOL DESCRIPTION

nD

n

nLE latch enable inputs (active HIGH)
nQ

n

GND ground (0 V)

n

OE output enable inputs (active LOW)

V

CC

TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE

data inputs

data outputs

DC supply voltage

PACKAGE

1999 Nov 24 3

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

handbook, full pagewidth

6

1D11D31D51D72D12D32D52D73D13D33D53D74D14D34D54D

5

1D01D21D41D62D02D22D42D63D03D23D43D64D04D24D44D

1LE 2LE 3LEGND GND GND GND 4LEV

4

1OE

3 2OE 3OEGND GND GND GND 4OEV

1Q01Q21Q41Q62Q02Q22Q42Q63Q03Q23Q43Q64Q04Q24Q44Q

2

1Q11Q31Q51Q72Q12Q32Q52Q73Q13Q33Q53Q74Q14Q34Q54Q

1

AHJBDEG TCF KMNRLP

CC

CC

V

CC

V

CC

Fig.1 Pin configuration.

GND GND GND GNDV

GND GND GND GNDV

CC

CC

74LVCH32373A

MNA492

6

7

V

CC

V

CC

7

6

handbook, full pagewidth

1D

1LE

1OE

3D

3LE

3OE

0

0

DQ

LATCH 1

LE LE

to 7 other channels

DQ

LATCH 17

LE LE

to 7 other channels

1Q

3Q

2D

2LE

2OE

4D

4LE

4OE

0

0

0

0

DQ

LATCH 9

LE LE

to 7 other channels

DQ

LATCH 25

LE LE

to 7 other channels

2Q

0

4Q

0

MNA493

Fig.2 Logic symbol.Fig.2 Logic symbol.

1999 Nov 24 4

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

data

input

V

CC

handbook, halfpage

74LVCH32373A

to internal circuit

MNA473

Fig.3 Bus hold circuit.

1999 Nov 24 5