Philips 74LVCH244AD, 74LVCH244ADB, 74LVC244ADB, 74LVC244AD, 74LVCH244APW Datasheet
INTEGRATED CIRCUITS
74LVC244A/74LVCH244A
Octal buffer/line driver with 5-volt tolerant
inputs/outputs (3-State)title
Product specification
Supersedes data of 1996 Sep 06
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
t
1A
1Y
V
3V
3.5
ns
Octal buffer/line driver with 5-volt
tolerant inputs/outputs (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when V
•Bushold on all data inputs (74LVCH244A only)
CC
= 0V
DESCRIPTION
The 74LVC244A/74LVCH244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. These features allow the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC244A/74LVCH244A is an octal non-inverting buffer/line
driver with 3-State outputs. The 3-State outputs are controlled by the
output enable inputs 1OE
outputs to assume a high impedance OFF-state. Schmitt-trigger
action at all inputs makes the circuit highly tolerant for slower input
rise and fall times.
The ’244’ is functionally identical to the ’240’, but the ’240’ has
non-inverting outputs.
and 2OE. A HIGH on nOE causes the
74L VC244A
74L VCH244A
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
to
n
PHL/tPLH
C
I
C
PD
NOTE:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
= CPD x V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
2. The condition is V
CC
2
x V
x fo) = sum of outputs.
CC
2An to 2Y
Input capacitance 4.4 pF
Power dissipation capacitance per
buffer
2
x fi + (CL x V
= GND to V
I
n;
n
CC
CC
2
x fo) where:
CL = 50pF
= 3.
CC
Notes 1 and 2 22.6 pF
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC244A D 74LVC244A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC244A DB 74LVC244A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC244A PW 7LVC244APW DH SOT360-1
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVCH244A D 74LVCH244A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVCH244A DB 74LVCH244A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVCH244A PW LVCH244APW DH SOT360-1
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
NORTH AMERICA PKG. DWG. #
1998 May 20 853-1876 19419
2
Philips Semiconductors Product specification
Octal buffer/line driver with 5-volt
tolerant inputs/outputs (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 1OE Output enable input (active LOW)
2, 4, 6, 8 1A0 to 1A‘3Data inputs
3, 5, 7, 9 2Y0 to 2Y3Bus outputs
10 GND Ground (0V)
17, 15, 13, 11 2A0 to 2A3Bus inputs
18, 16, 14, 12 1Y0 to 1Y3Bus outputs
19 2OE Output enable input (active-LOW)
20 V
CC
PIN CONFIGURATION
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3 1Y3
GND
Positive supply voltage
1
2
3
4
5
6
7
8
9
10 11
SV00212
20
V
CC
2OE
19
1Y0
18
2A0
17
1Y1
16
2A1
15
1Y2
14
2A2
13
12
2A3
FUNCTION TABLE
INPUTS OUTPUT
nOE nA
n
L L L
L H H
H X Z
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance OFF-state
LOGIC SYMBOL
1A
1A
1A
1A
1OE
2
0
4
1
6
2
8
3
1
18
1Y
0
16
1Y
1
14
1Y
2
12
1Y
3
FUNCTIONAL DIAGRAM
1A
0
2
74LVC244A
74LVCH244A
nY
n
17
2A
0
15
2A
1
13
2A
2
11
2A
3
19
2OE
1Y
18
0
3
2Y
5
2Y
7
2Y
9
2Y
SV00210
o
1
2
3
LOGIC SYMBOL (IEEE/IEC)
1
EN
2
4
6
8
19
EN
11 9
13 7
15 5
17 3
1998 May 20
18
16
14
12
SV00209
1A
1
4
1A
2
6
1A
3
8
1OE
1
2A
0
17
2A
1
15
2A
2
13
2A
3
11
2OE
19
1Y
1
1Y
2
1Y
3
2Y
o
2Y
1
2Y
2
2Y
3
SV00211
16
14
12
3
5
7
9
3
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