INTEGRATED CIRCUITS
74LVC244A/74LVCH244A
Octal buffer/line driver with 5-volt tolerant inputs/outputs (3-State)title
Product specification |
1998 May 20 |
Supersedes data of 1996 Sep 06
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal buffer/line driver with 5-volt |
74LVC244A |
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tolerant inputs/outputs (3-State) |
74LVCH244A |
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FEATURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when VCC = 0V
•Bushold on all data inputs (74LVCH244A only)
DESCRIPTION
The 74LVC244A/74LVCH244A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC244A/74LVCH244A is an octal non-inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the
output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times.
The '244' is functionally identical to the '240', but the '240' has non-inverting outputs.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
CL = 50pF |
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tPHL/tPLH |
1An to 1Yn; |
VCC = 3.3V |
3.5 |
ns |
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2An to 2Yn |
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CI |
Input capacitance |
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4.4 |
pF |
CPD |
Power dissipation capacitance per |
Notes 1 and 2 |
22.6 |
pF |
buffer |
NOTE:
1.CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL x VCC2 x fo) = sum of outputs.
2.The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES |
TEMPERATURE |
OUTSIDE |
NORTH AMERICA |
PKG. DWG. # |
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RANGE |
NORTH AMERICA |
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20-Pin Plastic Shrink Small Outline (SO) |
±40°C to +85°C |
74LVC244A D |
74LVC244A D |
SOT163-1 |
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20-Pin Plastic Shrink Small Outline (SSOP) Type II |
±40°C to +85°C |
74LVC244A DB |
74LVC244A DB |
SOT339-1 |
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20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I |
±40°C to +85°C |
74LVC244A PW |
7LVC244APW DH |
SOT360-1 |
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20-Pin Plastic Shrink Small Outline (SO) |
±40°C to +85°C |
74LVCH244A D |
74LVCH244A D |
SOT163-1 |
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20-Pin Plastic Shrink Small Outline (SSOP) Type II |
±40°C to +85°C |
74LVCH244A DB |
74LVCH244A DB |
SOT339-1 |
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20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I |
±40°C to +85°C |
74LVCH244A PW |
LVCH244APW DH |
SOT360-1 |
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1998 May 20 |
2 |
853-1876 19419 |
Philips Semiconductors |
Product specification |
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Octal buffer/line driver with 5-volt |
74LVC244A |
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tolerant inputs/outputs (3-State) |
74LVCH244A |
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PIN DESCRIPTION
PIN NUMBER |
SYMBOL |
FUNCTION |
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1 |
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Output enable input (active LOW) |
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1OE |
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2, 4, 6, 8 |
1A0 to 1A`3 |
Data inputs |
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3, 5, 7, 9 |
2Y0 to 2Y3 |
Bus outputs |
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10 |
GND |
Ground (0V) |
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17, 15, 13, 11 |
2A0 to 2A3 |
Bus inputs |
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18, 16, 14, 12 |
1Y0 to 1Y3 |
Bus outputs |
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19 |
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Output enable input (active-LOW) |
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2OE |
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20 |
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VCC |
Positive supply voltage |
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FUNCTION TABLE
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INPUTS |
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OUTPUT |
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nOE |
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nAn |
nYn |
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L |
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L |
L |
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L |
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H |
H |
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H |
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X |
Z |
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H |
= HIGH voltage level |
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L |
= LOW voltage level |
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X |
= Don't care |
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Z = High impedance OFF-state
PIN CONFIGURATION
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20 |
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1OE |
1 |
VCC |
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1A0 |
2 |
19 |
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2OE |
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2Y0 |
3 |
18 |
1Y0 |
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1A1 |
4 |
17 |
2A0 |
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2Y1 |
5 |
16 |
1Y1 |
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1A2 |
6 |
15 |
2A1 |
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2Y2 |
7 |
14 |
1Y2 |
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1A3 |
8 |
13 |
2A2 |
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2Y3 |
9 |
12 |
1Y3 |
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GND |
10 |
11 |
2A3 |
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SV00212 |
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LOGIC SYMBOL (IEEE/IEC)
1
EN
2 |
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18 |
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4 |
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16 |
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6 |
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14 |
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8 |
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12 |
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19 |
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EN |
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11 |
9 |
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13 |
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7 |
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15 |
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5 |
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17 |
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3 |
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LOGIC SYMBOL
2 |
18 |
1Y0 |
17 |
3 |
1A0 |
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2A0 |
2Yo |
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4 |
16 |
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15 |
5 |
1A1 |
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1Y1 |
2A1 |
2Y1 |
6 |
14 |
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13 |
7 |
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1Y2 |
2A2 |
2Y2 |
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1A2 |
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8 |
12 |
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11 |
9 |
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1Y3 |
2A3 |
2Y3 |
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1A3 |
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1OE 1 |
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19 |
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2OE |
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SV00210
FUNCTIONAL DIAGRAM
2 |
1A0 |
1Y0 |
18 |
4 |
1A1 |
1Y1 |
16 |
6 |
1A2 |
1Y2 |
14 |
8 |
1A3 |
1Y3 |
12 |
1 |
1OE |
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17 |
2A0 |
2Yo |
3 |
15 |
2A1 |
2Y1 |
5 |
13 |
2A2 |
2Y2 |
7 |
11 |
2A3 |
2Y3 |
9 |
19 |
2OE |
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SV00211 |
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SV00209
1998 May 20 |
3 |
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