Philips 74LVCH16374ADL, 74LVCH16374ADGG, 74LVC16374ADL, 74LVC16374ADGG Datasheet

INTEGRATED CIRCUITS

74LVC16374A/74LVCH16374A

16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)

Product specification

1998 Mar 17

Supersedes data of 1997 Aug 22

IC24 Data Handbook

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Philips Semiconductors	Product specification
16-bit edge triggered D-type flip-flop with 5 Volt	74LVC16374A/
tolerant inputs/outputs (3-State)	74LVCH16374A

FEATURES

•5 volt tolerant inputs/outputs for interfacing with 5V logic

•Wide supply voltage range of 1.2 V to 3.6 V

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•MULTIBYTETM flow-through standard pin-out architecture

•Low inductance multiple power and ground pins for minimum noise and ground bounce

•Direct interface with TTL levels

•All data inputs have bus hold (74LVCH16374A only)

•High impedance when VCC = 0

DESCRIPTION

The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed

3.3V/5V environment.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

The 74LVCH16374A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.

PIN CONFIGURATION

1OE				1				48	1CP
1Q0				2				47	1D0
1Q1				3				46	1D1
GND				4				45	GND
1Q2				5				44	1D2
1Q3				6				43	1D3
VCC				7				42	VCC
1Q4				8				41	1D4
1Q5				9				40	1D5
GND				10				39	GND
1Q6				11				38	1D6
1Q7				12				37	1D7
2Q0				13				36	2D0
2Q1				14				35	2D1
GND				15				34	GND
2Q2				16				33	2D2
2Q3				17				32	2D3
VCC				18				31	VCC
2Q4				19				30	2D4
2Q5				20				29	2D5
GND				21				28	GND
2Q6				22				27	2D6
2Q7				23				26	2D7
2OE				24				25	2CP
							SW00074

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	tPHL/tPLH	Propagation delay	CL = 50pF	3.8	ns
		Cp to Qn	VCC = 3.3V
	fMAX	Maximum clock frequency		150	MHz
	CI	Input capacitance		5.0	pF
	CPD	Power dissipation capacitance per flip-flop	VCC = 3.3V1	30	pF

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;(CL × VCC2 × fo) = sum of outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
48-Pin Plastic SSOP Type III	±40°C to +85°C	74LVC16374A DL	VC16374A DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74LVC16374A DGG	VC16374A DGG	SOT362-1
48-Pin Plastic SSOP Type III	±40°C to +85°C	74LVCH16374A DL	VCH16374A DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74LVCH16374A DGG	VCH16374A DGG	SOT362-1

1998 Mar 17

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853-2028 19111

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt																	74LVC16374A/
tolerant inputs/outputs (3-State)																74LVCH16374A
PIN DESCRIPTION						LOGIC SYMBOL
PIN NUMBER	SYMBOL			NAME AND FUNCTION						1				24
				Output enable input
1	1OE
				(active LOW)
						47				1OE				2OE					2
2, 3, 5, 6, 8, 9,	1Q0 to 1Q7			3-State flip-flop outputs						1D0							1Q0
11, 12						46				1D1							1Q1			3
						44				1D2							1Q2			5
4, 10, 15, 21,	GND			Ground (0V)
28, 34, 39, 45						43				1D3							1Q3			6
						41				1D4							1Q4			8
7, 18, 31, 42	VCC			Positive supply voltage
						40				1D5							1Q5			9
13, 14, 16, 17,	2Q0 to 2Q7			3-State flip-flop outputs
						38				1D6							1Q6			11
19, 20, 22, 23
						37				1D7							1Q7			12
				Output enable input
24	2OE					36				2D0							2Q0			13
				(active LOW)
						35				2D1							2Q1			14
25	2CP			Clock input		33				2D2							2Q2			16
						32				2D3							2Q3			17
36, 35, 33, 32,	2D0 to 2D7			Data inputs
30, 29, 27, 26						30				2D4							2Q4			19
						29				2D5							2Q5			20
47, 46, 44, 43,	1D0 to 1D7			Data inputs
41, 40, 38, 37						27				2D6							2Q6			22
						26				2D7							2Q7			23
48	1CP			Clock input
										1CP				2CP
										48				25
																		SW00075

LOGIC DIAGRAM

1D0	D	Q	1Q0	2D0
	CP
	FF1
1CP				2CP
1OE				2OE

D	Q	2Q0
CP
FF9

TO 7 OTHER CHANNELS	TO 7 OTHER CHANNELS
	SW00076

FUNCTION TABLE

OPERATING MODES				INPUTS		INTERNAL	OUTPUTS
						FLIP-FLOPS
	nOE			nCP	nDx		Q0 to Q7
Load and read register		L			l	L	L
		L			h	H	H
Load register and disable outputs		H			l	L	Z
		H			h	H	Z

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state

= LOW-to-HIGH CP transition

1998 Mar 17

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