Philips 74LVCH16374ADL, 74LVCH16374ADGG, 74LVC16374ADL, 74LVC16374ADGG Datasheet
INTEGRATED CIRCUITS
74LVC16374A/74LVCH16374A
16-bit edge triggered D-type flip-flop with
5 Volt tolerant inputs/outputs (3-State)
Product specification
Supersedes data of 1997 Aug 22
IC24 Data Handbook
1998 Mar 17
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
FEA TURES
•5 volt tolerant inputs/outputs for interfacing with 5V logic
•Wide supply voltage range of 1.2 V to 3.6 V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTE
TM
flow-through standard pin-out architecture
•Low inductance multiple power and ground pins for minimum
noise and ground bounce
•Direct interface with TTL levels
•All data inputs have bus hold (74LVCH16374A only)
•High impedance when V
DESCRIPTION
The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. The 74LVC16374A consists of 2 sections of
eight positive edge-triggered flip-flops. A clock (CP) input and an
output enable (OE
from either 3.3V or 5V devices. In 3-State operation, outputs can
handle 5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The flip-flops will store the state of their individual D-inputs that meet
the set-up and hold time requirements on the LOW-to-HIGH CP
transition.
When OE
is LOW, the contents of the flip-flops are available at the
outputs. When OE
OFF-state. Operation of the OE
flip-flops.
The 74LVCH16374A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
) are provided for each octal. Inputs can be driven
is HIGH, the outputs go to the high impedance
= 0
CC
input does not affect the state of the
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
2Q4
2Q5
GND
2Q6
2Q7
2OE
74L VC16374A/
74L VCH16374A
48
1
2
3
4
5
6
7
CC
8
9
10
11
12
13
14
15
16
17
18
CC
19
20
21
22
23
24
SW00074
1CP
47
1D0
46
1D1
45
GND
44
1D2
43
1D3
42
V
CC
41
1D4
40
1D5
39
GND
38
1D6
37
1D7
36
2D0
35
2D1
34
GND
33
2D2
32
2D3
31
V
CC
30
2D4
29
2D5
28
GND
27
2D6
26
2D7
25
2CP
QUICK REFERENCE DA TA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
MAX
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
= CPD × V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
= 25°C; tr = tf ≤ 2.5 ns
amb
Propagation delay
Cp to Qn
Maximum clock frequency 150 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per flip-flop VCC = 3.3V
CC
2
× V
L
× fo) = sum of outputs.
CC
2
× fi + (CL × V
PARAMETER CONDITIONS TYPICAL UNIT
2
× fo) where:
CC
CL = 50pF
VCC = 3.3V
1
3.8 ns
30 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVC16374A DL VC16374A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVC16374A DGG VC16374A DGG SOT362-1
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVCH16374A DL VCH16374A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVCH16374A DGG VCH16374A DGG SOT362-1
1998 Mar 17 853-2028 19111
2
Philips Semiconductors Product specification
OPERATING MODES
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1OE
2, 3, 5, 6, 8, 9,
11, 12
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
13, 14, 16, 17,
19, 20, 22, 23
1Q0 to 1Q7 3-State flip-flop outputs
GND Ground (0V)
CC
2Q0 to 2Q7 3-State flip-flop outputs
24 2OE
25 2CP Clock input
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
2D0 to 2D7 Data inputs
1D0 to 1D7 Data inputs
48 1CP Clock input
Output enable input
(active LOW)
Positive supply voltage
Output enable input
(active LOW)
LOGIC SYMBOL
74LVC16374A/
74LVCH16374A
241
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1OE 2OE
1CP 2CP
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
LOGIC DIAGRAM
1D0
1CP
1OE
DQ
CP
FF1
TO 7 OTHER CHANNELS
1Q0
FUNCTION TABLE
INPUTS
nOE nCP nDx
Load and read register
Load register and disable outputs
L
L
H
H
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high impedance OFF-state
= LOW-to-HIGH CP transition
2D0
2CP
2OE
48 25
DQ
CP
FF9
TO 7 OTHER CHANNELS
SW00076
l
h
l
h
2Q0
INTERNAL
FLIP-FLOPS
L
H
L
H
SW00075
OUTPUTS
Q0 to Q7
L
H
Z
Z
1998 Mar 17
3
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