Philips 74LVCH16373ADL, 74LVCH16373ADGG, 74LVC16373ADL, 74LVC16373ADGG Datasheet

INTEGRATED CIRCUITS

74LVC16373A/74LVCH16373A

16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State)

Product specification

1998 Mar 17

Supersedes data of 1997 Aug 22

IC24 Data Handbook

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Philips Semiconductors	Product specification
16-bit D-type transparent latch with 5 Volt tolerant	74LVC16373A/
inputs/outputs (3-State)	74LVCH16373A

FEATURES

•5 volt tolerant inputs/outputs for interfacing with 5V logic

•Wide supply voltage range of 1.2V to 3.6V

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•MULTIBYTETM flow-through standard pin-out architecture

•Low inductance multiple power and ground pins for minimum noise and ground bounce

•Direct interface with TTL levels

•All data inputs have bus hold (74LVCH167373A only)

•High impedance when VCC = 0

DESCRIPTION

The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. One latch enable (LE) input and one output

enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed

3.3V/5V environment.

The 74LVC(H)16373A consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are

available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The 74LVCH16373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.

PIN CONFIGURATION

									1LE
1OE				1				48
1Q0
				2				47	1D0
1Q1
				3				46	1D1
GND				4				45	GND
1Q2
				5				44	1D2
1Q3				6				43	1D3
VCC				7				42	VCC
1Q4				8				41	1D4
1Q5				9				40	1D5
GND				10				39	GND
1Q6				11				38	1D6
1Q7				12				37	1D7
2Q0				13				36	2D0
2Q1				14				35	2D1
GND				15				34	GND
2Q2				16				33	2D2
2Q3				17				32	2D3
VCC				18				31	VCC
2Q4				19				30	2D4
2Q5				20				29	2D5
GND				21				28	GND
2Q6				22				27	2D6
2Q7				23				26	2D7
2OE				24				25	2LE
							SW00066

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
		Propagation delay	CL = 50pF
	tPHL/tPLH	Dn to Qn		3.0	ns
			VCC = 3.3V
		LE to Qn		3.4
	CI	Input capacitance		5.0	pF
	CPD	Power dissipation capacitance per latch	VCC = 3.3V	26	pF

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;(CL × VCC2 × fo) = sum of outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
48-Pin Plastic SSOP Type III	±40°C to +85°C	74LVC16373A DL	VC16373A DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74LVC16373A DGG	VC16373A DGG	SOT362-1
48-Pin Plastic SSOP Type III	±40°C to +85°C	74LVCH16373A DL	VCH16373A DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74LVCH16373A DGG	VCH16373A DGG	SOT362-1

1998 Mar 17

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853-2027 19112

Philips Semiconductors Product specification

	16-bit D-type transparent latch with 5 Volt tolerant																74LVC16373A/
	inputs/outputs (3-State)															74LVCH16373A
	PIN DESCRIPTION						LOGIC SYMBOL
	PIN NUMBER	SYMBOL			NAME AND FUNCTION						1			24
					Output enable input
	1	1OE			(active LOW)
	2, 3, 5, 6, 8, 9,	1Q0 to 1Q7			Data inputs/outputs		47				1OE			2OE					2
											1D0						1Q0
	11, 12
							46				1D1						1Q1			3
	4, 10, 15, 21,	GND			Ground (0V)		44				1D2						1Q2			5
	28, 34, 39, 45
							43				1D3						1Q3			6
	7, 18, 31, 42	VCC			Positive supply voltage
							41				1D4						1Q4			8
	13, 14, 16, 17,	2Q0 to 2Q7			Data inputs/outputs		40				1D5						1Q5			9
	19, 20, 22, 23
							38				1D6						1Q6			11
					Output enable input
	24	2OE					37				1D7						1Q7			12
					(active LOW)
							36				2D0						2Q0			13
	25	2LE			Latch enable input (active
							35				2D1						2Q1			14
					HIGH)
							33				2D2						2Q2			16
	36, 35, 33, 32,	2D0 to 2D7			Data inputs
							32				2D3						2Q3			17
	30, 29, 27, 26
							30				2D4						2Q4			19
	47, 46, 44, 43,	1D0 to 1D7			Data inputs
	41, 40, 38, 37						29				2D5						2Q5			20
							27				2D6						2Q6			22
	48	1LE			Latch enable input (active
					HIGH)		26				2D7						2Q7			23
											1LE			2LE
											48			25
																		SW00067

LOGIC DIAGRAM

1D0	D	Q	1Q0	2D0
	LATCH
		1
	LE	LE
1LE				2LE
1OE				2OE

D Q		2Q0
LATCH
9

LE

LE

TO 7 OTHER CHANNELS

TO 7 OTHER CHANNELS

SW00068

FUNCTION TABLE (per section of eight bits)

	OPERATING MODES				INPUTS		INTERNAL	OUTPUTS
							LATCHES
		OE			LE	Dn		Q0 to Q7
enable and read register			L		H	L	L	L
(transparent mode)			L		H	H	H	H
latch and read register			L		L	l	L	L
			L		L	h	H	H
latch register and disable outputs			H		L	l	L	Z
			H		L	h	H	Z
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L	= LOW voltage level
l	= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X	= don't care

Z = high impedance OFF-state

1998 Mar 17

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