Philips 74LVCH16244ADL, 74LVCH16244ADGG, 74LVC16244ADL, 74LVC16244ADGG Datasheet
INTEGRATED CIRCUITS
74LVC16244A/74LVCH16244A
16-bit buffer/line driver;
5V input/output tolerant (3-State)
Product specification
Supersedes data of 1997 Jun 30
IC24 Data Handbook
1997 Oct 28
Philips Semiconductors Product specification
16-bit buffer/line driver; 5V input/output tolerant
(3-State)
FEA TURES
PIN CONFIGURATION
74L VC16244A/
74L VCH16244A
•5 volt tolerant inputs/outputs for interfacing with 5V logic
48
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
V
4Y0
4Y1
GND
4Y2
4Y3
4OE
1
2
3
4
5
6
7
CC
8
9
10
11
12
13
14
15
16
17
18
CC
19
20
21
22
23
24
SW00194
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTE
TM
flow-through standard pin-out architecture
•Low inductance multiple power and ground pins for minimum
noise and ground bounce
•Direct interface with TTL levels
•All data inputs have bus hold (74LVCH16244A only)
DESCRIPTION
The 74LVC(H)16244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. In 3-State operation, outputs can handle 5V .
These features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC(H)16244A is a 16-bit non-inverting buf fer/line driver with
3-State outputs. The device can be used as four 4-bit buffers, two
8-bit buffers or one 16-bit buffer. The 3-State outputs are controlled
by the output enable inputs 1OE
the outputs to assume a high impedance OFF-state. The device can
be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
The 74LVC(H)16244A is identical to the 74LVC16240A but has
non-inverting outputs.
The 74LVCH16244A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
and 2OE. A HIGH on nOE causes
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVC16244A DL VC16244A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVC16244A DGG VC16244A DGG SOT362-1
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVCH16244A DL VCH16244A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVCH16244A DGG VCH16244A DGG SOT362-1
2OE
47
1A0
46
1A1
45
GND
44
1A2
43
1A3
42
V
CC
41
2A0
40
2A1
39
GND
38
2A2
37
2A3
36
3A0
35
3A1
34
GND
33
3A2
32
3A3
31
V
CC
30
4A0
29
4A1
28
GND
27
4A2
26
4A3
25
3OE
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
P
= CPD × V
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
L
1997 Oct 28 853-1994 18612
= 25°C; tr = tf ≤ 2.5 ns
amb
Propagation delay
1An to 1Yn;
2An to 2Yn
Input capacitance 5.0 pF
Power dissipation capacitance per buffer VI = GND to V
2
× fi + (CL × V
CC
2
× V
× fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
2
× fo) where:
CC
CL = 50pF
VCC = 3.3V
CC
1
3.0 ns
25 pF
2
Philips Semiconductors Product specification
16-bit buffer/line driver; 5V input/output tolerant
(3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1OE
Output enable input
(active LOW)
2, 3, 5, 6 1Y0 to 1Y3 Data outputs
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
GND Ground (0V)
CC
Positive supply voltage
8, 9, 11, 12 2Y0 to 2Y3 Data outputs
13, 14, 16, 17 3Y0 to 3Y3 Data outputs
19, 20, 22, 23 4Y0 to 4Y3 Data outputs
24 4OE
25 3OE
Output enable input
(active LOW)
Output enable input
(active LOW)
30, 29, 27, 26 4A0 to 4A3 Data inputs
36, 35, 33, 32 3A0 to 3A3 Data inputs
41, 40, 38, 37 2A0 to 2A3 Data inputs
47, 46, 44, 43 1A0 to 1A3 Data inputs
48 2OE
Output enable input
(active LOW)
LOGIC SYMBOL
1A0
1A1
1A2
1A3
1OE
2A0
2A1
2A2
47
46
44
43
1
41
40
38
2
1Y0
3
1Y1
5
1Y2
6
1Y3
8
2Y0
9
2Y1
11
2Y2
3A0
3A1
3A2
3A3
3OE
4A0
4A1
4A2
36
35
33
32
25
30
29
27
13
14
16
17
19
20
22
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
FUNCTION TABLE
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
LOGIC SYMBOL (IEEE/IEC)
BUSHOLD CIRCUIT
74LVC16244A/
74LVCH16244A
INPUTS OUTPUT
nOE nAn nYn
L L L
L H H
H X Z
1OE
2OE
3OE
4OE
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1
48
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
2EN
3EN
4EN
1 ∇
1
2 ∇
1
3 ∇
1
4 ∇
1
V
CC
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SW00056
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
37
2A3
48
2OE
1997 Oct 28
12
2Y3
4A3
4OE
26
24
23
4Y3
SW00195
Data Input
To internal circuit
SW00044
3
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