Philips 74LVCH162373ADL, 74LVCH162373ADGG, 74LVC162373ADL, 74LVC162373ADGG Datasheet

INTEGRATED CIRCUITS

DATA SHEET

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch with

30 Ω series termination resistors;

5 V input/output tolerant; 3-state

Product specification			1999 Aug 05
File under Integrated Circuits, IC24

Philips Semiconductors	Product specification
16-bit D-type transparent latch with 30 Ω series	74LVC162373A;
termination resistors; 5 V input/output tolerant; 3-state	74LVCH162373A

FEATURES

·ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

·5 V tolerant input/output for interfacing with 5 V logic

·Wide supply voltage range of 1.2 to 3.6 V

·Complies with JEDEC standard no. 8-1A

·CMOS low power consumption

·MULTIBYTEä flow-through standard pin-out architecture

·Low inductance multiple power and ground pins for minimum noise and ground bounce

·Direct interface with TTL levels

·All data inputs have bus hold (74LVCH162373A only)

·High impedance when VCC = 0

·Power off disables outputs, permitting live insertion.

DESCRIPTION

The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE) are provide for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

The 74LVC(H)162373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state off latches.

The 74LVCH162373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.

The 74LVC(H)162373A is designed with 30 W series termination resistors in both HIGH and LOW output stages to reduce line noise.

FUNCTION TABLE (per section of eight bits)

See note 1.

OPERATION MODES				INPUTS		INTERNAL	OUTPUTS
						LATCHES
		OE		LE	Dn		Q0 to Q7
Enable and read register		L		H	L	L	L
(transparent mode)		L		H	H	H	H
Latch and read register		L		L	l	L	L
		L		L	h	H	H
Latch register and disable outputs		H		L	l	L	Z
		H		L	h	H	Z

Note

1.H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state.

1999 Aug 05

2

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series				74LVC162373A;
termination resistors; 5 V input/output tolerant; 3-state			74LVCH162373A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf £ 2.5 ns.
SYMBOL	PARAMETER	CONDITIONS		TYPICAL	UNIT
tPHL/tPLH	propagation delay	CL = 50 pF; VCC = 3.3 V
	Dn to Qn			3.2	ns
	LE to Qn			3.5	ns
CI	input capacitance			5.0	pF
CPD	power dissipation capacitance per	VCC = 3.3 V; note 1		26.0	pF
	latch

Note

1.CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz; fo = output frequency in MHz;

å (CL ´ VCC2 ´ fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

ORDERING INFORMATION

	OUTSIDE NORTH				PACKAGE
		NORTH AMERICA
			TEMPERATURE
	AMERICA			PINS	PACKAGE	MATERIAL	CODE
			RANGE
	74LVC162373ADL	VC162373A DL	-40 to +85 °C	48	SSOP	plastic	SOT370-1
	74LVC162373ADGG	VC162373A DGG		48	TSSOP	plastic	SOT362-1
	74LVCH162373ADL	VCH162373A DL		48	SSOP	plastic	SOT370-1
	74LVCH162373ADGG	VCH162373A DGG		48	TSSOP	plastic	SOT362-1

PINNING

PIN			SYMBOL	DESCRIPTION
1				output enable input (active LOW)
	1OE
2, 3, 5, 6, 8, 9, 11, 12	1Q0 to 1Q7			data inputs/outputs
4, 10, 15, 21, 28, 34, 39, 45	GND			ground (0 V)
7, 18, 31, 42	VCC			DC supply voltage
13, 14, 16, 17, 19, 20, 22, 23	2Q0 to 2Q7			data inputs/outputs
24				output enable input (active LOW)
	2OE
25	2LE			latch enable input (active HIGH)
36, 35, 33, 32, 30, 29, 27, 26	2D0 to 2D7			data inputs
47, 46, 44, 43, 41, 40, 38, 37	1D0 to 1D7			data inputs
48	1LE			latch enable input (active HIGH)

1999 Aug 05

3

Philips Semiconductors	Product specification
16-bit D-type transparent latch with 30 Ω series	74LVC162373A;
termination resistors; 5 V input/output tolerant; 3-state	74LVCH162373A

handbook, halfpage

1OE			1	48			1LE
1Q0							1D0
			2			47
1Q1							1D1
			3			46
GND							GND
			4			45
1Q2							1D2
			5			44
1Q3							1D3
			6			43
VCC							VCC
			7			42
1Q4							1D4
			8			41
1Q5							1D5
			9			40
							GND
GND			10			39
1Q6							1D6
			11			38
1Q7							1D7
			12			37
2Q0				162373A			2D0
			13			36
2Q1							2D1
			14			35
							GND
GND			15			34
2Q2							2D2
			16			33
2Q3							2D3
			17			32
							VCC
VCC			18			31
2Q4							2D4
			19			30
2Q5							2D5
			20			29
GND							GND
			21			28
2Q6							2D6
			22			27
2Q7							2D7
			23			26
							2LE
2OE			24			25

handbook, halfpage		1				24
		1OE				2OE
47		1D0						1Q0			2
46		1D1						1Q1			3
44		1D2						1Q2			5
43		1D3						1Q3			6
41		1D4						1Q4			8
40		1D5						1Q5			9
38		1D6						1Q6			11
37		1D7						1Q7			12
36		2D0						2Q0			13
35		2D1						2Q1			14
33		2D2						2Q2			16
32		2D3						2Q3			17
30		2D4						2Q4			19
29		2D5						2Q5			20
27		2D6						2Q6			22
26		2D7						2Q7			23
		1LE				2LE
		48				25				MNA425

MNA424

Fig.1 Pin configuration.

Fig.2 Logic symbol.

1999 Aug 05

4

Philips Semiconductors	Product specification
16-bit D-type transparent latch with 30 Ω series	74LVC162373A;
termination resistors; 5 V input/output tolerant; 3-state	74LVCH162373A

1D0	D	Q	1Q0	2D0
	LATCH
		1
	LE	LE
1LE				2LE
1OE				2OE
	to 7 other channels

D	Q	2Q0
LATCH
	9
LE	LE

to 7 other channels

MNA426

Fig.3 Logic diagram.

handbook, halfpage1OE			1	1EN
			48
1LE				C3
			24
				2EN
2OE
			25
2LE				C4
1D0			47					2	1Q0
				3D		1
			46					3
1D1									1Q1
			44					5
1D2									1Q2
			43					6		handbook, halfpage		VCC
1D3									1Q3
			41					8
1D4			40					9	1Q4
1D5			38					11	1Q5	input											to internal circuit
1D6									1Q6
			37					12
1D7									1Q7
			36					13
2D0				4D		2			2Q0									MNA428
			35					14
2D1									2Q1
			33					16
2D2									2Q2
			32					17
2D3									2Q3
			30					19
2D4									2Q4
			29					20
2D5									2Q5
			27					22
2D6									2Q6
			26					23
2D7									2Q7
						MNA427

Fig.4 IEC logic symbol.

Fig.5 Bus hold circuit.

1999 Aug 05

5