Philips 74LVCH162373ADL, 74LVCH162373ADGG, 74LVC162373ADL, 74LVC162373ADGG Datasheet

INTEGRATED CIRCUITS

DATA SH EET

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch with
30 Ω series termination resistors;
5 V input/output tolerant; 3-state

Product specification
File under Integrated Circuits, IC24

1999 Aug 05

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

FEATURES

• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V

• 5 V tolerant input/output for
interfacing with 5 V logic

• Wide supply voltage range of

1.2 to 3.6 V

• Complies with JEDEC standard
no. 8-1A

• CMOS low power consumption

• MULTIBYTE flow-through

standard pin-out architecture

• Lowinductancemultiplepowerand
ground pins for minimum noise and
ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold

(74LVCH162373A only)

• High impedance when VCC=0

• Power off disables outputs,

permitting live insertion.

DESCRIPTION

The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate
D-type inputs for each latch and 3-state outputs for bus oriented applications.
One latch enable (LE) input and one output enable (OE) are provide for each
octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.

The74LVC(H)162373consistsof2sectionsofeightD-typetransparentlatches
with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the
latches. In this condition the latches are transparent, i.e. a latch output will
change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the
D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE isLOW, the contents of the eight latches areavailable at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state off latches.

The74LVCH162373A bus hold data inputs eliminates the need forexternalpull
up resistors to hold unused inputs.

The 74LVC(H)162373A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.

74LVC162373A;

74LVCH162373A

FUNCTION TABLE (per section of eight bits)

See note 1.

OPERATION MODES

Enable and read register
(transparent mode)

Latch and read register

Latch register and disable outputs

Note

1. H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.

OE LE D

LHL L L
LHH H H
LLl L L

LLh H H
HL l L Z
HLh H Z

INPUTS

n

INTERNAL

LATCHES

OUTPUTS

Q0to Q

7

1999 Aug 05 2

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

74LVC162373A;

74LVCH162373A

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤2.5 ns.

amb

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

C

I

C

PD

propagation delay CL= 50 pF; VCC= 3.3 V

D

to Q

n

LE to Q

n

n

3.2 ns

3.5 ns
input capacitance 5.0 pF
power dissipation capacitance per

VCC= 3.3 V; note 1 26.0 pF

latch

Note

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

= input frequency in MHz;

f

i

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fo= output frequency in MHz;
∑ (CL× V

2

× fo) = sum of outputs;

CC

CL= output load capacitance in pF;
VCC= supply voltage in Volts.

ORDERING INFORMATION

PACKAGE

OUTSIDE NORTH

AMERICA

NORTH AMERICA

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74LVC162373ADL VC162373A DL −40 to +85 °C 48 SSOP plastic SOT370-1
74LVC162373ADGG VC162373A DGG 48 TSSOP plastic SOT362-1
74LVCH162373ADL VCH162373A DL 48 SSOP plastic SOT370-1
74LVCH162373ADGG VCH162373A DGG 48 TSSOP plastic SOT362-1

PINNING

PIN SYMBOL DESCRIPTION

11
2, 3, 5, 6, 8, 9, 11, 12 1Q

OE output enable input (active LOW)

to 1Q

0

7

data inputs/outputs
4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V)
7, 18, 31, 42 V
13, 14, 16, 17, 19, 20, 22, 23 2Q
24 2

CC

to 2Q

0

7

OE output enable input (active LOW)

DC supply voltage

data inputs/outputs

25 2LE latch enable input (active HIGH)
36, 35, 33, 32, 30, 29, 27, 26 2D
47, 46, 44, 43, 41, 40, 38, 37 1D

to 2D

0

to 1D

0

7
7

data inputs

data inputs
48 1LE latch enable input (active HIGH)

1999 Aug 05 3

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

handbook, halfpage

1OE

1Q
1Q

GND

1Q
1Q

V

CC

1Q
1Q

GND

1Q
1Q
2Q
2Q

GND

2Q
2Q

V

CC

2Q
2Q

GND

2Q
2Q

2OE

1
2

0

3

1

4
5

2

6

3

7
8

4

9

5

10
11

6

12

7

162373A

13

0

14

1

15
16

2

17

3

18
19

4

20

5

21
22

6

23

7

24

MNA424

1LE

48

1D

47

0

1D

46

1

GND

45

1D

44

2

1D

43

3

V

42

CC

1D

41

4

1D

40

5

GND

39

1D

38

6

1D

37

7

2D

36

0

2D

35

1

GND

34

2D

33

2

2D

32

3

V

31

CC

2D

30

4

2D

29

5

GND

28

2D

27

6

2D

26

7

2LE

25

handbook, halfpage

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

74LVC162373A;

74LVCH162373A

1

24

1OE

2OE

1D

0

1D

1

1D

2

1D

3

1D

4

1D

5

1D

6

1D

7

2D

0

2D

1

2D

2

2D

3

2D

4

2D

5

2D

6

2D

7
1LE 2LE

48 25

1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

2
3
5
6
8

9
11
12
13
14
16
17
19

20

22

23

MNA425

Fig.1 Pin configuration.

1999 Aug 05 4

Fig.2 Logic symbol.

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

handbook, full pagewidth

1D

1LE

1OE

D

0

Q

LATCH

1

LE LE

to 7 other channels

1Q

Fig.3 Logic diagram.

2D

0

0

2LE

2OE

74LVC162373A;

74LVCH162373A

D

Q

LATCH

9

LE LE

to 7 other channels

2Q

MNA426

0

handbook, halfpage

1OE

1LE

2OE

2LE

1D
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D

1

1EN

48

C3

24

2EN

25

C4

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

3D 1

4D 2

MNA427

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

2

1Q

0

3

1Q

1

5

1Q

2

6

1Q

3

8

1Q

4

9

1Q

5

11

1Q

6

12

1Q

7

13

2Q

0

14

2Q

1

16

2Q

2

17

2Q

3

19

2Q

4

20

2Q

5

22

2Q

6

23

2Q

7

handbook, halfpage

input

V

CC

to internal circuit

MNA428

Fig.4 IEC logic symbol.

1999 Aug 05 5

Fig.5 Bus hold circuit.