Philips 74LVC162373A, 74LVCH162373A Technical data

INTEGRATED CIRCUITS

DATA SH EET

74LVC162373A;
74LVCH162373A

16-bit D-type transparent latch;
30 Ω series termination resistors;
5 V tolerant inputs/outputs; 3-state

Product specification
Supersedes data of 1999 Aug 05

2004 Feb 05

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination
resistors; 5 V tolerant inputs/outputs; 3-state

FEATURES

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple power and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• All data inputs have bushold (74LVCH162373A only)

• High-impedance when VCC=0V

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC(H)162373A is a 16-bit D-type transparent
latch featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. One latch
enable (pin nLE) input and one output enable (pin nOE)
are provided for each octal. Inputs can be driven from
either 3.3 or 5 Vdevices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices
in a mixed 3.3 and 5 V environment.

The 74LVC(H)162373A consists of 2 sections of eight
D-typetransparent latches with3-state true outputs.When
pin nLE is HIGH, data at the corresponding data inputs
(pins nDn) enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time
its corresponding data inputs changes.

When pin nLE is LOW the latches store the information
thatwas presentat the datainputs a set-uptime preceding
the HIGH-to-LOW transition of pin nLE. When pin nOE is
LOW, the contents of the eight latchesare available at the
outputs. When pin nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.

74LVC162373A;

74LVCH162373A

The 74LVCH162373A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.

The 74LVC(H)162373A is designed with 30 Ω series
termination resistorsin both high and low output stages to
reduce line noise.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤ 2.5 ns

amb

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

propagation delay nDn to nQn CL= 50 pF; VCC= 3.3 V 3.3 ns
propagation delay nLE to nQn CL= 50 pF; VCC= 3.3 V 3.5 ns

t

PZH/tPZL

t

PHZ/tPLZ

C

I

C

PD

3-state output enable time nOE to nQn CL= 50 pF; VCC= 3.3 V 4.0 ns
3-state output disable time nOE to nQn CL= 50 pF; VCC= 3.3 V 3.4 ns
input capacitance 5.0 pF
power dissipation per latch VCC= 3.3 V; notes 1 and 2

outputs enabled 26 pF
outputs disabled 19 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi× N+Σ(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;

2004 Feb 05 2

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination
resistors; 5 V tolerant inputs/outputs; 3-state

VCC= supply voltage in Volts;
N = total load switching outputs;
Σ(CL× V

2. The condition is VI= GND to VCC.

ORDERING INFORMATION

TYPE NUMBER

74LVC162373ADGG −40 to +125 °C 48 TSSOP48 plastic SOT362-1
74LVCH162373ADGG −40 to +125 °C 48 TSSOP48 plastic SOT362-1
74LVC162373ADL −40 to +125 °C 48 SSOP48 plastic SOT370-1
74LVCH162373ADL −40 to +125 °C 48 SSOP48 plastic SOT370-1

FUNCTION TABLE

Per section of eight bits; note 1

Enable and read register (transparent mode) L H L L L

Latch and read register L L l L L

Latch register and disable outputs H L l L Z

2

× fo) = sum of the outputs.

CC

TEMPERATURE

OPERATING MODES

RANGE

PACKAGE

PINS PACKAGE MATERIAL CODE

INPUT

nOE nLE nDn

LHH H H

LLh H H

HLh H Z

74LVC162373A;

74LVCH162373A

INTERNAL

LATCH

OUTPUT nQn

Note

1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.

2004 Feb 05 3

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination
resistors; 5 V tolerant inputs/outputs; 3-state

PINNING

SYMBOL PIN DESCRIPTION

1OE 1 output enable input

(active LOW)
1Q0 2 data output
1Q1 3 data output
GND 4, 10, 15, 21, 28,

ground (0 V)

34, 39, 45
1Q2 5 data output
1Q3 6 data output
V

CC

7, 18, 31, 42 supply voltage
1Q4 8 data output
1Q5 9 data output
1Q6 11 data output
1Q7 12 data output
2Q0 13 data output
2Q1 14 data output
2Q2 16 data output
2Q3 17 data output
2Q4 19 data output
2Q5 20 data output
2Q6 22 data output
2Q7 23 data output
2OE 24 output enable input

(active LOW)

2LE 25 latch enable input

(active HIGH)
2D7 26 data input
2D6 27 data input
2D5 29 data input
2D4 30 data input
2D3 32 data input
2D2 33 data input
2D1 35 data input
2D0 36 data input
1D7 37 data input
1D6 38 data input
1D5 40 data input
1D4 41 data input
1D3 43 data input
1D2 44 data input

SYMBOL PIN DESCRIPTION

1D1 46 data input
1D0 47 data input
1LE 48 latch enable input

1OE

1Q0
1Q1

GND

1Q2
1Q3
V

CC

1Q4
1Q5

GND

1Q6
1Q7
2Q0
2Q1

GND

2Q2
2Q3
V

CC

2Q4
2Q5

GND

2Q6
2Q7

2OE

Fig.1 Pin configuration SSOP48 and TSSOP48.

74LVC162373A;

74LVCH162373A

(active HIGH)

1
2
3
4
5
6
7
8

9
10
11
12

162373A

13
14
15
16
17
18
19
20
21
22
23
24

001aaa336

48

1LE

47

1D0

46

1D1

45

GND

44

1D2

43

1D3
V

42

CC

41

1D4

40

1D5

39

GND

38

1D6

37

1D7

36

2D0

35

2D1

34

GND

33

2D2

32

2D3
V

31

CC

30

2D4

29

2D5

28

GND

27

2D6

26

2D7

25

2LE

2004 Feb 05 4

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination
resistors; 5 V tolerant inputs/outputs; 3-state

handbook, full pagewidth

1LE

1OE

Q

D

LATCH

1

LE LE

to 7 other channels

1Q01D0

2LE

2OE

Fig.2 Logic diagram.

74LVC162373A;

74LVCH162373A

Q

D

LATCH

9

LE LE

to 7 other channels

2Q02D0

MGU769

1

24

1OE

2OE

47

1D0

46

1D1

44

1D2

43

1D3

41

1D4
1D5

40

1D6

38

1D7

37

2D0

36

2D1

35

2D2

33

2D3

32

2D4

30

2D5

29

2D6

27

2D7

26

1LE 2LE

48 25

1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7

2
3
5
6
8

9
11
12
13
14
16
17
19

20

22

23

mgu768

1OE

1LE

2OE

2LE

1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7

1

48
24
25

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

1EN
C3
2EN
C4

3D

4D 2

mgu770

2

1

1Q0

3

1Q1

5

1Q2

6

1Q3

8

1Q4

9

1Q5

11

1Q6

12

1Q7

13

2Q0

14

2Q1

16

2Q2

17

2Q3

19

2Q4

20

2Q5

22

2Q6

23

2Q7

Fig.3 Logic symbol.

2004 Feb 05 5

Fig.4 Logic symbol (IEEE/IEC).

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination
resistors; 5 V tolerant inputs/outputs; 3-state

input

V

CC

to internal circuit

MNA428

handbook, halfpage

74LVC162373A;

74LVCH162373A

Fig.5 Bushold circuit.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

supply voltage for maximum speed performance 2.7 3.6 V

for low-voltage applications 1.2 3.6 V

V

I

V

O

input voltage 0 5.5 V
output voltage output HIGH or LOW state 0 V

CC

V

output 3-state 0 5.5 V

T

amb

tr,t

f

operating ambient temperature in free-air −40 +125 °C
input rise and fall times VCC= 1.2 to 2.7 V 0 20 ns/V

VCC= 2.7 to 3.6 V 0 10 ns/V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

I

IK

V

I

I

OK

V

O

supply voltage −0.5 +6.5 V
input diode current VI<0 −−50 mA
input voltage note 1 −0.5 +6.5 V
output diode current VO>VCC or VO<0 −±50 mA
output voltage output HIGH or LOW state; note 1 −0.5 VCC+ 0.5 V

output 3-state; note 1 −0.5 +6.5 V

I

O

ICC, I
T

stg

P

tot

GND

output source or sink current VO=0toV

CC

−±50 mA
VCC or GND current −±100 mA
storage temperature −65 +150 °C
power dissipation T

= −40 to +125 °C; note 2 − 500 mW

amb

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. Above 60 °C the value of P

derates linearly with 5.5 mW/K.

tot

2004 Feb 05 6