INTEGRATED CIRCUITS
74LVC162244A/74LVCH162244A
16-bit buffer/line driver; with 30Ω series termination resistors, 5V input/output tolerant (3-State)
Product specification |
1998 Feb 17 |
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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16-bit buffer/line driver; with 30Ω series termination |
74LVC162244A/ |
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resistors; 5V input/output tolerant (3-State) |
74LVCH162244A |
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FEATURES
•5 volt tolerant inputs/outputs for interfacing with 5V logic
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTETM flow-through standard pin-out architecture
•Low inductance multiple power and ground pins for minimum noise and ground bounce
•Direct interface with TTL levels
•Bus Hold on data inputs (74LVCH162244A only)
•Integrated 30W termination resistors
DESCRIPTION
The 74LVC(H)162244A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment.
The 74LVC(H)162244A is a 16-bit non-inverting buffer/line driver with 3-State outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LVC(H)162244A is designed with 30W series termination resistors in both HIGH and LOW output stages to reduce line noise. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
The 74LVCH162244A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.
PIN CONFIGURATION
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1 |
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48 |
2OE |
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1OE |
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1Y0 |
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47 |
1A0 |
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1Y1 |
3 |
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46 |
1A1 |
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GND |
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45 |
GND |
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1Y2 |
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44 |
1A2 |
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1Y3 |
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43 |
1A3 |
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VCC |
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42 |
VCC |
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2Y0 |
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41 |
2A0 |
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2Y1 |
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40 |
2A1 |
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GND |
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39 |
GND |
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2Y2 |
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38 |
2A2 |
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2Y3 |
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2A3 |
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3Y0 |
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36 |
3A0 |
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3Y1 |
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35 |
3A1 |
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GND |
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34 |
GND |
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3Y2 |
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33 |
3A2 |
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3Y3 |
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32 |
3A3 |
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VCC |
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31 |
VCC |
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4Y0 |
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30 |
4A0 |
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4Y1 |
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29 |
4A1 |
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GND |
21 |
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28 |
GND |
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4Y2 |
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27 |
4A2 |
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4Y3 |
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26 |
4A3 |
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24 |
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25 |
3OE |
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4OE |
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SW00194 |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
DWG NUMBER |
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48-Pin Plastic SSOP Type III |
±40°C to +85°C |
74LVC162244A DL |
VC162244A DL |
SOT370-1 |
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48-Pin Plastic TSSOP Type II |
±40°C to +85°C |
74LVC162244A DGG |
VC162244A DGG |
SOT362-1 |
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48-Pin Plastic SSOP Type III |
±40°C to +85°C |
74LVCH162244A DL |
VCH162244A DL |
SOT370-1 |
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48-Pin Plastic TSSOP Type II |
±40°C to +85°C |
74LVCH162244A DGG |
VCH162244A DGG |
SOT362-1 |
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
CL = 50pF |
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tPHL/tPLH |
1An to 1Yn; |
2.9 |
ns |
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VCC = 3.3V |
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2An to 2Yn |
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CI |
Input capacitance |
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5.0 |
pF |
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CPD |
Power dissipation capacitance per buffer |
VI = GND to VCC1 |
25 |
pF |
NOTES:
1.CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
1998 Feb 17 |
2 |
853-2014 18975 |
Philips Semiconductors |
Product specification |
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|
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16-bit buffer/line driver; with 30Ω series termination |
74LVC162244A/ |
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resistors; 5V input/output tolerant (3-State) |
74LVCH162244A |
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PIN DESCRIPTION
PIN NUMBER |
SYMBOL |
NAME AND FUNCTION |
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Output enable input |
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1 |
1OE |
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(active LOW) |
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2, 3, 5, 6 |
1Y0 to 1Y3 |
Data outputs |
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4, 10, 15, 21, |
GND |
Ground (0V) |
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28, 34, 39, 45 |
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7, 18, 31, 42 |
VCC |
Positive supply voltage |
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8, 9, 11, 12 |
2Y0 to 2Y3 |
Data outputs |
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13, 14, 16, 17 |
3Y0 to 3Y3 |
Data outputs |
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19, 20, 22, 23 |
4Y0 to 4Y3 |
Data outputs |
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Output enable input |
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24 |
4OE |
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(active LOW) |
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Output enable input |
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25 |
3OE |
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(active LOW) |
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30, 29, 27, 26 |
4A0 to 4A3 |
Data inputs |
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36, 35, 33, 32 |
3A0 to 3A3 |
Data inputs |
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41, 40, 38, 37 |
2A0 to 2A3 |
Data inputs |
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47, 46, 44, 43 |
1A0 to 1A3 |
Data inputs |
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Output enable input |
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48 |
2OE |
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(active LOW) |
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LOGIC SYMBOL
47 |
2 |
1Y0 |
36 |
13 |
1A0 |
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3A0 |
3Y0 |
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46 |
3 |
1Y1 |
35 |
14 |
1A1 |
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3A1 |
3Y1 |
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44 |
5 |
1Y2 |
33 |
16 |
1A2 |
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3A2 |
3Y2 |
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43 |
6 |
1Y3 |
32 |
17 |
1A3 |
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3A3 |
3Y3 |
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1 |
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25 |
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1OE |
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3OE |
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41 |
8 |
2Y0 |
30 |
19 |
2A0 |
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4A0 |
4Y0 |
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40 |
9 |
2Y1 |
29 |
20 |
2A1 |
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4A1 |
4Y1 |
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38 |
11 |
2Y2 |
27 |
22 |
2A2 |
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4A2 |
4Y2 |
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37 |
12 |
2Y3 |
26 |
23 |
2A3 |
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4A3 |
4Y3 |
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48 |
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24 |
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2OE |
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4OE |
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FUNCTION TABLE
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INPUTS |
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OUTPUT |
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nAn |
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nYn |
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nOE |
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L |
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L |
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L |
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L |
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H |
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H |
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H |
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X |
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Z |
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H = HIGH voltage level |
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L = LOW voltage level |
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X = don't care |
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Z = high impedance OFF-state |
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LOGIC SYMBOL (IEEE/IEC) |
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1 |
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1EN |
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1OE |
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2EN |
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2OE |
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25 |
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3EN |
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3OE |
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24 |
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4EN |
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4OE |
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47 |
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2 |
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1A0 |
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1 |
1 |
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1Y0 |
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46 |
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3 |
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1A1 |
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1Y1 |
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1A2 |
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1Y2 |
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1A3 |
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1Y3 |
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41 |
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8 |
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2A0 |
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2Y0 |
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2A1 |
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2Y1 |
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2A2 |
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2Y2 |
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12 |
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2A3 |
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2Y3 |
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36 |
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3A0 |
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3Y0 |
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3A1 |
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3Y1 |
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3A2 |
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16 |
3Y2 |
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32 |
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17 |
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3A3 |
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3Y3 |
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30 |
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19 |
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4A0 |
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4Y0 |
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1 |
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29 |
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4A1 |
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4Y1 |
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27 |
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22 |
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4A2 |
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4Y2 |
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26 |
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23 |
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4A3 |
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4Y3 |
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SW00056 |
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BUSHOLD CIRCUIT
VCC
Data Input |
To internal circuit |
SW00195
SW00044
1998 Feb 17 |
3 |