Philips 74LVC841APW, 74LVC841ADB, 74LVC841AD Datasheet

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74LVC841A

10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)

Product specification	1998 Jun 17
IC24 Data Handbook

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Philips Semiconductors	Product specification

10-bit transparent latch with 5-volt tolerant

74LVC841A

inputs/outputs (3-State)

FEATURES

•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

•Wide supply voltage range of 1.2 V to 3.6 V

•In accordance with the JEDEC standard no. 8-1 A

•Inputs accept voltages up to 5.5 V

•CMOS low power consumption

•Direct interface with TTL levels

•Flow-through pin-out architecture

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns

DESCRIPTION

The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. In 3-State operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74LVC841A consists of ten transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the ten latches are available at the outputs.

When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	Propagation delay	CL = 50 pF;
tPHL/tPLH	Dn to Qn;	VCC = 3.3 V	4.5	ns
	LE to Qn		5.0
CI	Input capacitance		5.0	pF
CPD	Power dissipation capacitance per latch	VI = GND to VCC1	22	pF

NOTE:

1CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD ×VCC2 ×fi (CL ×VCC2 ×fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL ×VCC2 ×fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
24-Pin Plastic SO	±40°C to +125°C	74LVC841A D	74LVC841A D	SOT137-1
24-Pin Plastic SSOP Type II	±40°C to +125°C	74LVC841A DB	74LVC841A DB	SOT340-1
24-Pin Plastic TSSOP Type I	±40°C to +125°C	74LVC841A PW	7LVC841APW DH	SOT355-1

PIN CONFIGURATION												PIN DESCRIPTION
												PIN NUMBER		SYMBOL		NAME AND FUNCTION
	OE				1		24			VCC		1				Output enable input (active Low)
	D0													OE
					2		23			Q0
	D1
					3			22		Q1		2, 3, 4, 5, 6, 7, 8,	D0 to D9			Data inputs
	D2				4			21		Q2		9, 10, 11
	D3				5		20			Q3		23, 22, 21, 20, 19,	Q0 to Q9			3-state latch outputs
	D4				6		19			Q4		18, 17, 16, 15, 14
	D5				7		18			Q5		12	GND			Ground (0 V)
	D6				8	17				Q6
	D7									Q7		13	LE			Latch enable input (active HIGH)
					9		16
	D8				10		15			Q8		24	VCC			Positive supply voltage
	D9				11	14				Q9
GND					12		13			LE
						SV01723

1998 Jun 17

2

853-2071 19589

	Philips Semiconductors	Product specification
	10-bit transparent latch with 5-volt tolerant	74LVC841A
	inputs/outputs (3-State)

LOGIC SYMBOL (IEEE/IEC)								LOGIC SYMBOL
		13						13	C1
								1
									EN
2		LE				23
		D0		Q0				2
3		D1		Q1		22			1D			23
4		D2		Q2		21		3				22
5		D3				20
				Q3				4				21
6						19
		D4		Q4				5				20
7						18
		D5		Q5				6				19
						17
8		D6		Q6				7				18
						16
9		D7		Q7				8				17
10		D8		Q8		15		9				16
11		D9		Q9		14		10				15
		OE
								11				14
		1			SV01724							SV01725

LOGIC DIAGRAM

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

LATCH

LATCH

LATCH

LATCH

LATCH

LATCH

LATCH

LATCH

LATCH

LATCH

1

2

3

4

5

6

7

8

9

10

LE

LE

LE

LE

LE

LE

LE LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

SV01726

FUNCTION TABLE for register An or Bn

		OPERATING MODES				INPUTS		INTERNAL	OUTPUTS
			OE			LE	Dn	LATCHES	Q0	TO Q9
Enable and read register (transparent mode)				L		H	L	L		L
				L		H	H	H		H
Latch and read register				L		↓	l	L		L
				L		↓	h	H		H
latch register and disable outputs				H		X	l	L		Z
				H		X	h	H		Z
Hold				L		L	X	NC		NC
NOTES:
H	=	HIGH voltage level
h	=	HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L	=	LOW voltage level
l	=	LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X	=	don't care
Z	=	high impedance OFF-state
NC =		no change

1998 Jun 17

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