Philips 74LVC74APW, 74LVC74ADB, 74LVC74AD Datasheet

INTEGRATED CIRCUITS

74LVC74A

Dual D-type flip-flop with set and reset;
positive-edge trigger

Product specification
IC24 Data Handbook

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

1998 Jun 17

Philips Semiconductors Product Specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

FEA TURES

•Wide supply voltage range of 1.2 V to 3.6 V

•In accordance with JEDEC standard no. 8-1A.

•Inputs accept voltages up to 5.5 V

•CMOS low power consumption

•Direct interface with TTL levels

•Output drive capability 50  transmission lines @ 85°C

QUICK REFERENCE DATA

GND = 0 V; T

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW)

PD

= CPD × V

P

D

f

= input frequency in MHz; CL = output load capacity in pF;

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

 (C

L

2. The condition is V

= 25°C; tr = tf ≤ 2.5 ns

amb

SYMBOL

t

PHL/tPLH

f

max

C

I

C

PD

2

× fi  (CL × V

CC

2

× V

× fo) = sum of the outputs.

CC

= GND to V

I

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nR

to nQ, nQ

D

Maximum clock frequency 250 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per flip-flop Notes 1 and 2 30 pF

CC.

2

× fo) + (V

CC

2

/RL) × duty factor LOW, where:

O

74LVC74A

DESCRIPTION

The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.

The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
inputs; also complementary Q and Q

outputs.

The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.

Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.

CL = 50 pF;
VCC = 3.3 V

3.6

3.5

3.5

) and (RD)

D

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

14-Pin Plastic SO –40°C to +85°C 74LVC74A D 74LVC74A D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC74A DB 74LVC74A DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC74A PW 74LVC74APW DH SOT402-1

PIN CONFIGURATION

1R

1

D

1D

2

1CP

3

1S

4

D

1Q

5

1Q

6
78

GND

1998 Jun 17 853-2070 19589

14
13
12
11
10

9

SV00491

V
2R
2D
2CP
2S
2Q
2Q

CC

D

D

LOGIC SYMBOL (IEEE/IEC)

4
3
2
1

10
11

12
13

2

S

C1
1D
R

S

C2
2D
R

5

6

9

8

SV00332

Philips Semiconductors Product Specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

PIN DESCRIPTION

PIN

NUMBER

1, 13 1RD, 2R
2, 12 1D, 2D Data inputs
3, 11 1CP, 2CP

4, 10 1SD, 2S
5, 9 1Q, 2Q True flip-flop outputs

6, 8 1Q, 2Q Complement flip-flop outputs
7 GND Ground (0 V)
14 V

LOGIC SYMBOL

SYMBOL NAME AND FUNCTION

Asynchronous reset-direct input

D

(active LOW)

Clock input (LOW-to-HIGH, edge
triggered)

Asynchronous set-direct input (active

D

LOW)

CC

Positive supply voltage

410

1S

D2SD

S

1CP
2CP

1D
2D

D

DCPQ

R

D

1RD2R

113

FF

Q

D

2

12

3

11

1Q2Q5

1Q
2Q

SV00492

9

5
9

74LVC74A

FUNCTION TABLE

INPUTS OUTPUTS

S

D

L H X X H L

H L X X L H

L L X X H H

S

D

H H ° L L H
H H ° H H L

NOTES:

H = HIGH voltage level
L = LOW voltage level
X = don“t care
° = LOW-to-HIGH CP transition
Q

= state after the next LOW-to-HIGH CP transition

n+1

FUNCTIONAL DIAGRAM

R

D

CP D Q Q

INPUTS OUTPUTS

R

D

CP D Q

4

1S

D

S

D

DQ
CP FF1

Q

R

D

S

D

DQ
CP FF2

Q

R

D

1Q

1Q

2Q

2Q

1D2

3

1CP

1

1R

D

10

2S

D

2D12
2CP11

13

2R

D

n+1

5

6

9

8

Q

n+1

1998 Jun 17

SV00494

3