Philips 74LVC646APW, 74LVC646ADB, 74LVC646AD Datasheet
INTEGRATED CIRCUITS
74LVC646A
Octal bus transceiver/register (3-State)
Product specification
Supercedes data of 1998 Mar 25
IC24 Data Handbook
1998 Jul 29
Philips Semiconductors Product specification
74L VC646AOctal bus transceiver/register (3-State)
FEA TURES
•Wide supply voltage range of 1.2V to 3.6V
•Flow-through pin-out architecture
•In accordance with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC646A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC646A consist of non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
I/O
C
PD
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacitance in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
Σ (C
L
2. The condition is V
= 25°C; tr = tf ≤ 2.5 ns
amb
2
CC
2
V
fo) = sum of the outputs.
CC
I
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
An to Yn
Maximum clock frequency 250 MHz
Input capacitance 5.0 pF
Input/output capacitance 10 pF
Power dissipation capacitance per gate Notes 1, 2 26 pF
CC.
2
fo) where:
CC
x fi Σ (CL V
= GND to V
for multiplexed transmission of data directly from the internal
registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal
registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH
logic level. Output enable (OE
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and
SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data
when OE
data may be stored in the ‘B’ register and/or ‘B’ data may be stored
in the ‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
The ‘646A’ is functionally identical to the ‘648A’ but has non-inverting
data paths.
CL = 50pF
VCC = 3.3V 3.9
is active (LOW). In the isolation mode (OE = HIGH), ‘A’
) and direction (DIR) inputs are
ns
ORDERING AND PACKAGE INFORMA TION
PACKAGES TEMPERATURE RANGE
24-Pin Plastic SO –40°C to +85°C 74LVC646A D 74LVC646A D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74LVC646A DB 74LVC646A DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC646A PW 7LVC646APW DH SOT355-1
1998 Jul 29 853-2105 19803
OUTSIDE NORTH
AMERICA
2
NORTH AMERICA PKG. DWG. #
Philips Semiconductors Product specification
FUNCTION
74LVC646AOctal bus transceiver/register (3-State)
PIN CONFIGURATION
CP
GND
S
DIR
AB
AB
A
A
A
A
A
A
A
A
1
2
3
4
0
5
1
6
2
7
3
8
4
9
5
10
6
11
7
12
24
23
22
21
20
19
18
17
16
15
14
13
SV00766
V
CP
S
OE
B
B
B
B
B
B
B
B
CC
BA
BA
0
1
2
3
4
5
6
7
FUNCTION TABLE
INPUTS DATA I/O *
OE DIR CP
X
X
H
H
L
L
L
L
X
X
X
X
L
L
H
H
H or L↑H or L
H or L
* The data output functions may be enabled or disabled by
various signals at the OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will
be stored on every LOW-to-HIGH transition on the clock
inputs.
un = unspecified
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
↑ = LOW-to-HIGH level transition
CP
AB
↑
X
X
↑
↑
X
X
X
X
H or L
X
X
BA
S
AB
X
X
X
X
X
X
L
H
S
BA
X
X
X
X
L
H
X
X
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 CP
2 S
3 DIR Direction control input
4, 5, 6, 7, 8,
9, 10, 11
12 GND Ground (0V)
20, 19, 18, 17,
16, 15, 14, 13
21 OE Output enable input (active LOW)
22 S
23 CP
24 V
A0 to A
7
input
un *
input input
output input
input output
B0 to B
input
un *
7
AB
AB
A0 to A
B0 to B
BA
BA
CC
‘A’ to ‘B’ clock input
(LOW-to-HIGH, edge-triggered)
Select ‘A’ to ‘B’ source input
‘A’ data inputs/outputs
7
‘B’ data inputs/outputs
7
Select ‘B’ to ‘A’ source input
‘B’ to ‘A’ clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
store A, B unspecified *
store B, A unspecified *
store A and B data,
isolation hold storage
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
1998 Jul 29
3
Philips Semiconductors Product specification
74LVC646AOctal bus transceiver/register (3-State)
LOGIC SYMBOL
1
2
4
5
6
7
8
9
10
11
AB
S
AB
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DIR
OE
CP
LOGIC SYMBOL (IEEE/IEC)
23
1
21
22
2
3
4
5
6
7
8
9
10
11
C4
C5
G3
G6
G7
3EN2
3EN1
≥
5D
1
6
1
6
7
7
1
FUNCTIONAL DIAGRAM
21
CP
S
3
4D
1
1
≥
2
BA
BA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
SV00765
23
22
20
19
18
17
16
15
14
13
20
19
18
17
16
15
14
13
4
A
0
A
5
1
A
6
2
A
7
3
A
8
4
A
9
5
A
10
6
A
11
7
21
OE
3
DIR
2
S
AB
22
S
BA
1
CP
AB
23
CP
BA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
SV00763
20
19
18
17
16
15
14
13
1998 Jul 29
SV00764
4
Philips Semiconductors Product specification
74LVC646AOctal bus transceiver/register (3-State)
LOGIC DIAGRAM
OE
DIR
S
BA
CP
BA
S
AB
CP
AB
V
CC
S
D
Y
1
A
n
S
D
Y
1
MUX
D
FF
CP
8 identical channels
D
Q
2
n
MUX
D
Q
D
2
FF
n
CP
V
CC
B
n
SV00762
1998 Jul 29
5
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