INTEGRATED CIRCUITS
74LVC574A
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
Product specification |
1998 Jul 29 |
m n r
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with 5-volt tolerant |
74LVC574A |
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inputs/outputs; positive edge-trigger (3-State) |
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FEATURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when VCC = 0V
•8-bit positive edge-triggered register
•Independent register and 3-State buffer operation
•Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
QUICK REFERENCE DATA
GND = 0V; Tamb =25°C; tr = tf 2.5ns
Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC574A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
The '574A' is functionally identical to the '374A', but the '374A' has a different pin arrangement.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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tPHL/tPLH |
Propagation delay |
CL = 50pF |
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CP to Qn |
VCC = 3.3V |
4.8 |
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fmax |
maximum clock frequency |
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150 |
MHz |
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CI |
Input capacitance |
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5.0 |
pF |
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CPD |
Power dissipation capacitance per |
Notes 1 and 2 |
20 |
pF |
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flip-flop |
NOTE:
1.CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL x VCC2 x fo) = sum of outputs.
2.The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES |
TEMPERATURE |
OUTSIDE |
NORTH AMERICA |
PKG. DWG. # |
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RANGE |
NORTH AMERICA |
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20-Pin Plastic Shrink Small Outline (SO) |
±40°C to +85°C |
74LVC574A D |
74LVC574A D |
SOT163-1 |
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20-Pin Plastic Shrink Small Outline (SSOP) Type II |
±40°C to +85°C |
74LVC574A DB |
74LVC574A DB |
SOT339-1 |
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20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I |
±40°C to +85°C |
74LVC574A PW |
7LVC574APW DH |
SOT360-1 |
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1998 Jul 29 |
2 |
853-1863 19804 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with 5-volt tolerant |
74LVC574A |
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inputs/outputs; positive edge-trigger (3-State) |
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PIN DESCRIPTION
PIN NUMBER |
SYMBOL |
FUNCTION |
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1 |
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Output enable input (active-Low) |
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OE |
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2, 3, 4, 5, |
D0-D7 |
Data inputs |
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6, 7, 8, 9 |
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19, 18, 17, 16, |
Q0-Q7 |
Data outputs |
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15, 14, 13, 12 |
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10 |
GND |
Ground (0V) |
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11 |
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CP |
Clock input (LOW-to-HIGH, |
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edge-triggered) |
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20 |
VCC |
Positive supply voltage |
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PIN CONFIGURATION
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OE |
1 |
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20 |
VCC |
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D0 |
2 |
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19 |
Q0 |
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D1 |
3 |
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18 |
Q1 |
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D2 |
4 |
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17 |
Q2 |
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D3 |
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5 |
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16 |
Q3 |
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D4 |
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6 |
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15 |
Q4 |
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D5 |
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7 |
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14 |
Q5 |
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D6 |
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8 |
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13 |
Q6 |
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D7 |
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9 |
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12 |
Q7 |
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GND |
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10 |
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11 |
CP |
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SA00400 |
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LOGIC SYMBOL
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11 |
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2 |
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D0 |
CP |
Q0 |
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19 |
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3 |
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D1 |
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Q1 |
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18 |
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4 |
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D2 |
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Q2 |
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17 |
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5 |
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D3 |
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Q3 |
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16 |
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6 |
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D4 |
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Q4 |
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15 |
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7 |
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D5 |
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Q5 |
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14 |
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8 |
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D6 |
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Q6 |
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13 |
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9 |
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D7 |
OE |
Q7 |
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12 |
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1 |
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LOGIC SYMBOL (IEEE/IEC)
1 |
C1 |
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11 |
EN |
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2 |
19 |
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1D |
3 |
18 |
4 |
17 |
5 |
16 |
6 |
15 |
7 |
14 |
8 |
13 |
9 |
12 |
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SA00402 |
FUNCTIONAL DIAGRAM
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2 |
D0 |
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Q0 |
19 |
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3 |
D1 |
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Q1 |
18 |
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4 |
D2 |
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Q2 |
17 |
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5 |
D3 |
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FF! |
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Q3 |
16 |
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3-State |
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6 |
D4 |
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to |
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Q4 |
15 |
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OUTPUTS |
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FF8 |
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7 |
D5 |
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Q5 |
14 |
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8 |
D6 |
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Q6 |
13 |
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9 |
D7 |
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Q7 |
12 |
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11 |
CP |
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1 |
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OE |
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SA00403 |
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SA00401
1998 Jul 29 |
3 |
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