Philips 74LVC543APW, 74LVC543ADB, 74LVC543AD Datasheet

INTEGRATED CIRCUITS

74LVC543A

Octal D-type registered transceiver (3-State)

Product specification

1998 Jul 31

Supersedes data of 1997 Jun 30

IC24 Data Handbook

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Philips Semiconductors	Product specification
Octal D-type registered transceiver (3-State)	74LVC543A

FEATURES

•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

•Supply voltage range of 1.2V to 3.6V

•Complies with JEDEC standard no. 8±1A

•CMOS low power consumption

•Direct interface with TTL levels

•8-bit octal transceiver with D-type latch

•Back-to-back registers for storage

•Separate controls for data flow in each direction

•3-State non-inverting outputs for bus oriented applications

•High impedance when VCC = 0V

DESCRIPTION

The 74LVC543A is a high±performance, low±power, low±voltage, Si±gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74LVC543A is an octal registered transceiver containing two sets of D±type latches for temporary storage of the data flow in either direction. Separate latch enable (LEAB, LEBA) and output

enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of the data flow.

The 74LVC543A contains eight D±type latches, with separate inputs and controls for each set. For data flow from A to B, for example, the A±to±B enable (EAB) input must be LOW in order to enter data from A0±A7 or take data from B0±B7, as indicated in the function table.

With EAB LOW, a LOW signal on the A±to±B latch enable (LEAB) input makes the A±to±B latches transparent; a subsequent LOW±to HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both low, the 3±state B output buffers are active and display the data present at the outputs of the A latches

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; Tr = Tf ≤ 2.5ns

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	tPHL/tPLH	Propagation delay	CL = 50 pF	3.3	ns
		An to Bn	VCC = 3.3V
	CI	input capacitance		5.0	pF
	CI/O	input/output capacitance		10.0	pF
	CPD	power dissipation capacitance per latch	VCC = 3.3V	27	pF

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in μW) PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL x VCC2 x fo ) = sum of the outputs

2.The condition is VI = GND to VCC

ORDERING INFORMATION

	PACKAGES	TEMPERATURE	OUTSIDE NORTH	NORTH AMERICA	PKG DWG. #
		RANGE	AMERICA
	24-Pin Plastic Small Outline (SO)	±40°C to +85°C	74LVC543A D	74LVC543A D	SOT137-1
	24-Pin Plastic Shrink Small Outline (SSOP) Type II	±40°C to +85°C	74LVC543A DB	74LVC543A DB	SOT340-1
	24-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I	±40°C to +85°C	74LVC543A PW	7LVC543APW DH	SOT355-1

1998 Jul 31

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853-1992 19813

Philips Semiconductors	Product specification
Octal D-type registered transceiver (3-State)	74LVC543A

PIN CONFIGURATION

LOGIC SYMBOL

						1	24	VCC
		LEBA
						2	23
	OEBA							EAB
				A0		3	22	B0
				A1		4	21	B1
				A2		5	20	B2
				A3		6	19	B3
				A4		7	18	B4
				A5		8	17	B5
				A6		9	16	B6
				A7		10	15	B7
						11	14
			EBA					LEAB
		GND				12	13
								OEAB
							SW00212

PIN DESCRIPTION

PIN NUMBER	SYMBOL					FUNCTION
						'B' to 'A' latch enable input
1		LEBA
						(active LOW)
						'B' to 'A' output enable
2		OEBA
						input (active LOW)
3,4,5,6, 7, 8, 9 10	A0 to A7					'A' data inputs/outputs
						'B' to 'A' enable input
11			EBA
						(active LOW)
12		GND				ground (0V)
22, 21, 20, 19,	B0 to B7					'B' data inputs/outputs
18, 17, 16, 15
						'A' to 'B' output enable
13		OEAB
						input (active LOW)
						'A' to 'B' latch enable input
14		LEAB
						(active LOW)
						'A' to 'B' enable input
23			EAB
						(active LOW)
24		VCC				positive supply voltage

	3		A0			B0	22
4			A1			B1	21
5			A2			B2	20
6			A3			B3	19
7			A4			B4	18
8			A5			B5	17
9			A6			B6	16
10			A7			B7	15

2 OEBA

13 OEAB

11 EBA

23 EAB

14 LEAB

1 LEBA

SW00213

LOGIC SYMBOL (IEEE/IEC)

	2	1EN3
	23	G1
	1
		1C5
	13	2EN4
	11
		G2
	14
		2C6

3	3	22
		5D
	6D	4
4		21
5		20
6		19
7		18
8		17
9		16
10		15

SW00214

1998 Jul 31

3

Philips Semiconductors	Product specification
Octal D-type registered transceiver (3-State)	74LVC543A

LOGIC DIAGRAM

OEBA

EBA

LEBA

OEAB

EAB

LEAB

LE

An

D

Bn

LE

D

8 IDENTICAL

CHANNELS

TO 7 OTHER CHANNELS

SW00215

FUNCTION TABLE

OPERATING MODES

INPUTS

OUTPUTS

OEXX

EXX

LEXX

DATA

Disabled

H

X

X

X

Z

Disabled

X

H

X

X

Z

Disabled + Latch

L

↑

L

h

Z

L

↑

L

l

Z

Latch + Display

L

L

↑

h

H

L

L

↑

l

L

Transparent

L

L

L

H

H

L

L

L

L

L

Hold

L

L

H

X

NC

(do nothing)

NOTES:

XX

=

AB for A-to-B direction, BA for B-to-A direction

H

=

High voltage level

L

=

Low voltage level

h

=

High state must be present one setup time before the Low-to-High transition of LEAB, LEBA, EAB, EBA

l

=

Low state must be present one setup time before the Low-to-High transition of LEAB, LEBA, EAB, EBA

X

=

Don't care

↑

=

Low-to-High level transition

NC

=

No change

Z

=

High impedance OFF state

1998 Jul 31

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