Philips 74lvc373a DATASHEETS
INTEGRATED CIRCUITS
74LVC373A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification 1998 Jul 29
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
74L VC373A
tolerant inputs/outputs (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when V
DESCRIPTION
The 74LVC373A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
CC
= 0V
The 74LVC373A is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for
bus-oriented applications. A latch enable (LE) input and an output
enable (OE
The ’373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D
latches. In this condition, the latches are transparent, i.e. a latch
output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present
at the D-inputs one setup time preceding the HIGH-to-LOW
transition of LE. When OE
are available at the outputs. When OE
high impedance OFF-state. Operation of the OE
affect the state of the latches.
The ’373’ is functionally identical to the ’573’, but the ’573’ has a
different pin arrangement.
) input are common to all internal latches.
is LOW, the contents of the eight latches
is HIGH, the outputs go to the
inputs enters the
n
input does not
t
PHL/tPLH
C
I
C
PD
NOTE:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
= CPD x V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
2. The condition is V
CC
2
x V
x fo) = sum of outputs.
CC
Propagation delay
Dn to Q
n;
LE to Q
n
Input capacitance 5.0 pF
Power dissipation capacitance per latch Notes 1 and 2 20 pF
2
x fi + (CL x V
= GND to V
I
CC
CC
2
x fo) where:
CL = 50pF
VCC = 3.3V 4.2
4.6
ns
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC373A D 74LVC373A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC373A DB 74LVC373A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC373A PW 7LVC373APW DH SOT360-1
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
NORTH AMERICA PKG. DWG. #
1998 Jul 29 853-1860 19802
2
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
PIN CONFIGURATION
V
1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3 Q4
10 11
GND
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8, 13,
14, 17, 18
2, 5, 6, 9, 12,
15, 16, 19
D0-D7 Data inputs
Q0-Q7 Data outputs
11 LE Latch enable input (active-High)
10 GND Ground (0V)
20 V
CC
LOGIC SYMBOL
3 4 7 8 13 14 1817
20
CC
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
12
LE
SA00383
Positive supply voltage
74LVC373A
LOGIC SYMBOL (IEEE/IEC)
1
11
32
4 5
7 6
89
13 12
14 15
17 16
18 19
FUNCTIONAL DIAGRAM
45
D1 Q1
89
D3 Q3
13
14 15
D5 Q5
18 19
D7 Q7
LE
11
1
OE
EN
C1
1D
LATCH
1 to 8
SA00385
3-State
OUTPUTS
23
Q0D0
67
Q2D2
12
Q4D4
1617
Q6D6
1998 Jul 29
D0 D1 D2 D3 D4 D5 D6 D7
11
LE
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SA00387
SA00384
3
Philips Semiconductors Product specification
OPERATING MODES
INTERNAL LATCHES
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
LOGIC DIAGRAM
D0
D
LE
LE
LE
OE
FUNCTION TABLE
Enable and read register
(transparent mode)
Latch and read register L
Latch register and
disable outputs
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition
X = Don’t care
Z = High impedance OFF-state
D1
Q
Q0
D
LE
LE
D2
QQQ QQQQ
D
LE
LE
Q1 Q2 Q3 Q4 Q5 Q6 Q7
D3
D
LE
LE
INPUTS
OE LE D
L
L
H
H
L
L
H
H
L
L
L
n
L
H
l
h
l
h
74LVC373A
D4
D
LE
LE
D5
D
LE
LE
D6
D
LE
LE
D7
D
LE
LE
SA00386
OUTPUTS
Q0 to Q
7
L
H
L
H
L
H
L
H
H
H
Z
Z
1998 Jul 29
4
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