Philips 74LVC1G07GW Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74LVC1G07
Buffer with open-drain output
Product specification
Supersedes data of 2000 Nov 22
File under Integrated Circuits, IC24
2001 Apr 06
Philips Semiconductors Product specification
Buffer with open-drain output 74LVC1G07
FEATURES
• Wide supply voltage range from 1.65 to 5.5 V
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• 24 mA output drive (VCC= 3.0 V)
• CMOS low power consumption
• Latch-up performance ≤250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• SOT353 package.
DESCRIPTION
The 74LVC1G07 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The input can be driven from either 3.3 or 5 V devices.
This featureallows the use of this device as translator in a
mixed 3.3 and 5 V environment.
Schmitttriggeractionattheinputmakesthecircuittolerant
for slower input rise and fall time.
The 74LVC1G07 provides the non-inverting buffer.
The output of the device is an open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤2.5 ns.
amb
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PLZ/tPZL
C
I
C
PD
propagation delay input A to output Y CL= 50 pF; VCC= 3.3 V 2.2 ns
input capacitance 5 pF
power dissipation capacitance per gate VCC= 3.3 V; notes 1 and 2 7 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+(CL×V
CC
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
= supply voltage in Volts.
V
CC
2. The condition is VI= GND to VCC.
FUNCTION TABLE
See note 1.
INPUT OUTPUT
AY
LL
HZ
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
2
× fo) where:
2001 Apr 06 2
Philips Semiconductors Product specification
Buffer with open-drain output 74LVC1G07
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING
74LVC1G07GW −40 to +85 °C 5 SC-88A plastic SOT353 VS
PINNING
PIN SYMBOL DESCRIPTION
1 n.c. not connected
2 A data input A
3 GND ground (0 V)
4 Y data output Y
5V
handbook, halfpage
n.c.
GND
CC
1
A
2
07
3
MNA622
V
5
CC
Y
4
supply voltage
handbook, halfpage
AY
2
MNA623
4
Fig.1 Pin configuration.
handbook, halfpage
2
A
MNA624
4
Y
Fig.3 IEC logic symbol.
2001 Apr 06 3
handbook, halfpage
Fig.2 Logic symbol.
Y
A
GND
Fig.4 Logic diagram.
MNA625
Philips Semiconductors Product specification
Buffer with open-drain output 74LVC1G07
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
V
O
T
amb
t
r,tf
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
, I
CC
GND
T
stg
P
D
supply voltage 1.65 5.5 V
input voltage 0 5.5 V
output voltage active mode 0 V
CC
V
high-impedance mode 0 5.5 V
operating ambient temperature −40 +85 °C
input rise and fall times VCC= 1.65 to 2.7 V 0 20 ns/V
V
= 2.7 to 5.5 V 0 10 ns/V
CC
supply voltage −0.5 +6.5 V
input diode current VI<0 −−50 mA
input voltage note 1 −0.5 +6.5 V
output diode current VO>VCC or VO<0 −±50 mA
output voltage active mode; notes 1 and 2 −0.5 VCC+ 0.5 V
Power-down mode; notes 1 and 2 −0.5 +6.5 V
output source or sink current VO=0toV
CC
−±50 mA
VCC or GND current −±100 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range from
− 200 mW
−40 to +85 °C; note 3
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
3. Above 55 °C the value of PD derates linearly with 2.5 mW/K.
2001 Apr 06 4
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