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INTEGRATED CIRCUITS
74LVC169
Presettable synchronous 4-bit up/down
binary counter
specification
Supersedes data of 1996 Aug 23
IC24 Data Handbook
1998 May 20
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Philips Semiconductors Product specification
Presettable synchronous 4-bit up/down
binary counter
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•In accordance with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Synchronous counting and loading
•Up/down counting
•Modular 16 binary counter
•Two count enable inputs for n-bit cascading
•Built-in lookahead carry capability
•Presettable for programmable operation
•Positive-edge triggered clock
DESCRIPTION
The 74LVC169 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
74L VC169
The 74LVC169 is a synchronous presettable binary counter which
features an internal lookahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D
to D3) to be loaded into the counter on the positive-going edge
0
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The lookahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
to Q3) of the counters may be preset to a HIGH or
0
to Q3) to LOW level
0
, CET and CEP
. This
0
_______________________________
f
=
max
tp
(CP to TC) + tSU (CEP to CP)
(max)
1
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
MAX
C
I
C
PD
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD x V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
Σ (C
L
2. The condition is V
= 25°C; TR = TF 2.5ns
amb
Propagation delay
CP to Q
CP to TC
CET to TC
maximum clock frequency 200 MHz
input capacitance 5.0 pF
power dissipation capacitance per gate notes 1 and 2 42 pF
2
x fi +Σ (CL x V
CC
2
x V
x f
CC
= sum of the outputs
o )
= GND to V
1
PARAMETER CONDITIONS TYPICAL UNIT
CL = 50 pF
n
2
x f
CC
CC
where:
o )
VCC = 3.3V 5.0
6.5
5.3
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
16-Pin Plastic SO –40°C to +85°C 74LVC169 D 74LVC169 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC169 DB 74LVC169 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC169 PW 74LVC169PW DH SOT403-1
ns
1998 May 20 853-1866 19421
2
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Philips Semiconductors Product specification
Presettable synchronous 4-bit up/down
binary counter
PIN CONFIGURATION
U/D
CP
D
D
D
D
CEP
GND
LOGIC SYMBOL
1
2
3
0
4
1
5
2
6
3
7
3456
16
15
14
13
12
11
10
98
SF00766
V
TC
Q
Q
Q
Q
CET
PE
CC
0
1
2
3
74LVC169
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 U/D up/down control input
2 CP
3,4,5,6 D0 to D
7 CEP
8 GND ground (0V)
9 PE
10 CET
14,13,12,11 Q0 to Q
15 TC
16 V
CC
clock input (LOW-to-HIGH,
edge-triggered)
data inputs
3
count enable inputs (active
LOW)
parallel enable input
(active LOW)
count enable carry input
(active LOW)
flip-flop outputs
3
terminal count output
(active LOW)
positive supply voltage
10
VCC = Pin 16
GND = Pin 8
D
PE
9
1
U/D
CP
2
CEP
7
CET
0D1D2D3
Q0Q1Q2Q
TC
3
11121314
15
SF00786
LOGIC SYMBOL (IEEE/IEC)
9
1
10
7
2
3
4
5
6
CTR DIV 16
M1 [LOAD]
M2 [COUNT]
M3 [UP]
M4 [DOWN]
G5
G6
2, 3, 5, 6+/C7
2, 4, 5, 6–
1, 7D
[1]
[2]
[4]
[8]
3, 5 CT=15
4, 5 CT=0
15
14
13
12
11
SF00787
1998 May 20
3
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Philips Semiconductors Product specification
Presettable synchronous 4-bit up/down
binary counter
STATE DIAGRAM
01234
15
14
13
COUNT DOWN
COUNT UP
FUNCTION TABLE
OPERATING
MODES
Parallel load
(Dn→Qn)
CP U/D CEP CET PE DnQnTC
↑ X X X l l L *
↑
Count Up
(increment)
Count Down
(decrement)
Hold
(do nothing)
↑
↑
↑
↑
H = High voltage level steady state
h = High voltage level one setup time prior to the Low-to-High
clock transition
L = Low voltage level steady state
l = Low voltage level one setup time prior to the Low-to-High
clock transition
q = Lower case letters indicate the state of the referenced output
prior to the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
* = The TC
is Low when CET is Low and the counter is at
Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is
(LLLL).
INPUTS OUTPUTS
X X X X X H *
h l l h X
l l l h X
X h X h X q
X X X h X q
5
6
7
89101112
SF00788
Count
Up
Count
Down
n
H
n
74LVC169
TYPICAL TIMING SEQUENCE
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
Typical timing sequence: reset outputs to zero; preset to binary
*
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
*
*
12 13 14 15 0 1 2
RESET PRESET
INHIBITCOUNT
SY00069
1998 May 20
4
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Philips Semiconductors Product specification
Presettable synchronous 4-bit up/down
binary counter
LOGIC DIAGRAM
3
D
0
4
D
1
5
D
2
DCPQ
DCPQ
DCPQ
74LVC169
Q
Q
Q
14
Q
0
13
Q
1
12
Q
2
VCC= Pin 16
GND = Pin 8
D
PE
CEP
CET
CP
U/D
6
3
9
7
10
2
1
DCPQ
Q
11
15
SF00789
Q
3
TC
1998 May 20
5