Philips 74LVC163PW, 74LVC163DB, 74LVC163D Datasheet
INTEGRATED CIRCUITS
74LVC163
Presettable synchronous 4-bit binary
counter; synchronous reset
Product specification
Supersedes data of 1996 Aug 23
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary counter;
synchronous reset
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•In accordance with JEDEC standard no. 8–1A
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Synchronous reset
•Synchronous counting and loading
•Two count enable inputs for n–bit cascading
•Positive edge–triggered clock
DESCRIPTION
The 74LVC163 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC163 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D
to D3) to be loaded into the counter on the positive–going edge
0
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The look–ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set–up time,
according to the following formula:
74L VC163
to Q3) of the counters may be preset to a HIGH or
0
to Q3) to LOW level
0
, CET and CEP
. This
0
_______________________________
f
=
max
tp
(CP to TC) + tSU (CEP to CP)
(max)
1
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
MAX
C
I
C
PD
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD x V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
Σ (C
L
2. The condition is V
= 25°C; TR = TF 2.5ns
amb
Propagation delay
CP to Q
CP to TC
CET to TC
maximum clock frequency 200 MHz
input capacitance 5.0 pF
power dissipation capacitance per gate notes 1 and 2 39 pF
2
x fi +Σ (CL x V
CC
2
x V
x f
CC
= sum of the outputs
o )
= GND to V
1
PARAMETER CONDITIONS TYPICAL UNIT
CL = 50 pF
n
2
x f
CC
CC
where:
o )
VCC = 3.3V 4.9
5.7
4.5
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
16-Pin Plastic SO –40°C to +85°C 74LVC163 D 74LVC163 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC163 DB 74LVC163 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC163 PW 74LVC163PW DH SOT403-1
ns
1998 May 20 853-1865 19421
2
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary counter;
synchronous reset
PIN CONFIGURATION
LOGIC SYMBOL
MR
CP
CEP
1
2
D0
3
D1
4
D2
5
D3
6
16
V
CC
TC
15
Q0
14
Q1
13
Q2
12
Q3
11
CET
107
98GND PE
SF00656
15
74LVC163
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 MR
2 CP
3,4,5,6 D0 to D
7 CEP count enable inputs
8 GND ground (0V)
9 PE
10 CET count enable carry input
14,13,12,11 Q0 to Q
15 TC terminal count output
16 V
CC
LOGIC SYMBOL (IEEE/IEC)
asynchronous master
reset (active LOW)
clock input (LOW-to-HIGH,
edge-triggered)
data inputs
3
parallel enable input
(active LOW)
flip-flop outputs
3
positive supply voltage
3
4
5
6
9PE
V
= Pin 16
CC
GND = Pin 8
D
0
D
1
D
2
D
3
CEP
CET
710
TC
CP MR
21
Q
0
Q
1
Q
2
Q
3
14
13
12
11
SY00065
1
9
7
10
2
3
4
5
6
R
M1
G3
G4
C2 /1,3,4+
,2 D
1
CTR4
4 CT=15
14
13
12
11
15
SY00066
1998 May 20
3
Philips Semiconductors Product specification
Parallel load
Presettable synchronous 4-bit binary counter;
synchronous reset
FUNCTIONAL DIAGRAM
3456
D
D
3
2
TC 15
Q
Q
3
2
10
7
2CP
1
PE9
CET
CEP
MR
D
D
1
0
PARALLEL LOAD
CIRCUITRY
BINARY
COUNTER
Q
Q
1
0
14 13 12 11
74LVC163
FUNCTION TABLE
OPERATING
MODES
MR CP CEP CET PE Dn Qn TC
Reset (clear) l ↑ X X X X L L
h ↑ X X l l L L
h ↑ X X l h H *
Count h ↑ h h h X count *
Hold h X l X h X q
(do nothing) h X X l h X q
NOTES:
* = The TC output is High when CET is High and the counter
is at Terminal Count (HHHH)
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High
clock transition
q = Lower case letters indicate the state of the referenced
output one setup time prior to the Low-to-High clock
transition
X = Don’t care
↑ = Low-to-High clock transition
INPUTS OUTPUTS
n
n
*
L
STATE DIAGRAM
0 1 2 3
15
14
13
12 11 10 9
SF00664
SY00068
4
5
6
7
8
TYPICAL TIMING SEQUENCE
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
12 13 14 15 0 1 2
RESET PRESET
INHIBITCOUNT
SY00069
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
1998 May 20
4
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