Philips 74LVC163 User Guide

INTEGRATED CIRCUITS

DATA SH EET

74LVC163

Presettable synchronous 4-bit
binary counter; synchronous reset

Product specification
Supersedes data of 2003 June 02

2004 May 05

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; synchronous reset

FEATURES

• Wide supply voltage range from 1.2 V to 3.6 V

• Complies with JEDEC standard JESD8-B/JESD36

• Inputs accept voltages up to 5.5 V

• CMOS low power consumption

• Direct interface with TTL levels

• Synchronous reset

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive edge-triggered clock.

• ESD protection:

– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from−40 °C to +85 °C and −40 °C to +125 °C.

DESCRIPTION

The 74LVC163 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.

The 74LVC163 is a synchronous presettable binary
counterwhichfeaturesaninternal look-head carry andcan
be used for high-speed counting. Synchronous operation
is provided by having all flip-flops clocked simultaneously
on the positive-going edge of the clock (pin CP). The
outputs (pins Q0 to Q3) of the counters may be preset to a

74LVC163

HIGH-level or LOW-level. A LOW-level at the parallel
enable input (pin PE) disables the counting action and
causes the data at the data inputs (pins D0 to D3) to be
loaded into the counter on the positive-going edge of the
clock (provided that the set-up and hold time requirements
forPEaremet).Presettakesplace regardless of the levels
at count enable inputs (pins CEP and CET). A LOW-level
at the master reset input (pin MR) sets all four outputs of
the flip-flops (pins Q0 to Q3) to LOW-level after the next
positive-going transition on the clock input (pin CP)
(provided that the set-up and hold time requirements for
PE are met). This action occurs regardless of the levels at
input pins PE, CET and CEP. This synchronous reset
featureenablesthedesignerto modify the maximumcount
with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (pins CEP and CET)
must be HIGH to count. The CET input is fed forward to
enable the terminal count output (pin TC). The TC output
thus enabled will produce a HIGH output pulse of a
durationapproximatelyequaltoa HIGH-level output ofQ0.
Thispulsecanbeusedtoenablethenextcascadedstage.

The maximum clock frequency for the cascaded counters
is determined by t
(set-up time CEP to CP) according to the

formula: .f

max

(propagation delay CP to TC) and t

PHL

=

1

------------------------------------ ­t

PHL max()tsu

+

su

2004 May 05 2

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary

74LVC163

counter; synchronous reset

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

f

clk(max)

C

I

C

PD

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW).

PD

PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts;
N = total load switching outputs;
Σ(CL× V

2. The condition is VI= GND to VCC.

=25°C; tr=tf≤ 2.5 ns.

amb

propagation delay: CL= 50 pF; VCC= 3.3 V

CP to Qn 4.0 ns
CP to TC 4.6 ns

CET to TC 3.5 ns
maximum clock frequency 200 MHz
input capacitance 5.0 pF
power dissipation capacitance per gate notes 1 and 2 17 pF

2

× fi× N+Σ(CL× V

CC

2

× fo) = sum of the outputs.

CC

2

× fo) where:

CC

ORDERING INFORMATION

TYPE NUMBER

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74LVC163D −40 °C to +125 °C 16 SO16 plastic SOT109-1
74LVC163DB −40 °C to +125 °C 16 SSOP16 plastic SOT338-1
74LVC163PW −40 °C to +125 °C 16 TSSOP16 plastic SOT403-1
74LVC163BQ −40 °C to +125 °C 16 DHVQFN16 plastic SOT763-1

2004 May 05 3

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary

74LVC163

counter; synchronous reset

FUNCTION TABLE

See note 1.

OPERATING

MODES

Reset (clear) l ↑ XXXXLL
Parallel load h ↑ XX l l LL

Count h ↑ h h h X count *
Hold

(do nothing)

Note

1. * = the TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level.
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition.
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock

transition.
X = don’t care.
↑=LOW-to-HIGH clock transition.

MR CP CEP CET PE Dn Qn TC

h ↑ XX l hH*

hXlXhXqn*
hXXl hXqnL

INPUT OUTPUT

PINNING

PIN SYMBOL DESCRIPTION

1 MR synchronous master reset (active LOW)
2 CP clock input (LOW-to-HIGH, edge-triggered)
3 D0 data input
4 D1 data input
5 D2 data input
6 D3 data input
7 CEP count enable input
8 GND ground (0 V)

9 PE parallel enable input (active LOW)
10 CET count enable carry input
11 Q3 flip-flop output
12 Q2 flip-flop output
13 Q1 flip-flop output
14 Q0 flip-flop output
15 TC terminal count output
16 V

CC

supply voltage

2004 May 05 4

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; synchronous reset

MR V

1

CP TC

2

D0 Q0

3

D1 Q1

4

163

D2 Q2

5

D3 Q3

6

CEP CET

7

GND PE

8

001aaa770

16

CC

15

14

13

12

11

10

9

terminal 1

index area

CP TC

D0 Q0
D1 Q1
D2 Q2
D3 Q3

CEP CET

MR

1

2 15
3 14
4 13

163

5 12
6 11
7 10

Transparent top view

GND

(1)

8

GND

V
16

9

PE

CC

001aaa740

74LVC163

Fig.1 Pin configuration SO16 and (T)SSOP16.

handbook, halfpage

3
4
5
6
9

D0
D1
D2
D3
PE

CEP7CET

15

TC

Q0
Q1
Q2
Q3

MR

CP

MNA905

10

1

2

(1) The die substrate is attached to the exposed die pad using

conductivedie attach material.It cannot beused asasupply pin
or input.

Fig.2 Pin configuration DHVQFN16

handbook, halfpage

14
13
12
11

1
9
7

10

2

3
4
5
6

CTR4

R
M1
G3
G4

C2 /1,3,4+

1,2D

4 CT = 15

14
13
12
11

15

MNA906

Fig.3 Logic symbol.

2004 May 05 5

Fig.4 Logic symbol (IEEE/IEC).

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; synchronous reset

handbook, halfpage

PE

9

CET

10

CEP

7

CP

2

MR

1

3456

D0 D1 D2 D3

PARALLEL LOAD

CIRCUITRY

BINARY

COUNTER

Q0 Q1 Q2 Q3

14 13 12 11

Fig.5 Functional diagram.

TC

MNA907

74LVC163

handbook, halfpage

15

0

1 2 3 4

15

14

13

11 10 9 8

12

Fig.6 State diagram.

5

6

7

MNA908

handbook, full pagewidth

Typical timing sequence: Reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.

MR

PE

D0
D1
D2
D3

CP

CEP

CET

Q0
Q1
Q2
Q3
TC

12 13 14 15 0 1 2

RESET PRESET

INHIBITCOUNT

MGU760

Fig.7 Timing sequence.

2004 May 05 6

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2004 May 05 7

2004 May 05 7

D0 D1 D2 D3

CET

CEP

handbook, full pagewidth

Philips Semiconductors Product specification

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary

counter; synchronous reset

Presettable synchronous 4-bit binary

counter; synchronous reset

PE

MR

CP

D
CP

FF0

Q

Q

Q0

D
CP

FF1

Q

Q

Q1 Q2 Q3 TC

D
CP

FF2

Q

Q

D
CP

FF3

Q

Q

74LVC163

74LVC163

MGU761

Fig.8 Logic diagram.