Philips 74LVC16241ADL, 74LVC16241ADGG Datasheet

74LVC16241A
16-bit buffer/line driver (3-State)
Product specification Supersedes data of 1995 Dec 26 IC24 Data Handbook
 
1997 Jul 29
Philips Semiconductors Product specification
74L VC16241A16-bit buffer/line driver (3-State)
FEA TURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
DESCRIPTION
The 74LVC16241A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V . These features allow the use of these devices in a mixed 3.3V/5V environment.
The 74LVC16241A is a 16-bit buf fer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs nOE and nOE. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
PIN CONFIGURATION
1
1OE
2
1Y0
3
1Y1
4
GND
5
1Y2
6
1Y3
7
V
CC
2Y0
8
2Y1
9
GND
10 11
2Y2
12
2Y3
13
3Y0
14
3Y1
15
GND
16
3Y2
17
3Y3
18
V
CC
19
4Y0
20
4Y1
21
GND
22
4Y2
23
4Y3
24
4OE
48
47 46 45 44 43 42 41 40 39
38 37 36 35 34
33 32 31 30
29 28 27 26
25
SW00049
2OE
1A0 1A1 GND 1A2 1A3 V
CC
2A0 2A1 GND
2A2 2A3 3A0 3A1 GND
3A2 3A3 V
CC
4A0 4A1 GND 4A2 4A3 3OE
QUICK REFERENCE DA TA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
PD = CPD x V f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
= 25 C; tr = tf 2.5 ns
amb
Propagation delay nAn to nYn
Input capacitance 5.0 pF Power dissipation capacitance per buffer VI = GND to V
2
x fi +  (CL x V
CC
2
x V
x fo) = sum of outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
2
x fo) where:
CC
CL = 50pF VCC = 3.3V
CC
1
2.9 ns
25 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVC16241A DL VC16241A DL SOT370-1 48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVC16241A DGG VC16241A DGG SOT362-1
1997 Jul 29 853-2006 18217
2
Philips Semiconductors Product specification
16-bit buffer/line driver (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1OE
2, 3, 5, 6 1Y0 to 1Y3 Data outputs
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
GND Ground (0V)
CC
8, 9, 11, 12 2Y0 to 2Y3 Data outputs 13, 14, 16, 17 3Y0 to 3Y3 Data outputs 19, 20, 22, 23 4Y0 to 4Y3 Data outputs
24 4OE
25 3OE
30, 29, 27, 26 4A0 to 4A3 Data inputs 36, 35, 33, 32 3A0 to 3A3 Data inputs 41, 40, 38, 37 2A0 to 2A3 Data inputs 47, 46, 44, 43 1A0 to 1A3 Data inputs
48 2OE
Output enable input (active LOW)
Positive supply voltage
Output enable input (active LOW)
Output enable input (active LOW)
Output enable input (active LOW)
LOGIC SYMBOL (IEEE/IEC)
1OE 2OE 3OE 4OE
1A0 1A1 1A2 1A3 2A0 2A1 2A2 2A3 3A0
3A1 3A2 3A3 4A0 4A1 4A2 4A3
1 48 25 24
47 46
44 43 41
40 38 37 36 35 33 32
30 29
27 26
EN1 EN2 EN3 EN4
74LVC16241A
1
1
2 1
11
12
3 1
4 1
13 14
16 17 19 20 22 23
SW00055
2
1Y0
3
1Y1
5
1Y2
6
1Y3
8
2Y0
9
2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3
LOGIC SYMBOL
47
1A0
46
1A1
44
1A2
43
1A3
1
1OE
41
2A0
40
2A1
38
2A2
37
2A3
48
2OE
FUNCTION TABLES
2
1Y0
3A0
36
13
3Y0
nOE 1An, 4An 1Yn, 4Yn
3
1Y1
5
1Y2
6
1Y3
8
2Y0
9
2Y1
11
2Y2
3A1
3A2
3A3
3OE
4A0
4A1
4A2
35
33
32
25
30
29
27
14
3Y1
16
3Y2
17
3Y3
nOE 2An, 3An 2Yn, 3Yn
19
4Y0
20
4Y1
22
4Y2
H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state
12
2Y3
4A3
4OE
26
24
23
4Y3
SW00146
INPUTS OUTPUT
L H H L L L
H X Z
INPUTS OUTPUT
H H H H L L
L X Z
1997 Jul 29
3
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