Philips 74LVC162373A, 74LVCH162373A Technical data

INTEGRATED CIRCUITS

DATA SHEET

74LVC162373A;

74LVCH162373A

16-bit D-type transparent latch;

30 Ω series termination resistors;

5 V tolerant inputs/outputs; 3-state

Product specification			2004 Feb 05
Supersedes data of 1999 Aug 05

Philips Semiconductors	Product specification
16-bit D-type transparent latch; 30 Ω series termination	74LVC162373A;
resistors; 5 V tolerant inputs/outputs; 3-state	74LVCH162373A

FEATURES

∙5 V tolerant inputs/outputs for interfacing with 5 V logic

∙Wide supply voltage range from 1.2 to 3.6 V

∙CMOS low power consumption

∙MULTIBYTE flow-through standard pin-out architecture

∙Low inductance multiple power and ground pins for minimum noise and ground bounce

∙Direct interface with TTL levels

∙All data inputs have bushold (74LVCH162373A only)

∙High-impedance when VCC = 0 V

∙Complies with JEDEC standard no. 8-1A

∙ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.

∙Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (pin nLE) input and one output enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

The 74LVC(H)162373A consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding data inputs changes.

When pin nLE is LOW the latches store the information that was present at the data inputs a set-up time preceding the HIGH-to-LOW transition of pin nLE. When pin nOE is LOW, the contents of the eight latches are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.

The 74LVCH162373A bushold data inputs eliminates the need for external pull-up resistors to hold unused inputs.

The 74LVC(H)162373A is designed with 30 Ω series termination resistors in both high and low output stages to reduce line noise.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns

SYMBOL	PARAMETER					CONDITIONS	TYPICAL	UNIT
tPHL/tPLH	propagation delay nDn to nQn					CL = 50 pF; VCC = 3.3 V	3.3	ns
	propagation delay nLE to nQn					CL = 50 pF; VCC = 3.3 V	3.5	ns
tPZH/tPZL						CL = 50 pF; VCC = 3.3 V
	3-state output enable time nOE				to nQn		4.0	ns
tPHZ/tPLZ					to nQn	CL = 50 pF; VCC = 3.3 V	3.4	ns
	3-state output disable time nOE
CI	input capacitance						5.0	pF
CPD	power dissipation per latch					VCC = 3.3 V; notes 1 and 2
						outputs enabled	26	pF
						outputs disabled	19	pF

Notes

1.CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz;

CL = output load capacitance in pF;

2004 Feb 05

2

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination

74LVC162373A;

resistors; 5 V tolerant inputs/outputs; 3-state

74LVCH162373A

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

ORDERING INFORMATION

TYPE NUMBER

TEMPERATURE

PACKAGE

RANGE

PINS

PACKAGE

MATERIAL

CODE

74LVC162373ADGG

−40 to +125 °C

48

TSSOP48

plastic

SOT362-1

74LVCH162373ADGG

−40 to +125 °C

48

TSSOP48

plastic

SOT362-1

74LVC162373ADL

−40 to +125 °C

48

SSOP48

plastic

SOT370-1

74LVCH162373ADL

−40 to +125 °C

48

SSOP48

plastic

SOT370-1

FUNCTION TABLE

Per section of eight bits; note 1

OPERATING MODES

INPUT

INTERNAL

OUTPUT nQn

LATCH

nOE

nLE

nDn

Enable and read register (transparent mode)

L

H

L

L

L

L

H

H

H

H

Latch and read register

L

L

l

L

L

L

L

h

H

H

Latch register and disable outputs

H

L

l

L

Z

H

L

h

H

Z

Note

1.H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state.

2004 Feb 05

3

Philips Semiconductors	Product specification
16-bit D-type transparent latch; 30 Ω series termination	74LVC162373A;
resistors; 5 V tolerant inputs/outputs; 3-state	74LVCH162373A

PINNING

	SYMBOL			PIN	DESCRIPTION
				1	output enable input
1OE
					(active LOW)
1Q0				2	data output
1Q1				3	data output
GND				4, 10, 15, 21, 28,	ground (0 V)
				34, 39, 45
1Q2				5	data output
1Q3				6	data output
VCC				7, 18, 31, 42	supply voltage
1Q4				8	data output
1Q5				9	data output
1Q6				11	data output
1Q7				12	data output
2Q0				13	data output
2Q1				14	data output
2Q2				16	data output
2Q3				17	data output
2Q4				19	data output
2Q5				20	data output
2Q6				22	data output
2Q7				23	data output
				24	output enable input
2OE
					(active LOW)
2LE				25	latch enable input
					(active HIGH)
2D7				26	data input
2D6				27	data input
2D5				29	data input
2D4				30	data input
2D3				32	data input
2D2				33	data input
2D1				35	data input
2D0				36	data input
1D7				37	data input
1D6				38	data input
1D5				40	data input
1D4				41	data input
1D3				43	data input
1D2				44	data input

SYMBOL	PIN	DESCRIPTION
1D1	46	data input
1D0	47	data input
1LE	48	latch enable input
		(active HIGH)

1OE			1		48	1LE
1Q0
			2		47	1D0
1Q1
			3		46	1D1
GND
			4		45	GND
1Q2
			5		44	1D2
1Q3
			6		43	1D3
VCC						VCC
			7		42
1Q4
			8		41	1D4
1Q5
			9		40	1D5
GND
			10		39	GND
1Q6			11		38	1D6
1Q7			12	162373A	37	1D7
2Q0			13		36	2D0
2Q1			14		35	2D1
GND			15		34	GND
2Q2			16		33	2D2
2Q3			17		32	2D3
VCC						VCC
			18		31
2Q4			19		30	2D4
2Q5			20		29	2D5
GND			21		28	GND
2Q6			22		27	2D6
2Q7			23		26	2D7
2OE			24		25	2LE
				001aaa336

Fig.1 Pin configuration SSOP48 and TSSOP48.

2004 Feb 05

4

Philips Semiconductors	Product specification
16-bit D-type transparent latch; 30 Ω series termination	74LVC162373A;
resistors; 5 V tolerant inputs/outputs; 3-state	74LVCH162373A

1D0	D	Q	1Q0	2D0
	LATCH
		1
	LE	LE
1LE				2LE
1OE				2OE
	to 7 other channels

D	Q	2Q0
LATCH
	9
LE	LE
to 7 other channels
		MGU769

Fig.2 Logic diagram.

		1				24										1	1EN
													1OE
																48
													1LE				C3
																24
		1OE				2OE											2EN
													2OE
																25
47		1D0								1Q0		2	2LE				C4
46		1D1								1Q1		3	1D0			47					2	1Q0
44		1D2								1Q2		5					3D		1
																46					3
43		1D3								1Q3		6	1D1									1Q1
																44					5
41		1D4								1Q4		8	1D2									1Q2
																43					6
40		1D5								1Q5		9	1D3									1Q3
																41					8
38		1D6								1Q6		11	1D4									1Q4
																40					9
37		1D7								1Q7		12	1D5									1Q5
																38					11
36		2D0								2Q0		13	1D6									1Q6
																37					12
35		2D1								2Q1		14	1D7									1Q7
																36					13
33		2D2								2Q2		16	2D0				4D		2			2Q0
																35					14
32		2D3								2Q3		17	2D1									2Q1
																33					16
30		2D4								2Q4		19	2D2									2Q2
																32					17
29		2D5								2Q5		20	2D3									2Q3
																30					19
27		2D6								2Q6		22	2D4									2Q4
																29					20
26		2D7								2Q7		23	2D5									2Q5
																27					22
		1LE				2LE							2D6									2Q6
																26					23
											mgu768		2D7									2Q7
		48				25
																			mgu770

Fig.3 Logic symbol.

Fig.4 Logic symbol (IEEE/IEC).

2004 Feb 05

5

Philips Semiconductors Product specification

16-bit D-type transparent latch; 30 Ω series termination

74LVC162373A;

resistors; 5 V tolerant inputs/outputs; 3-state

74LVCH162373A

VCC

input

to internal circuit

MNA428

Fig.5 Bushold circuit.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

VCC

supply voltage

for maximum speed performance

2.7

3.6

V

for low-voltage applications

1.2

3.6

V

VI

input voltage

0

5.5

V

VO

output voltage

output HIGH or LOW state

0

VCC

V

output 3-state

0

5.5

V

Tamb

operating ambient temperature

in free-air

−40

+125

°C

tr, tf

input rise and fall times

VCC = 1.2 to 2.7 V

0

20

ns/V

VCC = 2.7 to 3.6 V

0

10

ns/V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCC	supply voltage		−0.5	+6.5	V
IIK	input diode current	VI < 0	−	−50	mA
VI	input voltage	note 1	−0.5	+6.5	V
IOK	output diode current	VO > VCC or VO < 0	−	±50	mA
VO	output voltage	output HIGH or LOW state; note 1	−0.5	VCC + 0.5	V
		output 3-state; note 1	−0.5	+6.5	V
IO	output source or sink current	VO = 0 to VCC	−	±50	mA
ICC, IGND	VCC or GND current		−	±100	mA
Tstg	storage temperature		−65	+150	°C
Ptot	power dissipation	Tamb = −40 to +125 °C; note 2	−	500	mW

Notes

1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

2004 Feb 05

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