Philips 74LVC157PW, 74LVC157DB, 74LVC157D, 74LVC157APW, 74LVC157ADB Datasheet
...
INTEGRATED CIRCUITS
74LVC157A
Quad 2-input multiplexer
Product specification |
1998 Jul 29 |
Supercedes data of 1997 Nov 07
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
|
|
|
|
|
|
|
Quad 2-input multiplexer |
74LVC157A |
|
|
|
|
|
|
|
FEATURES
•Wide supply voltage range of 1.2 to 3.6 V
•In accordance with JEDEC standard no. 8-1A
•CMOS lower power consumption
•Direct interface with TTL levels
•5 Volt tolerant inputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC157A is a high-performance, low-power, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC157A is a quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
input (S). The four outputs present the selected data in the true
(non-inverted) form. The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74LV157. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common.
The 74LVC157A is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S.
SYMBOL |
|
|
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
|
|
|
|
|
|
|
|
Propagation delay |
|
3.1 |
|
||
tPHL/tPLH |
nl0, nl1, to nY |
CL = 50 pF; |
ns |
|||
|
|
|
|
3.0 |
||
E to nY |
VCC = 3.3 V |
|||||
|
S to nY |
|
3.3 |
|
||
|
|
|
|
|
||
CI |
Input capacitance |
|
5.0 |
pF |
||
CPD |
Power dissipation capacitance per gate |
VI = GND to VCC1 |
33 |
pF |
||
NOTES:
1.CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD × VCC2 × fi S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
|
|
|
|
|
16-Pin Plastic SO |
±40°C to +85°C |
74LVC157A D |
74LVC157A D |
SOT109-1 |
|
|
|
|
|
16-Pin Plastic SSOP Type II |
±40°C to +85°C |
74LVC157A DB |
74LVC157A DB |
SOT338-1 |
|
|
|
|
|
16-Pin Plastic TSSOP Type I |
±40°C to +85°C |
74LVC157A PW |
74LVC157APW DH |
SOT403-1 |
PIN CONFIGURATION |
|
|
|
|
|
|
PIN DESCRIPTION |
|
||||||
|
|
|
|
|
|
|
|
|
|
PIN |
|
SYMBOL |
FUNCTION |
|
S |
1 |
|
|
16 |
|
VCC |
|
NUMBER |
|
|||||
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
|
S |
Common data select input |
|
1I 0 |
2 |
|
|
15 |
|
E |
||||||||
|
|
|
|
|
|
|
|
|
|
2, 5, 11, 14 |
|
1l0 to 4l0 |
Data inputs from sources 0 |
|
1I 1 |
3 |
|
|
14 |
|
4I 0 |
||||||||
|
|
|
|
|
|
|
|
|
|
3, 6, 10, 13 |
|
1l1 to 4l1 |
Data inputs from sources 1 |
|
1Y |
4 |
|
|
13 |
|
4I 1 |
||||||||
|
|
|
|
|
|
4, 7, 9, 12 |
|
1Y to 4Y |
Multiplexer outputs |
|||||
|
|
|
|
|
|
|
|
|
|
|
||||
2I 0 |
5 |
|
|
12 |
|
4Y |
|
8 |
|
GND |
Ground (0 V) |
|||
|
|
|
|
|
|
|
|
|
|
|
||||
2I 1 |
6 |
|
|
11 |
|
3I 0 |
|
|
|
|
|
|
||
|
|
|
|
15 |
|
E |
Enable input (active LOW) |
|||||||
|
|
|
|
|
|
|
|
|
|
|
||||
2Y |
7 |
|
|
10 |
|
3I 1 |
|
16 |
|
VCC |
Positive supply voltage |
|||
GND |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
8 |
|
|
9 |
|
3Y |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SV00563 |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1998 Jul 29 |
2 |
853-1945 19802 |
Philips Semiconductors |
Product specification |
|
|
|
|
Quad 2-input multiplexer |
74LVC157A |
|
|
|
|
LOGIC SYMBOL
|
2 |
3 |
5 |
6 |
11 |
10 |
14 |
13 |
|
1I0 |
1I1 |
2I0 |
2I1 |
3I0 |
3I1 |
4I0 |
4I1 |
1 |
S |
|
|
|
|
|
|
|
15 |
E |
|
|
|
|
|
|
|
|
|
|
1Y |
2Y |
3Y |
4Y |
|
|
|
|
|
4 |
7 |
9 |
12 |
|
|
|
|
|
|
|
|
|
|
SV00564 |
LOGIC SYMBOL (IEEE/IEC)
1 |
|
G1 |
|
|
||
|
|
|
|
|||
15 |
|
EN |
|
|
||
|
|
|
|
|||
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MUX |
||
1 |
|
|
||||
|
|
|
||||
|
|
|
|
|
||
4
3
1
5
7
6
11
9
10
14
12
13
SV00565
FUNCTIONAL DIAGRAM
2 |
1I 0 |
1Y |
4 |
|
3 |
1I 1 |
|||
|
|
|||
5 |
2I 0 |
|
7 |
|
6 |
2I 1 |
2Y |
||
|
|
|||
|
SELECTOR |
MULTIPLEXER |
|
|
11 |
OUTPUTS |
|
||
3I 0 |
9 |
|||
10 |
3I 1 |
3Y |
||
|
|
|||
14 |
4I 0 |
4Y |
12 |
|
13 |
4I 1 |
|||
|
|
|||
|
S |
E |
|
|
|
1 |
15 |
|
|
|
|
SV00566 |
||
FUNCTION TABLE
|
|
|
|
|
|
INPUTS |
|
|
OUTPUTS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S |
|
nl0 |
nl1 |
nY |
|
|
|
E |
|||||||
|
|
H |
|
X |
|
X |
X |
L |
||
|
|
|
L |
|
L |
|
L |
X |
L |
|
|
|
|
L |
|
L |
|
H |
X |
H |
|
|
|
|
L |
|
H |
|
X |
L |
L |
|
|
|
|
L |
|
H |
|
X |
H |
H |
|
|
|
|
|
|
|
|
|
|
||
NOTES: |
|
|
|
|
|
|||||
H |
= |
|
HIGH voltage level |
|
|
|
||||
L |
= |
|
LOW voltage level |
|
|
|
||||
X |
= |
|
don't care |
|
|
|
|
|
||
LOGIC DIAGRAM
S
E
1I1
1Y
1I0 
2I1
2Y
2I0 
3I1
3Y
3I0 
4I1
4Y
4I0 
SV00581
1998 Jul 29 |
3 |
Loading...