Philips Semiconductors Product specification
74L VC08AQuad 2-input AND gate
2
1997 Jun 30 853-1996 18167
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•In accordance with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
DESCRIPTION
The 74LVC08A is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
The 74LVC08A provides the 2-input AND function.
QUICK REFERENCE DA TA
GND = 0 V; T
amb
= 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLH
Propagation delay
nA, nB to nY
CL = 50 pF;
V
CC
= 3.3 V
2.6 ns
C
I
Input capacitance 5.0 pF
C
PD
Power dissipation capacitance per gate Notes 1 and 2 28 pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation
(P
D
in µW)
P
D
= CPD × V
CC
2
× fi (CL × V
CC
2
× fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
f
o
= output frequency in MHz; VCC = supply voltage in V;
(C
L
× V
CC
2
× fo) = sum of the outputs.
2. The condition is VI = GND to V
CC.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic SO –40°C to +85°C 74LVC08A D 74LVC08A D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC08A DB 74LVC08A DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC08A PW 74LVC08APW DH SOT402-1
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
V
CC
3B
3A
3Y
4Y
4B
4A
1A
1B
2Y
1Y
2A
2B
SY00034
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 4, 9, 12 1A – 4A