Philips 74LVC04APW, 74LVC04ADB, 74LVC04DB, 74LVC04D Datasheet

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Philips 74LVC04APW, 74LVC04ADB, 74LVC04DB, 74LVC04D Datasheet

INTEGRATED CIRCUITS

74LVC04A

Hex inverter

Product specification

1997 Jun 30

Supersedes data of 1997 Mar 28

IC24 Data Handbook

m n r

Philips Semiconductors

Product specification

 

 

 

 

 

Hex inverter

74LVC04A

 

 

 

 

 

 

FEATURES

Wide supply range of 1.2V to 3.6V

Complies with JEDEC standard no. 8-1A

Inputs accept voltages up to 5.5V

CMOS low power consumption

Direct interface with TTL levels

5-volt tolerant inputs, for interfacing with 5-volt logic

DESCRIPTION

The 74LVC04A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment.

The 74LVC04A provides six inverting buffers.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

 

 

 

 

 

tPHL/tPLH

Propagation delay

CL = 50 pF;

2.5

ns

nA to nY

VCC = 3.3 V

 

 

 

CI

Input capacitance

 

5.0

pF

CPD

Power dissipation capacitance per gate

Notes 1 and 2

25

pF

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in μW) PD = CPD VCC2 x fi (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;(CL VCC2 fo) = sum of the outputs.

2.The condition is VI = GND to VCC.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

 

 

 

 

 

14-Pin Plastic SO

±40°C to +85°C

74LVC04A D

74LVC04A D

SOT108-1

 

 

 

 

 

14-Pin Plastic SSOP Type II

±40°C to +85°C

74LVC04A DB

74LVC04A DB

SOT337-1

 

 

 

 

 

14-Pin Plastic TSSOP Type I

±40°C to +85°C

74LVC04A PW

74LVC04APW DH

SOT402-1

 

 

 

 

 

PIN CONFIGURATION

 

 

 

PIN DESCRIPTION

 

1A

1

 

14

VCC

 

PIN NUMBER

SYMBOL

NAME AND FUNCTION

 

 

 

 

 

 

 

 

1, 3, 5, 9, 11, 13

1A to 6A

Data inputs

1Y

2

 

13

6A

 

2, 4, 6, 8, 10, 12

1Y to 6Y

Data outputs

 

 

 

 

 

 

 

 

 

2A

3

 

12

6Y

 

7

GND

Ground (0 V)

 

 

 

 

 

 

 

 

 

2Y

4

 

11

5A

 

14

VCC

Positive supply voltage

3A

5

 

10

5Y

 

 

 

 

3Y

6

 

9

4A

 

 

 

 

GND

7

 

8

4Y

 

 

 

 

 

 

 

SV00396

 

 

 

 

 

 

 

 

 

 

 

1997 Jun 30

2

853-1953 18162

Philips Semiconductors

Product specification

 

 

 

Hex inverter

74LVC04A

 

 

 

LOGIC SYMBOL

1

1A

1Y

2

3

2A

2Y

4

5

3A

3Y

6

9

4A

4Y

8

11

5A

5Y

10

13

6A

6Y

12

LOGIC DIAGRAM (ONE GATE)

A

Y

 

SV00399

FUNCTION TABLE

INPUTS

OUTPUTS

 

 

nA

nY

 

 

L

H

H

L

 

 

NOTES:

H = HIGH voltage level

L = LOW voltage level

SV00397

LOGIC SYMBOL (IEEE/IEC)

 

1

1

2

 

 

3

4

 

1

 

 

5

6

 

1

 

 

9

8

 

1

 

11

10

1

 

 

 

 

13

12

1

 

 

SV00398

 

 

 

 

 

 

 

 

 

1997 Jun 30

3

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