Philips 74lvc04a DATASHEETS
INTEGRATED CIRCUITS
74LVC04A
Hex inverter
Product specification
Supersedes data of 1997 Mar 28
IC24 Data Handbook
1997 Jun 30
Philips Semiconductors Product specification
Hex inverter
FEA TURES
•Wide supply range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•5-volt tolerant inputs, for interfacing with 5-volt logic
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
2. The condition is V
= 25°C; tr = tf 2.5 ns
amb
Propagation delay
nA to nY
Input capacitance 5.0 pF
Power dissipation capacitance per gate Notes 1 and 2 25 pF
V
2
x fi (CL V
CC
2
fo) = sum of the outputs.
CC
= GND to V
I
CC.
2
fo) where:
CC
74L VC04A
DESCRIPTION
The 74LVC04A is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
The 74LVC04A provides six inverting buffers.
PARAMETER CONDITIONS TYPICAL UNIT
CL = 50 pF;
VCC = 3.3 V
2.5 ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic SO –40°C to +85°C 74LVC04A D 74LVC04A D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC04A DB 74LVC04A DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC04A PW 74LVC04APW DH SOT402-1
PIN CONFIGURATION
1
1A
2
1Y
3
2A
4
2Y
5
3A
6
3Y
GND
7
14
V
13
6A
12
6Y
11
5A
10
5Y
9
4A
8
4Y
SV00396
CC
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 3, 5, 9, 11, 13 1A to 6A Data inputs
2, 4, 6, 8, 10, 12 1Y to 6Y Data outputs
7 GND Ground (0 V)
14 V
Positive supply voltage
CC
1997 Jun 30 853-1953 18162
2
Philips Semiconductors Product specification
Hex inverter
LOGIC SYMBOL
1A 1Y
1
2A
3
5
3A 3Y
4A 4Y
9
11
5A 5Y
6A
13
LOGIC SYMBOL (IEEE/IEC)
2Y
6Y
SV00397
74LVC04A
LOGIC DIAGRAM (ONE GATE)
2
4
6
8
10
12
FUNCTION TABLE
NOTES:
H = HIGH voltage level
L = LOW voltage level
AY
SV00399
INPUTS OUTPUTS
nA nY
L H
H L
12
34
56
98
11 10
13 12
1
1
1
1
1
1
SV00398
1997 Jun 30
3
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