Philips 74LVC00APW, 74LVC00ADB, 74LVC00AD Datasheet

74LVC00A
Quad 2-input NAND gate
Product specification Supersedes data of 1997 Aug 11 IC24 Data Handbook
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1998 Apr 28
Philips Semiconductors Product specification
Data inputs
74L VC00AQuad 2-input NAND gate
FEA TURES
Wide supply range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
5-volt tolerant inputs, for interfacing with 5-volt logic
DESCRIPTION
The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times.
The 74LVC00A provides the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
= 25°C; tr =tf 2.5 ns
amb
t
PHL
t
PLH
C
I
C
PD
2
CC
2
V
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay nA, nB to nY
CL = 50 pF; VCC = 3.3 V
3.0 ns
Input capacitance 5.0 pF Power dissipation capacitance per gate VI = GND to V
x fi  (CL V
2
fo) where:
CC
CC
1
28 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic SO –40°C to +85°C 74LVC00A D 74LVC00A D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC00A DB 74LVC00A DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC00A PW 74LVC00APW DH SOT402-1
PIN CONFIGURATION
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
LOGIC SYMBOL (IEEE/IEC)
1 2
4 5
9
10
12 13
&
&
&
&
SY00034
SV00378
LOGIC SYMBOL
1A
14
V
CC
4B
13
4A
12
4Y
11
3B
10
3A
9
3Y
87
1
1B
2
2A
4
2B
5
3A
9
3B
10
4A
12
4B
13
1Y
3
2Y
6
3Y
8
4Y
11
SY00035
PIN DESCRIPTION
PIN
3
6
NUMBER
1, 4, 9, 12 1A – 4A
2, 5, 10, 13 1B – 4B
3, 6, 8, 11 1Y – 4Y Data outputs
8
7 GND Ground (0 V)
14 V
11
SYMBOL NAME AND FUNCTION
p
CC
Positive supply voltage
1998 Apr 28 853-2017 19310
2
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
mW
74LVC00AQuad 2-input NAND gate
LOGIC DIAGRAM (ONE GATE)
A
Y
B
SV00379
RECOMMENDED OPERATING CONDITIONS
T
V V
tr, t
CC CC
V
V
amb
O
DC supply voltage (for max. speed performance) 2.7 3.6 V DC supply voltage (for low-voltage applications) 1.2 3.6 V DC Input voltage range 0 5.5 V
I
DC output voltage range 0 V Operating ambient temperature range in free-air –40 +85 °C
Input rise and fall times
f
FUNCTION TABLE
nA nB nY
L L H
L H H H L H H H L
NOTES:
H = HIGH voltage level L =LOW voltage level
VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V
INPUTS OUTPUTS
LIMITS
MIN MAX
CC
0 0
20 10
V
ns/V
ABSOLUTE MAXIMUM RATINGS
1
Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
, I
GND
CC
T
stg
DC supply voltage (for max. speed performance)
DC input diode current VI 0 –50 mA DC input voltage Note 2 –0.5 to +5.5 V DC output diode current V DC output voltage Note 2 –0.5 to VCC + 0.5 V DC output source or sink current VO = 0 to V DC VCC or GND current 100 mA Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
–0.5 to +6.5 V
VCC or VO 0 50 mA
O
CC
50 mA
Power dissipation per package
P
TOT
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500 – plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
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